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1.1 root 1: /*
2: * Texas Instruments OMAP processors.
3: *
1.1.1.2 root 4: * Copyright (C) 2006-2008 Andrzej Zaborowski <[email protected]>
1.1 root 5: *
6: * This program is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU General Public License as
1.1.1.2 root 8: * published by the Free Software Foundation; either version 2 or
9: * (at your option) version 3 of the License.
1.1 root 10: *
11: * This program is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: * GNU General Public License for more details.
15: *
1.1.1.2 root 16: * You should have received a copy of the GNU General Public License along
1.1.1.3 root 17: * with this program; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #ifndef hw_omap_h
1.1.1.7 ! root 20: #include "memory.h"
1.1 root 21: # define hw_omap_h "omap.h"
22:
23: # define OMAP_EMIFS_BASE 0x00000000
1.1.1.2 root 24: # define OMAP2_Q0_BASE 0x00000000
1.1 root 25: # define OMAP_CS0_BASE 0x00000000
26: # define OMAP_CS1_BASE 0x04000000
27: # define OMAP_CS2_BASE 0x08000000
28: # define OMAP_CS3_BASE 0x0c000000
29: # define OMAP_EMIFF_BASE 0x10000000
30: # define OMAP_IMIF_BASE 0x20000000
31: # define OMAP_LOCALBUS_BASE 0x30000000
1.1.1.2 root 32: # define OMAP2_Q1_BASE 0x40000000
33: # define OMAP2_L4_BASE 0x48000000
34: # define OMAP2_SRAM_BASE 0x40200000
35: # define OMAP2_L3_BASE 0x68000000
36: # define OMAP2_Q2_BASE 0x80000000
37: # define OMAP2_Q3_BASE 0xc0000000
1.1 root 38: # define OMAP_MPUI_BASE 0xe1000000
39:
40: # define OMAP730_SRAM_SIZE 0x00032000
41: # define OMAP15XX_SRAM_SIZE 0x00030000
42: # define OMAP16XX_SRAM_SIZE 0x00004000
43: # define OMAP1611_SRAM_SIZE 0x0003e800
1.1.1.2 root 44: # define OMAP242X_SRAM_SIZE 0x000a0000
45: # define OMAP243X_SRAM_SIZE 0x00010000
1.1 root 46: # define OMAP_CS0_SIZE 0x04000000
47: # define OMAP_CS1_SIZE 0x04000000
48: # define OMAP_CS2_SIZE 0x04000000
49: # define OMAP_CS3_SIZE 0x04000000
50:
1.1.1.2 root 51: /* omap_clk.c */
1.1 root 52: struct omap_mpu_state_s;
53: typedef struct clk *omap_clk;
54: omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
55: void omap_clk_init(struct omap_mpu_state_s *mpu);
56: void omap_clk_adduser(struct clk *clk, qemu_irq user);
57: void omap_clk_get(omap_clk clk);
58: void omap_clk_put(omap_clk clk);
59: void omap_clk_onoff(omap_clk clk, int on);
60: void omap_clk_canidle(omap_clk clk, int can);
61: void omap_clk_setrate(omap_clk clk, int divide, int multiply);
62: int64_t omap_clk_getrate(omap_clk clk);
63: void omap_clk_reparent(omap_clk clk, omap_clk parent);
64:
1.1.1.5 root 65: /* OMAP2 l4 Interconnect */
1.1.1.2 root 66: struct omap_l4_s;
1.1.1.5 root 67: struct omap_l4_region_s {
68: target_phys_addr_t offset;
69: size_t size;
70: int access;
71: };
72: struct omap_l4_agent_info_s {
73: int ta;
74: int region;
75: int regions;
76: int ta_region;
77: };
78: struct omap_target_agent_s {
79: struct omap_l4_s *bus;
80: int regions;
81: const struct omap_l4_region_s *start;
82: target_phys_addr_t base;
83: uint32_t component;
84: uint32_t control;
85: uint32_t status;
86: };
1.1.1.2 root 87: struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
88:
89: struct omap_target_agent_s;
1.1.1.5 root 90: struct omap_target_agent_s *omap_l4ta_get(
91: struct omap_l4_s *bus,
92: const struct omap_l4_region_s *regions,
93: const struct omap_l4_agent_info_s *agents,
94: int cs);
1.1.1.2 root 95: target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
96: int iotype);
1.1.1.7 ! root 97: target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
! 98: int region);
1.1.1.5 root 99: int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
100: CPUWriteMemoryFunc * const *mem_write, void *opaque);
1.1.1.2 root 101:
1.1.1.5 root 102: /* OMAP2 SDRAM controller */
1.1.1.2 root 103: struct omap_sdrc_s;
104: struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
1.1.1.5 root 105: void omap_sdrc_reset(struct omap_sdrc_s *s);
1.1.1.2 root 106:
1.1.1.5 root 107: /* OMAP2 general purpose memory controller */
1.1.1.2 root 108: struct omap_gpmc_s;
1.1.1.7 ! root 109: struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
! 110: target_phys_addr_t base,
! 111: qemu_irq irq, qemu_irq drq);
1.1.1.5 root 112: void omap_gpmc_reset(struct omap_gpmc_s *s);
1.1.1.7 ! root 113: void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
! 114: void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
1.1 root 115:
116: /*
117: * Common IRQ numbers for level 1 interrupt handler
118: * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
119: */
120: # define OMAP_INT_CAMERA 1
121: # define OMAP_INT_FIQ 3
122: # define OMAP_INT_RTDX 6
123: # define OMAP_INT_DSP_MMU_ABORT 7
124: # define OMAP_INT_HOST 8
125: # define OMAP_INT_ABORT 9
126: # define OMAP_INT_BRIDGE_PRIV 13
127: # define OMAP_INT_GPIO_BANK1 14
128: # define OMAP_INT_UART3 15
129: # define OMAP_INT_TIMER3 16
130: # define OMAP_INT_DMA_CH0_6 19
131: # define OMAP_INT_DMA_CH1_7 20
132: # define OMAP_INT_DMA_CH2_8 21
133: # define OMAP_INT_DMA_CH3 22
134: # define OMAP_INT_DMA_CH4 23
135: # define OMAP_INT_DMA_CH5 24
136: # define OMAP_INT_DMA_LCD 25
137: # define OMAP_INT_TIMER1 26
138: # define OMAP_INT_WD_TIMER 27
139: # define OMAP_INT_BRIDGE_PUB 28
140: # define OMAP_INT_TIMER2 30
141: # define OMAP_INT_LCD_CTRL 31
142:
143: /*
144: * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
145: */
146: # define OMAP_INT_15XX_IH2_IRQ 0
147: # define OMAP_INT_15XX_LB_MMU 17
148: # define OMAP_INT_15XX_LOCAL_BUS 29
149:
150: /*
151: * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
152: */
153: # define OMAP_INT_1510_SPI_TX 4
154: # define OMAP_INT_1510_SPI_RX 5
155: # define OMAP_INT_1510_DSP_MAILBOX1 10
156: # define OMAP_INT_1510_DSP_MAILBOX2 11
157:
158: /*
159: * OMAP-310 specific IRQ numbers for level 1 interrupt handler
160: */
161: # define OMAP_INT_310_McBSP2_TX 4
162: # define OMAP_INT_310_McBSP2_RX 5
163: # define OMAP_INT_310_HSB_MAILBOX1 12
164: # define OMAP_INT_310_HSAB_MMU 18
165:
166: /*
167: * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
168: */
169: # define OMAP_INT_1610_IH2_IRQ 0
170: # define OMAP_INT_1610_IH2_FIQ 2
171: # define OMAP_INT_1610_McBSP2_TX 4
172: # define OMAP_INT_1610_McBSP2_RX 5
173: # define OMAP_INT_1610_DSP_MAILBOX1 10
174: # define OMAP_INT_1610_DSP_MAILBOX2 11
175: # define OMAP_INT_1610_LCD_LINE 12
176: # define OMAP_INT_1610_GPTIMER1 17
177: # define OMAP_INT_1610_GPTIMER2 18
178: # define OMAP_INT_1610_SSR_FIFO_0 29
179:
180: /*
181: * OMAP-730 specific IRQ numbers for level 1 interrupt handler
182: */
183: # define OMAP_INT_730_IH2_FIQ 0
184: # define OMAP_INT_730_IH2_IRQ 1
185: # define OMAP_INT_730_USB_NON_ISO 2
186: # define OMAP_INT_730_USB_ISO 3
187: # define OMAP_INT_730_ICR 4
188: # define OMAP_INT_730_EAC 5
189: # define OMAP_INT_730_GPIO_BANK1 6
190: # define OMAP_INT_730_GPIO_BANK2 7
191: # define OMAP_INT_730_GPIO_BANK3 8
192: # define OMAP_INT_730_McBSP2TX 10
193: # define OMAP_INT_730_McBSP2RX 11
194: # define OMAP_INT_730_McBSP2RX_OVF 12
195: # define OMAP_INT_730_LCD_LINE 14
196: # define OMAP_INT_730_GSM_PROTECT 15
197: # define OMAP_INT_730_TIMER3 16
198: # define OMAP_INT_730_GPIO_BANK5 17
199: # define OMAP_INT_730_GPIO_BANK6 18
200: # define OMAP_INT_730_SPGIO_WR 29
201:
202: /*
203: * Common IRQ numbers for level 2 interrupt handler
204: */
205: # define OMAP_INT_KEYBOARD 1
206: # define OMAP_INT_uWireTX 2
207: # define OMAP_INT_uWireRX 3
208: # define OMAP_INT_I2C 4
209: # define OMAP_INT_MPUIO 5
210: # define OMAP_INT_USB_HHC_1 6
211: # define OMAP_INT_McBSP3TX 10
212: # define OMAP_INT_McBSP3RX 11
213: # define OMAP_INT_McBSP1TX 12
214: # define OMAP_INT_McBSP1RX 13
215: # define OMAP_INT_UART1 14
216: # define OMAP_INT_UART2 15
217: # define OMAP_INT_USB_W2FC 20
218: # define OMAP_INT_1WIRE 21
219: # define OMAP_INT_OS_TIMER 22
220: # define OMAP_INT_OQN 23
221: # define OMAP_INT_GAUGE_32K 24
222: # define OMAP_INT_RTC_TIMER 25
223: # define OMAP_INT_RTC_ALARM 26
224: # define OMAP_INT_DSP_MMU 28
225:
226: /*
227: * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
228: */
229: # define OMAP_INT_1510_BT_MCSI1TX 16
230: # define OMAP_INT_1510_BT_MCSI1RX 17
231: # define OMAP_INT_1510_SoSSI_MATCH 19
232: # define OMAP_INT_1510_MEM_STICK 27
233: # define OMAP_INT_1510_COM_SPI_RO 31
234:
235: /*
236: * OMAP-310 specific IRQ numbers for level 2 interrupt handler
237: */
238: # define OMAP_INT_310_FAC 0
239: # define OMAP_INT_310_USB_HHC_2 7
240: # define OMAP_INT_310_MCSI1_FE 16
241: # define OMAP_INT_310_MCSI2_FE 17
242: # define OMAP_INT_310_USB_W2FC_ISO 29
243: # define OMAP_INT_310_USB_W2FC_NON_ISO 30
244: # define OMAP_INT_310_McBSP2RX_OF 31
245:
246: /*
247: * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
248: */
249: # define OMAP_INT_1610_FAC 0
250: # define OMAP_INT_1610_USB_HHC_2 7
251: # define OMAP_INT_1610_USB_OTG 8
252: # define OMAP_INT_1610_SoSSI 9
253: # define OMAP_INT_1610_BT_MCSI1TX 16
254: # define OMAP_INT_1610_BT_MCSI1RX 17
255: # define OMAP_INT_1610_SoSSI_MATCH 19
256: # define OMAP_INT_1610_MEM_STICK 27
257: # define OMAP_INT_1610_McBSP2RX_OF 31
258: # define OMAP_INT_1610_STI 32
259: # define OMAP_INT_1610_STI_WAKEUP 33
260: # define OMAP_INT_1610_GPTIMER3 34
261: # define OMAP_INT_1610_GPTIMER4 35
262: # define OMAP_INT_1610_GPTIMER5 36
263: # define OMAP_INT_1610_GPTIMER6 37
264: # define OMAP_INT_1610_GPTIMER7 38
265: # define OMAP_INT_1610_GPTIMER8 39
266: # define OMAP_INT_1610_GPIO_BANK2 40
267: # define OMAP_INT_1610_GPIO_BANK3 41
268: # define OMAP_INT_1610_MMC2 42
269: # define OMAP_INT_1610_CF 43
270: # define OMAP_INT_1610_WAKE_UP_REQ 46
271: # define OMAP_INT_1610_GPIO_BANK4 48
272: # define OMAP_INT_1610_SPI 49
273: # define OMAP_INT_1610_DMA_CH6 53
274: # define OMAP_INT_1610_DMA_CH7 54
275: # define OMAP_INT_1610_DMA_CH8 55
276: # define OMAP_INT_1610_DMA_CH9 56
277: # define OMAP_INT_1610_DMA_CH10 57
278: # define OMAP_INT_1610_DMA_CH11 58
279: # define OMAP_INT_1610_DMA_CH12 59
280: # define OMAP_INT_1610_DMA_CH13 60
281: # define OMAP_INT_1610_DMA_CH14 61
282: # define OMAP_INT_1610_DMA_CH15 62
283: # define OMAP_INT_1610_NAND 63
284:
285: /*
286: * OMAP-730 specific IRQ numbers for level 2 interrupt handler
287: */
288: # define OMAP_INT_730_HW_ERRORS 0
289: # define OMAP_INT_730_NFIQ_PWR_FAIL 1
290: # define OMAP_INT_730_CFCD 2
291: # define OMAP_INT_730_CFIREQ 3
292: # define OMAP_INT_730_I2C 4
293: # define OMAP_INT_730_PCC 5
294: # define OMAP_INT_730_MPU_EXT_NIRQ 6
295: # define OMAP_INT_730_SPI_100K_1 7
296: # define OMAP_INT_730_SYREN_SPI 8
297: # define OMAP_INT_730_VLYNQ 9
298: # define OMAP_INT_730_GPIO_BANK4 10
299: # define OMAP_INT_730_McBSP1TX 11
300: # define OMAP_INT_730_McBSP1RX 12
301: # define OMAP_INT_730_McBSP1RX_OF 13
302: # define OMAP_INT_730_UART_MODEM_IRDA_2 14
303: # define OMAP_INT_730_UART_MODEM_1 15
304: # define OMAP_INT_730_MCSI 16
305: # define OMAP_INT_730_uWireTX 17
306: # define OMAP_INT_730_uWireRX 18
307: # define OMAP_INT_730_SMC_CD 19
308: # define OMAP_INT_730_SMC_IREQ 20
309: # define OMAP_INT_730_HDQ_1WIRE 21
310: # define OMAP_INT_730_TIMER32K 22
311: # define OMAP_INT_730_MMC_SDIO 23
312: # define OMAP_INT_730_UPLD 24
313: # define OMAP_INT_730_USB_HHC_1 27
314: # define OMAP_INT_730_USB_HHC_2 28
315: # define OMAP_INT_730_USB_GENI 29
316: # define OMAP_INT_730_USB_OTG 30
317: # define OMAP_INT_730_CAMERA_IF 31
318: # define OMAP_INT_730_RNG 32
319: # define OMAP_INT_730_DUAL_MODE_TIMER 33
320: # define OMAP_INT_730_DBB_RF_EN 34
321: # define OMAP_INT_730_MPUIO_KEYPAD 35
322: # define OMAP_INT_730_SHA1_MD5 36
323: # define OMAP_INT_730_SPI_100K_2 37
324: # define OMAP_INT_730_RNG_IDLE 38
325: # define OMAP_INT_730_MPUIO 39
326: # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
327: # define OMAP_INT_730_LLPC_OE_FALLING 41
328: # define OMAP_INT_730_LLPC_OE_RISING 42
329: # define OMAP_INT_730_LLPC_VSYNC 43
330: # define OMAP_INT_730_WAKE_UP_REQ 46
331: # define OMAP_INT_730_DMA_CH6 53
332: # define OMAP_INT_730_DMA_CH7 54
333: # define OMAP_INT_730_DMA_CH8 55
334: # define OMAP_INT_730_DMA_CH9 56
335: # define OMAP_INT_730_DMA_CH10 57
336: # define OMAP_INT_730_DMA_CH11 58
337: # define OMAP_INT_730_DMA_CH12 59
338: # define OMAP_INT_730_DMA_CH13 60
339: # define OMAP_INT_730_DMA_CH14 61
340: # define OMAP_INT_730_DMA_CH15 62
341: # define OMAP_INT_730_NAND 63
342:
343: /*
344: * OMAP-24xx common IRQ numbers
345: */
1.1.1.2 root 346: # define OMAP_INT_24XX_STI 4
1.1 root 347: # define OMAP_INT_24XX_SYS_NIRQ 7
1.1.1.2 root 348: # define OMAP_INT_24XX_L3_IRQ 10
349: # define OMAP_INT_24XX_PRCM_MPU_IRQ 11
1.1 root 350: # define OMAP_INT_24XX_SDMA_IRQ0 12
351: # define OMAP_INT_24XX_SDMA_IRQ1 13
352: # define OMAP_INT_24XX_SDMA_IRQ2 14
353: # define OMAP_INT_24XX_SDMA_IRQ3 15
1.1.1.2 root 354: # define OMAP_INT_243X_MCBSP2_IRQ 16
355: # define OMAP_INT_243X_MCBSP3_IRQ 17
356: # define OMAP_INT_243X_MCBSP4_IRQ 18
357: # define OMAP_INT_243X_MCBSP5_IRQ 19
358: # define OMAP_INT_24XX_GPMC_IRQ 20
359: # define OMAP_INT_24XX_GUFFAW_IRQ 21
360: # define OMAP_INT_24XX_IVA_IRQ 22
361: # define OMAP_INT_24XX_EAC_IRQ 23
1.1 root 362: # define OMAP_INT_24XX_CAM_IRQ 24
363: # define OMAP_INT_24XX_DSS_IRQ 25
364: # define OMAP_INT_24XX_MAIL_U0_MPU 26
365: # define OMAP_INT_24XX_DSP_UMA 27
366: # define OMAP_INT_24XX_DSP_MMU 28
367: # define OMAP_INT_24XX_GPIO_BANK1 29
368: # define OMAP_INT_24XX_GPIO_BANK2 30
369: # define OMAP_INT_24XX_GPIO_BANK3 31
370: # define OMAP_INT_24XX_GPIO_BANK4 32
1.1.1.2 root 371: # define OMAP_INT_243X_GPIO_BANK5 33
1.1 root 372: # define OMAP_INT_24XX_MAIL_U3_MPU 34
1.1.1.2 root 373: # define OMAP_INT_24XX_WDT3 35
374: # define OMAP_INT_24XX_WDT4 36
1.1 root 375: # define OMAP_INT_24XX_GPTIMER1 37
376: # define OMAP_INT_24XX_GPTIMER2 38
377: # define OMAP_INT_24XX_GPTIMER3 39
378: # define OMAP_INT_24XX_GPTIMER4 40
379: # define OMAP_INT_24XX_GPTIMER5 41
380: # define OMAP_INT_24XX_GPTIMER6 42
381: # define OMAP_INT_24XX_GPTIMER7 43
382: # define OMAP_INT_24XX_GPTIMER8 44
383: # define OMAP_INT_24XX_GPTIMER9 45
384: # define OMAP_INT_24XX_GPTIMER10 46
385: # define OMAP_INT_24XX_GPTIMER11 47
386: # define OMAP_INT_24XX_GPTIMER12 48
1.1.1.2 root 387: # define OMAP_INT_24XX_PKA_IRQ 50
388: # define OMAP_INT_24XX_SHA1MD5_IRQ 51
389: # define OMAP_INT_24XX_RNG_IRQ 52
390: # define OMAP_INT_24XX_MG_IRQ 53
391: # define OMAP_INT_24XX_I2C1_IRQ 56
392: # define OMAP_INT_24XX_I2C2_IRQ 57
1.1 root 393: # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
394: # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
395: # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
396: # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
1.1.1.2 root 397: # define OMAP_INT_243X_MCBSP1_IRQ 64
398: # define OMAP_INT_24XX_MCSPI1_IRQ 65
399: # define OMAP_INT_24XX_MCSPI2_IRQ 66
400: # define OMAP_INT_24XX_SSI1_IRQ0 67
401: # define OMAP_INT_24XX_SSI1_IRQ1 68
402: # define OMAP_INT_24XX_SSI2_IRQ0 69
403: # define OMAP_INT_24XX_SSI2_IRQ1 70
404: # define OMAP_INT_24XX_SSI_GDD_IRQ 71
1.1 root 405: # define OMAP_INT_24XX_UART1_IRQ 72
406: # define OMAP_INT_24XX_UART2_IRQ 73
407: # define OMAP_INT_24XX_UART3_IRQ 74
408: # define OMAP_INT_24XX_USB_IRQ_GEN 75
409: # define OMAP_INT_24XX_USB_IRQ_NISO 76
410: # define OMAP_INT_24XX_USB_IRQ_ISO 77
411: # define OMAP_INT_24XX_USB_IRQ_HGEN 78
412: # define OMAP_INT_24XX_USB_IRQ_HSOF 79
413: # define OMAP_INT_24XX_USB_IRQ_OTG 80
1.1.1.2 root 414: # define OMAP_INT_24XX_VLYNQ_IRQ 81
1.1 root 415: # define OMAP_INT_24XX_MMC_IRQ 83
1.1.1.2 root 416: # define OMAP_INT_24XX_MS_IRQ 84
417: # define OMAP_INT_24XX_FAC_IRQ 85
418: # define OMAP_INT_24XX_MCSPI3_IRQ 91
1.1 root 419: # define OMAP_INT_243X_HS_USB_MC 92
420: # define OMAP_INT_243X_HS_USB_DMA 93
421: # define OMAP_INT_243X_CARKIT 94
1.1.1.2 root 422: # define OMAP_INT_34XX_GPTIMER12 95
1.1 root 423:
1.1.1.2 root 424: /* omap_dma.c */
1.1 root 425: enum omap_dma_model {
1.1.1.2 root 426: omap_dma_3_0,
427: omap_dma_3_1,
428: omap_dma_3_2,
429: omap_dma_4,
1.1 root 430: };
431:
1.1.1.2 root 432: struct soc_dma_s;
433: struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
1.1 root 434: qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
435: enum omap_dma_model model);
1.1.1.2 root 436: struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
437: struct omap_mpu_state_s *mpu, int fifo,
438: int chans, omap_clk iclk, omap_clk fclk);
439: void omap_dma_reset(struct soc_dma_s *s);
440:
441: struct dma_irq_map {
442: int ih;
443: int intr;
444: };
1.1 root 445:
1.1.1.2 root 446: /* Only used in OMAP DMA 3.x gigacells */
1.1 root 447: enum omap_dma_port {
448: emiff = 0,
449: emifs,
450: imif, /* omap16xx: ocp_t1 */
451: tipb,
452: local, /* omap16xx: ocp_t2 */
453: tipb_mpui,
1.1.1.2 root 454: __omap_dma_port_last,
1.1 root 455: };
456:
457: typedef enum {
458: constant = 0,
459: post_incremented,
460: single_index,
461: double_index,
462: } omap_dma_addressing_t;
463:
1.1.1.2 root 464: /* Only used in OMAP DMA 3.x gigacells */
1.1 root 465: struct omap_dma_lcd_channel_s {
466: enum omap_dma_port src;
467: target_phys_addr_t src_f1_top;
468: target_phys_addr_t src_f1_bottom;
469: target_phys_addr_t src_f2_top;
470: target_phys_addr_t src_f2_bottom;
471:
472: /* Used in OMAP DMA 3.2 gigacell */
473: unsigned char brust_f1;
474: unsigned char pack_f1;
475: unsigned char data_type_f1;
476: unsigned char brust_f2;
477: unsigned char pack_f2;
478: unsigned char data_type_f2;
479: unsigned char end_prog;
480: unsigned char repeat;
481: unsigned char auto_init;
482: unsigned char priority;
483: unsigned char fs;
484: unsigned char running;
485: unsigned char bs;
486: unsigned char omap_3_1_compatible_disable;
487: unsigned char dst;
488: unsigned char lch_type;
489: int16_t element_index_f1;
490: int16_t element_index_f2;
491: int32_t frame_index_f1;
492: int32_t frame_index_f2;
493: uint16_t elements_f1;
494: uint16_t frames_f1;
495: uint16_t elements_f2;
496: uint16_t frames_f2;
497: omap_dma_addressing_t mode_f1;
498: omap_dma_addressing_t mode_f2;
499:
500: /* Destination port is fixed. */
501: int interrupts;
502: int condition;
503: int dual;
504:
505: int current_frame;
1.1.1.3 root 506: target_phys_addr_t phys_framebuffer[2];
1.1 root 507: qemu_irq irq;
508: struct omap_mpu_state_s *mpu;
1.1.1.2 root 509: } *omap_dma_get_lcdch(struct soc_dma_s *s);
1.1 root 510:
511: /*
512: * DMA request numbers for OMAP1
513: * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
514: */
515: # define OMAP_DMA_NO_DEVICE 0
516: # define OMAP_DMA_MCSI1_TX 1
517: # define OMAP_DMA_MCSI1_RX 2
518: # define OMAP_DMA_I2C_RX 3
519: # define OMAP_DMA_I2C_TX 4
520: # define OMAP_DMA_EXT_NDMA_REQ0 5
521: # define OMAP_DMA_EXT_NDMA_REQ1 6
522: # define OMAP_DMA_UWIRE_TX 7
523: # define OMAP_DMA_MCBSP1_TX 8
524: # define OMAP_DMA_MCBSP1_RX 9
525: # define OMAP_DMA_MCBSP3_TX 10
526: # define OMAP_DMA_MCBSP3_RX 11
527: # define OMAP_DMA_UART1_TX 12
528: # define OMAP_DMA_UART1_RX 13
529: # define OMAP_DMA_UART2_TX 14
530: # define OMAP_DMA_UART2_RX 15
531: # define OMAP_DMA_MCBSP2_TX 16
532: # define OMAP_DMA_MCBSP2_RX 17
533: # define OMAP_DMA_UART3_TX 18
534: # define OMAP_DMA_UART3_RX 19
535: # define OMAP_DMA_CAMERA_IF_RX 20
536: # define OMAP_DMA_MMC_TX 21
537: # define OMAP_DMA_MMC_RX 22
538: # define OMAP_DMA_NAND 23 /* Not in OMAP310 */
539: # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
540: # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
541: # define OMAP_DMA_USB_W2FC_RX0 26
542: # define OMAP_DMA_USB_W2FC_RX1 27
543: # define OMAP_DMA_USB_W2FC_RX2 28
544: # define OMAP_DMA_USB_W2FC_TX0 29
545: # define OMAP_DMA_USB_W2FC_TX1 30
546: # define OMAP_DMA_USB_W2FC_TX2 31
547:
548: /* These are only for 1610 */
549: # define OMAP_DMA_CRYPTO_DES_IN 32
550: # define OMAP_DMA_SPI_TX 33
551: # define OMAP_DMA_SPI_RX 34
552: # define OMAP_DMA_CRYPTO_HASH 35
553: # define OMAP_DMA_CCP_ATTN 36
554: # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
555: # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
556: # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
557: # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
558: # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
559: # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
560: # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
561: # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
562: # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
563: # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
564: # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
565: # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
566: # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
567: # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
568: # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
569: # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
570: # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
571: # define OMAP_DMA_MMC2_TX 54
572: # define OMAP_DMA_MMC2_RX 55
573: # define OMAP_DMA_CRYPTO_DES_OUT 56
574:
1.1.1.2 root 575: /*
576: * DMA request numbers for the OMAP2
577: */
578: # define OMAP24XX_DMA_NO_DEVICE 0
579: # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
580: # define OMAP24XX_DMA_EXT_DMAREQ0 2
581: # define OMAP24XX_DMA_EXT_DMAREQ1 3
582: # define OMAP24XX_DMA_GPMC 4
583: # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
584: # define OMAP24XX_DMA_DSS 6
585: # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
586: # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
587: # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
588: # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
589: # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
590: # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
591: # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
592: # define OMAP24XX_DMA_EXT_DMAREQ2 14
593: # define OMAP24XX_DMA_EXT_DMAREQ3 15
594: # define OMAP24XX_DMA_EXT_DMAREQ4 16
595: # define OMAP24XX_DMA_EAC_AC_RD 17
596: # define OMAP24XX_DMA_EAC_AC_WR 18
597: # define OMAP24XX_DMA_EAC_MD_UL_RD 19
598: # define OMAP24XX_DMA_EAC_MD_UL_WR 20
599: # define OMAP24XX_DMA_EAC_MD_DL_RD 21
600: # define OMAP24XX_DMA_EAC_MD_DL_WR 22
601: # define OMAP24XX_DMA_EAC_BT_UL_RD 23
602: # define OMAP24XX_DMA_EAC_BT_UL_WR 24
603: # define OMAP24XX_DMA_EAC_BT_DL_RD 25
604: # define OMAP24XX_DMA_EAC_BT_DL_WR 26
605: # define OMAP24XX_DMA_I2C1_TX 27
606: # define OMAP24XX_DMA_I2C1_RX 28
607: # define OMAP24XX_DMA_I2C2_TX 29
608: # define OMAP24XX_DMA_I2C2_RX 30
609: # define OMAP24XX_DMA_MCBSP1_TX 31
610: # define OMAP24XX_DMA_MCBSP1_RX 32
611: # define OMAP24XX_DMA_MCBSP2_TX 33
612: # define OMAP24XX_DMA_MCBSP2_RX 34
613: # define OMAP24XX_DMA_SPI1_TX0 35
614: # define OMAP24XX_DMA_SPI1_RX0 36
615: # define OMAP24XX_DMA_SPI1_TX1 37
616: # define OMAP24XX_DMA_SPI1_RX1 38
617: # define OMAP24XX_DMA_SPI1_TX2 39
618: # define OMAP24XX_DMA_SPI1_RX2 40
619: # define OMAP24XX_DMA_SPI1_TX3 41
620: # define OMAP24XX_DMA_SPI1_RX3 42
621: # define OMAP24XX_DMA_SPI2_TX0 43
622: # define OMAP24XX_DMA_SPI2_RX0 44
623: # define OMAP24XX_DMA_SPI2_TX1 45
624: # define OMAP24XX_DMA_SPI2_RX1 46
625:
626: # define OMAP24XX_DMA_UART1_TX 49
627: # define OMAP24XX_DMA_UART1_RX 50
628: # define OMAP24XX_DMA_UART2_TX 51
629: # define OMAP24XX_DMA_UART2_RX 52
630: # define OMAP24XX_DMA_UART3_TX 53
631: # define OMAP24XX_DMA_UART3_RX 54
632: # define OMAP24XX_DMA_USB_W2FC_TX0 55
633: # define OMAP24XX_DMA_USB_W2FC_RX0 56
634: # define OMAP24XX_DMA_USB_W2FC_TX1 57
635: # define OMAP24XX_DMA_USB_W2FC_RX1 58
636: # define OMAP24XX_DMA_USB_W2FC_TX2 59
637: # define OMAP24XX_DMA_USB_W2FC_RX2 60
638: # define OMAP24XX_DMA_MMC1_TX 61
639: # define OMAP24XX_DMA_MMC1_RX 62
640: # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
641: # define OMAP24XX_DMA_EXT_DMAREQ5 64
642:
643: /* omap[123].c */
1.1.1.5 root 644: /* OMAP2 gp timer */
1.1.1.2 root 645: struct omap_gp_timer_s;
646: struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
647: qemu_irq irq, omap_clk fclk, omap_clk iclk);
1.1.1.5 root 648: void omap_gp_timer_reset(struct omap_gp_timer_s *s);
1.1.1.2 root 649:
1.1.1.5 root 650: /* OMAP2 sysctimer */
651: struct omap_synctimer_s;
652: struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
1.1.1.2 root 653: struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
1.1.1.5 root 654: void omap_synctimer_reset(struct omap_synctimer_s *s);
1.1 root 655:
656: struct omap_uart_s;
657: struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
1.1.1.2 root 658: qemu_irq irq, omap_clk fclk, omap_clk iclk,
1.1.1.6 root 659: qemu_irq txdma, qemu_irq rxdma,
660: const char *label, CharDriverState *chr);
1.1.1.2 root 661: struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
662: qemu_irq irq, omap_clk fclk, omap_clk iclk,
1.1.1.6 root 663: qemu_irq txdma, qemu_irq rxdma,
664: const char *label, CharDriverState *chr);
1.1.1.2 root 665: void omap_uart_reset(struct omap_uart_s *s);
666: void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
1.1 root 667:
668: struct omap_mpuio_s;
1.1.1.7 ! root 669: struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *system_memory,
! 670: target_phys_addr_t base,
1.1 root 671: qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
672: omap_clk clk);
673: qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
674: void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
675: void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
676:
1.1.1.3 root 677: struct uWireSlave {
1.1 root 678: uint16_t (*receive)(void *opaque);
679: void (*send)(void *opaque, uint16_t data);
680: void *opaque;
681: };
682: struct omap_uwire_s;
683: void omap_uwire_attach(struct omap_uwire_s *s,
1.1.1.3 root 684: uWireSlave *slave, int chipselect);
1.1 root 685:
1.1.1.5 root 686: /* OMAP2 spi */
1.1.1.2 root 687: struct omap_mcspi_s;
688: struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
689: qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
690: void omap_mcspi_attach(struct omap_mcspi_s *s,
691: uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
692: int chipselect);
1.1.1.5 root 693: void omap_mcspi_reset(struct omap_mcspi_s *s);
1.1 root 694:
1.1.1.3 root 695: struct I2SCodec {
1.1 root 696: void *opaque;
697:
698: /* The CPU can call this if it is generating the clock signal on the
699: * i2s port. The CODEC can ignore it if it is set up as a clock
700: * master and generates its own clock. */
701: void (*set_rate)(void *opaque, int in, int out);
702:
703: void (*tx_swallow)(void *opaque);
704: qemu_irq rx_swallow;
705: qemu_irq tx_start;
706:
707: int tx_rate;
708: int cts;
709: int rx_rate;
710: int rts;
711:
712: struct i2s_fifo_s {
713: uint8_t *fifo;
714: int len;
715: int start;
716: int size;
717: } in, out;
718: };
719: struct omap_mcbsp_s;
1.1.1.3 root 720: void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
1.1 root 721:
1.1.1.2 root 722: void omap_tap_init(struct omap_target_agent_s *ta,
723: struct omap_mpu_state_s *mpu);
724:
1.1 root 725: /* omap_lcdc.c */
726: struct omap_lcd_panel_s;
727: void omap_lcdc_reset(struct omap_lcd_panel_s *s);
728: struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
1.1.1.7 ! root 729: struct omap_dma_lcd_channel_s *dma, omap_clk clk);
1.1 root 730:
1.1.1.2 root 731: /* omap_dss.c */
732: struct rfbi_chip_s {
733: void *opaque;
734: void (*write)(void *opaque, int dc, uint16_t value);
735: void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
736: uint16_t (*read)(void *opaque, int dc);
737: };
738: struct omap_dss_s;
739: void omap_dss_reset(struct omap_dss_s *s);
740: struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
741: target_phys_addr_t l3_base,
742: qemu_irq irq, qemu_irq drq,
743: omap_clk fck1, omap_clk fck2, omap_clk ck54m,
744: omap_clk ick1, omap_clk ick2);
745: void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
746:
1.1 root 747: /* omap_mmc.c */
748: struct omap_mmc_s;
749: struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
750: BlockDriverState *bd,
751: qemu_irq irq, qemu_irq dma[], omap_clk clk);
1.1.1.2 root 752: struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
753: BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
754: omap_clk fclk, omap_clk iclk);
1.1 root 755: void omap_mmc_reset(struct omap_mmc_s *s);
756: void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
1.1.1.2 root 757: void omap_mmc_enable(struct omap_mmc_s *s, int enable);
1.1 root 758:
759: /* omap_i2c.c */
760: struct omap_i2c_s;
761: struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
762: qemu_irq irq, qemu_irq *dma, omap_clk clk);
1.1.1.2 root 763: struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
764: qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
1.1 root 765: void omap_i2c_reset(struct omap_i2c_s *s);
766: i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
767:
768: # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
769: # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
1.1.1.2 root 770: # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
771: # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
772: # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
773: # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
774: # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
775: # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
1.1.1.7 ! root 776: # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630)
1.1.1.2 root 777:
1.1 root 778: # define cpu_is_omap15xx(cpu) \
779: (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
1.1.1.2 root 780: # define cpu_is_omap16xx(cpu) \
781: (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
782: # define cpu_is_omap24xx(cpu) \
783: (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
784:
785: # define cpu_class_omap1(cpu) \
786: (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
787: # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
1.1.1.7 ! root 788: # define cpu_class_omap3(cpu) \
! 789: (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu))
1.1 root 790:
791: struct omap_mpu_state_s {
1.1.1.2 root 792: enum omap_mpu_model {
1.1 root 793: omap310,
794: omap1510,
1.1.1.2 root 795: omap1610,
796: omap1710,
797: omap2410,
798: omap2420,
799: omap2422,
800: omap2423,
801: omap2430,
802: omap3430,
1.1.1.7 ! root 803: omap3630,
1.1 root 804: } mpu_model;
805:
806: CPUState *env;
807:
808: qemu_irq *drq;
809:
810: qemu_irq wakeup;
811:
1.1.1.7 ! root 812: MemoryRegion ulpd_pm_iomem;
! 813: MemoryRegion pin_cfg_iomem;
! 814: MemoryRegion id_iomem;
! 815: MemoryRegion id_iomem_e18;
! 816: MemoryRegion id_iomem_ed4;
! 817: MemoryRegion id_iomem_e20;
! 818: MemoryRegion mpui_iomem;
! 819: MemoryRegion tcmi_iomem;
! 820: MemoryRegion clkm_iomem;
! 821: MemoryRegion clkdsp_iomem;
! 822: MemoryRegion pwl_iomem;
! 823: MemoryRegion pwt_iomem;
! 824: MemoryRegion mpui_io_iomem;
! 825: MemoryRegion imif_ram;
! 826: MemoryRegion emiff_ram;
! 827:
1.1 root 828: struct omap_dma_port_if_s {
829: uint32_t (*read[3])(struct omap_mpu_state_s *s,
830: target_phys_addr_t offset);
831: void (*write[3])(struct omap_mpu_state_s *s,
832: target_phys_addr_t offset, uint32_t value);
833: int (*addr_valid)(struct omap_mpu_state_s *s,
834: target_phys_addr_t addr);
1.1.1.2 root 835: } port[__omap_dma_port_last];
1.1 root 836:
837: unsigned long sdram_size;
838: unsigned long sram_size;
839:
840: /* MPUI-TIPB peripherals */
841: struct omap_uart_s *uart[3];
842:
1.1.1.7 ! root 843: DeviceState *gpio;
1.1 root 844:
845: struct omap_mcbsp_s *mcbsp1;
846: struct omap_mcbsp_s *mcbsp3;
847:
848: /* MPU public TIPB peripherals */
849: struct omap_32khz_timer_s *os_timer;
850:
851: struct omap_mmc_s *mmc;
852:
853: struct omap_mpuio_s *mpuio;
854:
855: struct omap_uwire_s *microwire;
856:
857: struct {
858: uint8_t output;
859: uint8_t level;
860: uint8_t enable;
861: int clk;
862: } pwl;
863:
864: struct {
865: uint8_t frc;
866: uint8_t vrc;
867: uint8_t gcr;
868: omap_clk clk;
869: } pwt;
870:
1.1.1.2 root 871: struct omap_i2c_s *i2c[2];
1.1 root 872:
873: struct omap_rtc_s *rtc;
874:
875: struct omap_mcbsp_s *mcbsp2;
876:
877: struct omap_lpg_s *led[2];
878:
879: /* MPU private TIPB peripherals */
1.1.1.7 ! root 880: DeviceState *ih[2];
1.1 root 881:
1.1.1.2 root 882: struct soc_dma_s *dma;
1.1 root 883:
884: struct omap_mpu_timer_s *timer[3];
885: struct omap_watchdog_timer_s *wdt;
886:
887: struct omap_lcd_panel_s *lcd;
888:
889: uint32_t ulpd_pm_regs[21];
890: int64_t ulpd_gauge_start;
891:
892: uint32_t func_mux_ctrl[14];
893: uint32_t comp_mode_ctrl[1];
894: uint32_t pull_dwn_ctrl[4];
895: uint32_t gate_inh_ctrl[1];
896: uint32_t voltage_ctrl[1];
897: uint32_t test_dbg_ctrl[1];
898: uint32_t mod_conf_ctrl[1];
899: int compat1509;
900:
901: uint32_t mpui_ctrl;
902:
903: struct omap_tipb_bridge_s *private_tipb;
904: struct omap_tipb_bridge_s *public_tipb;
905:
906: uint32_t tcmi_regs[17];
907:
908: struct dpll_ctl_s {
1.1.1.7 ! root 909: MemoryRegion iomem;
1.1 root 910: uint16_t mode;
911: omap_clk dpll;
912: } dpll[3];
913:
914: omap_clk clks;
915: struct {
916: int cold_start;
917: int clocking_scheme;
918: uint16_t arm_ckctl;
919: uint16_t arm_idlect1;
920: uint16_t arm_idlect2;
921: uint16_t arm_ewupct;
922: uint16_t arm_rstct1;
923: uint16_t arm_rstct2;
924: uint16_t arm_ckout1;
925: int dpll1_mode;
926: uint16_t dsp_idlect1;
927: uint16_t dsp_idlect2;
928: uint16_t dsp_rstct2;
929: } clkm;
1.1.1.2 root 930:
931: /* OMAP2-only peripherals */
932: struct omap_l4_s *l4;
933:
934: struct omap_gp_timer_s *gptimer[12];
1.1.1.5 root 935: struct omap_synctimer_s *synctimer;
1.1.1.2 root 936:
937: struct omap_prcm_s *prcm;
938: struct omap_sdrc_s *sdrc;
939: struct omap_gpmc_s *gpmc;
940: struct omap_sysctl_s *sysc;
941:
942: struct omap_mcspi_s *mcspi[2];
943:
944: struct omap_dss_s *dss;
945:
946: struct omap_eac_s *eac;
947: };
948:
949: /* omap1.c */
1.1.1.7 ! root 950: struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
! 951: unsigned long sdram_size,
1.1.1.2 root 952: const char *core);
953:
954: /* omap2.c */
955: struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
956: const char *core);
1.1 root 957:
958: # if TARGET_PHYS_ADDR_BITS == 32
959: # define OMAP_FMT_plx "%#08x"
960: # elif TARGET_PHYS_ADDR_BITS == 64
961: # define OMAP_FMT_plx "%#08" PRIx64
962: # else
963: # error TARGET_PHYS_ADDR_BITS undefined
964: # endif
965:
966: uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
967: void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
968: uint32_t value);
969: uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
970: void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
971: uint32_t value);
972: uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
973: void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
974: uint32_t value);
975:
1.1.1.2 root 976: void omap_mpu_wakeup(void *opaque, int irq, int req);
977:
1.1 root 978: # define OMAP_BAD_REG(paddr) \
1.1.1.2 root 979: fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
980: __FUNCTION__, paddr)
1.1 root 981: # define OMAP_RO_REG(paddr) \
1.1.1.2 root 982: fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
1.1 root 983: __FUNCTION__, paddr)
984:
1.1.1.2 root 985: /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
986: (Board-specifc tags are not here) */
987: #define OMAP_TAG_CLOCK 0x4f01
988: #define OMAP_TAG_MMC 0x4f02
989: #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
990: #define OMAP_TAG_USB 0x4f04
991: #define OMAP_TAG_LCD 0x4f05
992: #define OMAP_TAG_GPIO_SWITCH 0x4f06
993: #define OMAP_TAG_UART 0x4f07
994: #define OMAP_TAG_FBMEM 0x4f08
995: #define OMAP_TAG_STI_CONSOLE 0x4f09
996: #define OMAP_TAG_CAMERA_SENSOR 0x4f0a
997: #define OMAP_TAG_PARTITION 0x4f0b
998: #define OMAP_TAG_TEA5761 0x4f10
999: #define OMAP_TAG_TMP105 0x4f11
1000: #define OMAP_TAG_BOOT_REASON 0x4f80
1001: #define OMAP_TAG_FLASH_PART_STR 0x4f81
1002: #define OMAP_TAG_VERSION_STR 0x4f82
1003:
1004: enum {
1005: OMAP_GPIOSW_TYPE_COVER = 0 << 4,
1006: OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
1007: OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
1008: };
1009:
1010: #define OMAP_GPIOSW_INVERTED 0x0001
1011: #define OMAP_GPIOSW_OUTPUT 0x0002
1012:
1.1 root 1013: # define TCMI_VERBOSE 1
1014: //# define MEM_VERBOSE 1
1015:
1016: # ifdef TCMI_VERBOSE
1017: # define OMAP_8B_REG(paddr) \
1.1.1.2 root 1018: fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1.1 root 1019: __FUNCTION__, paddr)
1020: # define OMAP_16B_REG(paddr) \
1.1.1.2 root 1021: fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1.1 root 1022: __FUNCTION__, paddr)
1023: # define OMAP_32B_REG(paddr) \
1.1.1.2 root 1024: fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1.1 root 1025: __FUNCTION__, paddr)
1026: # else
1027: # define OMAP_8B_REG(paddr)
1028: # define OMAP_16B_REG(paddr)
1029: # define OMAP_32B_REG(paddr)
1030: # endif
1031:
1032: # define OMAP_MPUI_REG_MASK 0x000007ff
1033:
1034: # ifdef MEM_VERBOSE
1035: struct io_fn {
1.1.1.4 root 1036: CPUReadMemoryFunc * const *mem_read;
1037: CPUWriteMemoryFunc * const *mem_write;
1.1 root 1038: void *opaque;
1039: int in;
1040: };
1041:
1042: static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
1043: {
1044: struct io_fn *s = opaque;
1045: uint32_t ret;
1046:
1047: s->in ++;
1048: ret = s->mem_read[0](s->opaque, addr);
1049: s->in --;
1050: if (!s->in)
1051: fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
1052: return ret;
1053: }
1054: static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
1055: {
1056: struct io_fn *s = opaque;
1057: uint32_t ret;
1058:
1059: s->in ++;
1060: ret = s->mem_read[1](s->opaque, addr);
1061: s->in --;
1062: if (!s->in)
1063: fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
1064: return ret;
1065: }
1066: static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
1067: {
1068: struct io_fn *s = opaque;
1069: uint32_t ret;
1070:
1071: s->in ++;
1072: ret = s->mem_read[2](s->opaque, addr);
1073: s->in --;
1074: if (!s->in)
1075: fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
1076: return ret;
1077: }
1078: static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1079: {
1080: struct io_fn *s = opaque;
1081:
1082: if (!s->in)
1083: fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
1084: s->in ++;
1085: s->mem_write[0](s->opaque, addr, value);
1086: s->in --;
1087: }
1088: static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1089: {
1090: struct io_fn *s = opaque;
1091:
1092: if (!s->in)
1093: fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
1094: s->in ++;
1095: s->mem_write[1](s->opaque, addr, value);
1096: s->in --;
1097: }
1098: static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1099: {
1100: struct io_fn *s = opaque;
1101:
1102: if (!s->in)
1103: fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
1104: s->in ++;
1105: s->mem_write[2](s->opaque, addr, value);
1106: s->in --;
1107: }
1108:
1.1.1.4 root 1109: static CPUReadMemoryFunc * const io_readfn[] = { io_readb, io_readh, io_readw, };
1110: static CPUWriteMemoryFunc * const io_writefn[] = { io_writeb, io_writeh, io_writew, };
1.1 root 1111:
1.1.1.4 root 1112: inline static int debug_register_io_memory(CPUReadMemoryFunc * const *mem_read,
1113: CPUWriteMemoryFunc * const *mem_write,
1114: void *opaque)
1.1 root 1115: {
1.1.1.7 ! root 1116: struct io_fn *s = g_malloc(sizeof(struct io_fn));
1.1 root 1117:
1118: s->mem_read = mem_read;
1119: s->mem_write = mem_write;
1120: s->opaque = opaque;
1121: s->in = 0;
1.1.1.6 root 1122: return cpu_register_io_memory(io_readfn, io_writefn, s,
1123: DEVICE_NATIVE_ENDIAN);
1.1 root 1124: }
1125: # define cpu_register_io_memory debug_register_io_memory
1126: # endif
1127:
1.1.1.2 root 1128: /* Define when we want to reduce the number of IO regions registered. */
1129: /*# define L4_MUX_HACK*/
1130:
1.1 root 1131: #endif /* hw_omap_h */
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