Diff for /qemu/hw/omap_sx1.c between versions 1.1.1.7 and 1.1.1.8

version 1.1.1.7, 2018/04/24 19:29:17 version 1.1.1.8, 2018/04/24 19:49:29
Line 59 Line 59
  * - 1 RTC   * - 1 RTC
  */   */
   
 static uint32_t static_readb(void *opaque, target_phys_addr_t offset)  static uint64_t static_read(void *opaque, target_phys_addr_t offset,
                               unsigned size)
 {  {
     uint32_t *val = (uint32_t *) opaque;      uint32_t *val = (uint32_t *) opaque;
       uint32_t mask = (4 / size) - 1;
   
     return *val >> ((offset & 3) << 3);      return *val >> ((offset & mask) << 3);
 }  
   
 static uint32_t static_readh(void *opaque, target_phys_addr_t offset)  
 {  
     uint32_t *val = (uint32_t *) opaque;  
   
     return *val >> ((offset & 1) << 3);  
 }  
   
 static uint32_t static_readw(void *opaque, target_phys_addr_t offset)  
 {  
     uint32_t *val = (uint32_t *) opaque;  
   
     return *val >> ((offset & 0) << 3);  
 }  }
   
 static void static_write(void *opaque, target_phys_addr_t offset,  static void static_write(void *opaque, target_phys_addr_t offset,
                 uint32_t value)                           uint64_t value, unsigned size)
 {  {
 #ifdef SPY  #ifdef SPY
     printf("%s: value %08lx written at " PA_FMT "\n",      printf("%s: value %" PRIx64 " %u bytes written at 0x%x\n",
                     __FUNCTION__, value, offset);                      __func__, value, size, (int)offset);
 #endif  #endif
 }  }
   
 static CPUReadMemoryFunc * const static_readfn[] = {  static const MemoryRegionOps static_ops = {
     static_readb,      .read = static_read,
     static_readh,      .write = static_write,
     static_readw,      .endianness = DEVICE_NATIVE_ENDIAN,
 };  
   
 static CPUWriteMemoryFunc * const static_writefn[] = {  
     static_write,  
     static_write,  
     static_write,  
 };  };
   
 #define sdram_size      0x02000000  #define sdram_size      0x02000000
Line 123  static void sx1_init(ram_addr_t ram_size Line 105  static void sx1_init(ram_addr_t ram_size
 {  {
     struct omap_mpu_state_s *cpu;      struct omap_mpu_state_s *cpu;
     MemoryRegion *address_space = get_system_memory();      MemoryRegion *address_space = get_system_memory();
     int io;      MemoryRegion *flash = g_new(MemoryRegion, 1);
       MemoryRegion *flash_1 = g_new(MemoryRegion, 1);
       MemoryRegion *cs = g_new(MemoryRegion, 4);
     static uint32_t cs0val = 0x00213090;      static uint32_t cs0val = 0x00213090;
     static uint32_t cs1val = 0x00215070;      static uint32_t cs1val = 0x00215070;
     static uint32_t cs2val = 0x00001139;      static uint32_t cs2val = 0x00001139;
Line 140  static void sx1_init(ram_addr_t ram_size Line 124  static void sx1_init(ram_addr_t ram_size
     cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);      cpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model);
   
     /* External Flash (EMIFS) */      /* External Flash (EMIFS) */
     cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,      memory_region_init_ram(flash, "omap_sx1.flash0-0", flash_size);
                                  qemu_ram_alloc(NULL, "omap_sx1.flash0-0",      vmstate_register_ram_global(flash);
                                                 flash_size) | IO_MEM_ROM);      memory_region_set_readonly(flash, true);
       memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash);
     io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val,  
                                 DEVICE_NATIVE_ENDIAN);      memory_region_init_io(&cs[0], &static_ops, &cs0val,
     cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,                            "sx1.cs0", OMAP_CS0_SIZE - flash_size);
                     OMAP_CS0_SIZE - flash_size, io);      memory_region_add_subregion(address_space,
     io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val,                                  OMAP_CS0_BASE + flash_size, &cs[0]);
                                 DEVICE_NATIVE_ENDIAN);  
     cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);  
     io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val,      memory_region_init_io(&cs[2], &static_ops, &cs2val,
                                 DEVICE_NATIVE_ENDIAN);                            "sx1.cs2", OMAP_CS2_SIZE);
     cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);      memory_region_add_subregion(address_space,
                                   OMAP_CS2_BASE, &cs[2]);
   
       memory_region_init_io(&cs[3], &static_ops, &cs3val,
                             "sx1.cs3", OMAP_CS3_SIZE);
       memory_region_add_subregion(address_space,
                                   OMAP_CS2_BASE, &cs[3]);
   
     fl_idx = 0;      fl_idx = 0;
 #ifdef TARGET_WORDS_BIGENDIAN  #ifdef TARGET_WORDS_BIGENDIAN
Line 176  static void sx1_init(ram_addr_t ram_size Line 166  static void sx1_init(ram_addr_t ram_size
   
     if ((version == 1) &&      if ((version == 1) &&
             (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {              (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
         cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size,          memory_region_init_ram(flash_1, "omap_sx1.flash1-0", flash1_size);
                                      qemu_ram_alloc(NULL, "omap_sx1.flash1-0",          vmstate_register_ram_global(flash_1);
                                                     flash1_size) | IO_MEM_ROM);          memory_region_set_readonly(flash_1, true);
         io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,          memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1);
                                     DEVICE_NATIVE_ENDIAN);  
         cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,          memory_region_init_io(&cs[1], &static_ops, &cs1val,
                         OMAP_CS1_SIZE - flash1_size, io);                                "sx1.cs1", OMAP_CS1_SIZE - flash1_size);
           memory_region_add_subregion(address_space,
                                   OMAP_CS1_BASE + flash1_size, &cs[1]);
   
         if (!pflash_cfi01_register(OMAP_CS1_BASE, NULL,          if (!pflash_cfi01_register(OMAP_CS1_BASE, NULL,
                                    "omap_sx1.flash1-1", flash1_size,                                     "omap_sx1.flash1-1", flash1_size,
Line 194  static void sx1_init(ram_addr_t ram_size Line 186  static void sx1_init(ram_addr_t ram_size
         }          }
         fl_idx++;          fl_idx++;
     } else {      } else {
         io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val,          memory_region_init_io(&cs[1], &static_ops, &cs1val,
                                     DEVICE_NATIVE_ENDIAN);                                "sx1.cs1", OMAP_CS1_SIZE);
         cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);          memory_region_add_subregion(address_space,
                                   OMAP_CS1_BASE, &cs[1]);
     }      }
   
     if (!kernel_filename && !fl_idx) {      if (!kernel_filename && !fl_idx) {

Removed from v.1.1.1.7  
changed lines
  Added in v.1.1.1.8


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