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1.1 root 1: /* omap_sx1.c Support for the Siemens SX1 smartphone emulation.
2: *
3: * Copyright (C) 2008
4: * Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
5: * Copyright (C) 2007 Vladimir Ananiev <[email protected]>
6: *
7: * based on PalmOne's (TM) PDAs support (palm.c)
8: */
9:
10: /*
11: * PalmOne's (TM) PDAs.
12: *
13: * Copyright (C) 2006-2007 Andrzej Zaborowski <[email protected]>
14: *
15: * This program is free software; you can redistribute it and/or
16: * modify it under the terms of the GNU General Public License as
17: * published by the Free Software Foundation; either version 2 of
18: * the License, or (at your option) any later version.
19: *
20: * This program is distributed in the hope that it will be useful,
21: * but WITHOUT ANY WARRANTY; without even the implied warranty of
22: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23: * GNU General Public License for more details.
24: *
25: * You should have received a copy of the GNU General Public License along
1.1.1.2 ! root 26: * with this program; if not, see <http://www.gnu.org/licenses/>.
1.1 root 27: */
28: #include "hw.h"
29: #include "sysemu.h"
30: #include "console.h"
31: #include "omap.h"
32: #include "boards.h"
33: #include "arm-misc.h"
34: #include "flash.h"
35:
36: /*****************************************************************************/
37: /* Siemens SX1 Cellphone V1 */
38: /* - ARM OMAP310 processor
39: * - SRAM 192 kB
40: * - SDRAM 32 MB at 0x10000000
41: * - Boot flash 16 MB at 0x00000000
42: * - Application flash 8 MB at 0x04000000
43: * - 3 serial ports
44: * - 1 SecureDigital
45: * - 1 LCD display
46: * - 1 RTC
47: */
48:
49: /*****************************************************************************/
50: /* Siemens SX1 Cellphone V2 */
51: /* - ARM OMAP310 processor
52: * - SRAM 192 kB
53: * - SDRAM 32 MB at 0x10000000
54: * - Boot flash 32 MB at 0x00000000
55: * - 3 serial ports
56: * - 1 SecureDigital
57: * - 1 LCD display
58: * - 1 RTC
59: */
60:
61: static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
62: {
63: uint32_t *val = (uint32_t *) opaque;
64:
65: return *val >> ((offset & 3) << 3);
66: }
67:
68: static uint32_t static_readh(void *opaque, target_phys_addr_t offset)
69: {
70: uint32_t *val = (uint32_t *) opaque;
71:
72: return *val >> ((offset & 1) << 3);
73: }
74:
75: static uint32_t static_readw(void *opaque, target_phys_addr_t offset)
76: {
77: uint32_t *val = (uint32_t *) opaque;
78:
79: return *val >> ((offset & 0) << 3);
80: }
81:
82: static void static_write(void *opaque, target_phys_addr_t offset,
83: uint32_t value)
84: {
85: #ifdef SPY
86: printf("%s: value %08lx written at " PA_FMT "\n",
87: __FUNCTION__, value, offset);
88: #endif
89: }
90:
91: static CPUReadMemoryFunc *static_readfn[] = {
92: static_readb,
93: static_readh,
94: static_readw,
95: };
96:
97: static CPUWriteMemoryFunc *static_writefn[] = {
98: static_write,
99: static_write,
100: static_write,
101: };
102:
103: #define sdram_size 0x02000000
104: #define sector_size (128 * 1024)
105: #define flash0_size (16 * 1024 * 1024)
106: #define flash1_size ( 8 * 1024 * 1024)
107: #define flash2_size (32 * 1024 * 1024)
108: #define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE)
109: #define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE)
110:
111: static struct arm_boot_info sx1_binfo = {
112: .loader_start = OMAP_EMIFF_BASE,
113: .ram_size = sdram_size,
114: .board_id = 0x265,
115: };
116:
1.1.1.2 ! root 117: static void sx1_init(ram_addr_t ram_size,
1.1 root 118: const char *boot_device,
119: const char *kernel_filename, const char *kernel_cmdline,
120: const char *initrd_filename, const char *cpu_model,
121: const int version)
122: {
123: struct omap_mpu_state_s *cpu;
124: int io;
125: static uint32_t cs0val = 0x00213090;
126: static uint32_t cs1val = 0x00215070;
127: static uint32_t cs2val = 0x00001139;
128: static uint32_t cs3val = 0x00001139;
129: ram_addr_t phys_flash;
130: int index;
131: int fl_idx;
132: uint32_t flash_size = flash0_size;
133:
134: if (version == 2) {
135: flash_size = flash2_size;
136: }
137:
138: cpu = omap310_mpu_init(sx1_binfo.ram_size, cpu_model);
139:
140: /* External Flash (EMIFS) */
141: cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
142: (phys_flash = qemu_ram_alloc(flash_size)) | IO_MEM_ROM);
143:
1.1.1.2 ! root 144: io = cpu_register_io_memory(static_readfn, static_writefn, &cs0val);
1.1 root 145: cpu_register_physical_memory(OMAP_CS0_BASE + flash_size,
146: OMAP_CS0_SIZE - flash_size, io);
1.1.1.2 ! root 147: io = cpu_register_io_memory(static_readfn, static_writefn, &cs2val);
1.1 root 148: cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io);
1.1.1.2 ! root 149: io = cpu_register_io_memory(static_readfn, static_writefn, &cs3val);
1.1 root 150: cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io);
151:
152: fl_idx = 0;
153:
154: if ((index = drive_get_index(IF_PFLASH, 0, fl_idx)) > -1) {
155: if (!pflash_cfi01_register(OMAP_CS0_BASE, qemu_ram_alloc(flash_size),
156: drives_table[index].bdrv, sector_size, flash_size / sector_size,
157: 4, 0, 0, 0, 0)) {
158: fprintf(stderr, "qemu: Error registering flash memory %d.\n",
159: fl_idx);
160: }
161: fl_idx++;
162: }
163:
164: if ((version == 1) &&
165: (index = drive_get_index(IF_PFLASH, 0, fl_idx)) > -1) {
166: cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size,
167: (phys_flash = qemu_ram_alloc(flash1_size)) |
168: IO_MEM_ROM);
1.1.1.2 ! root 169: io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val);
1.1 root 170: cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,
171: OMAP_CS1_SIZE - flash1_size, io);
172:
173: if (!pflash_cfi01_register(OMAP_CS1_BASE, qemu_ram_alloc(flash1_size),
174: drives_table[index].bdrv, sector_size, flash1_size / sector_size,
175: 4, 0, 0, 0, 0)) {
176: fprintf(stderr, "qemu: Error registering flash memory %d.\n",
177: fl_idx);
178: }
179: fl_idx++;
180: } else {
1.1.1.2 ! root 181: io = cpu_register_io_memory(static_readfn, static_writefn, &cs1val);
1.1 root 182: cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io);
183: }
184:
185: if (!kernel_filename && !fl_idx) {
186: fprintf(stderr, "Kernel or Flash image must be specified\n");
187: exit(1);
188: }
189:
190: /* Load the kernel. */
191: if (kernel_filename) {
192: /* Start at bootloader. */
193: cpu->env->regs[15] = sx1_binfo.loader_start;
194:
195: sx1_binfo.kernel_filename = kernel_filename;
196: sx1_binfo.kernel_cmdline = kernel_cmdline;
197: sx1_binfo.initrd_filename = initrd_filename;
198: arm_load_kernel(cpu->env, &sx1_binfo);
199: } else {
200: cpu->env->regs[15] = 0x00000000;
201: }
202:
203: /* TODO: fix next line */
204: //~ qemu_console_resize(ds, 640, 480);
205: }
206:
1.1.1.2 ! root 207: static void sx1_init_v1(ram_addr_t ram_size,
1.1 root 208: const char *boot_device,
209: const char *kernel_filename, const char *kernel_cmdline,
210: const char *initrd_filename, const char *cpu_model)
211: {
1.1.1.2 ! root 212: sx1_init(ram_size, boot_device, kernel_filename,
1.1 root 213: kernel_cmdline, initrd_filename, cpu_model, 1);
214: }
215:
1.1.1.2 ! root 216: static void sx1_init_v2(ram_addr_t ram_size,
1.1 root 217: const char *boot_device,
218: const char *kernel_filename, const char *kernel_cmdline,
219: const char *initrd_filename, const char *cpu_model)
220: {
1.1.1.2 ! root 221: sx1_init(ram_size, boot_device, kernel_filename,
1.1 root 222: kernel_cmdline, initrd_filename, cpu_model, 2);
223: }
224:
1.1.1.2 ! root 225: static QEMUMachine sx1_machine_v2 = {
1.1 root 226: .name = "sx1",
227: .desc = "Siemens SX1 (OMAP310) V2",
228: .init = sx1_init_v2,
229: };
230:
1.1.1.2 ! root 231: static QEMUMachine sx1_machine_v1 = {
1.1 root 232: .name = "sx1-v1",
233: .desc = "Siemens SX1 (OMAP310) V1",
234: .init = sx1_init_v1,
235: };
1.1.1.2 ! root 236:
! 237: static void sx1_machine_init(void)
! 238: {
! 239: qemu_register_machine(&sx1_machine_v2);
! 240: qemu_register_machine(&sx1_machine_v1);
! 241: }
! 242:
! 243: machine_init(sx1_machine_init);
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