--- qemu/hw/omap_synctimer.c 2018/04/24 18:28:00 1.1 +++ qemu/hw/omap_synctimer.c 2018/04/24 19:46:31 1.1.1.4 @@ -21,13 +21,14 @@ #include "qemu-timer.h" #include "omap.h" struct omap_synctimer_s { + MemoryRegion iomem; uint32_t val; uint16_t readh; }; /* 32-kHz Sync Timer of the OMAP2 */ static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) { - return muldiv64(qemu_get_clock(vm_clock), 0x8000, get_ticks_per_sec()); + return muldiv64(qemu_get_clock_ns(vm_clock), 0x8000, get_ticks_per_sec()); } void omap_synctimer_reset(struct omap_synctimer_s *s) @@ -65,32 +66,37 @@ static uint32_t omap_synctimer_readh(voi } } -static CPUReadMemoryFunc * const omap_synctimer_readfn[] = { - omap_badwidth_read32, - omap_synctimer_readh, - omap_synctimer_readw, -}; - static void omap_synctimer_write(void *opaque, target_phys_addr_t addr, uint32_t value) { OMAP_BAD_REG(addr); } -static CPUWriteMemoryFunc * const omap_synctimer_writefn[] = { - omap_badwidth_write32, - omap_synctimer_write, - omap_synctimer_write, +static const MemoryRegionOps omap_synctimer_ops = { + .old_mmio = { + .read = { + omap_badwidth_read32, + omap_synctimer_readh, + omap_synctimer_readw, + }, + .write = { + omap_badwidth_write32, + omap_synctimer_write, + omap_synctimer_write, + }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk) { - struct omap_synctimer_s *s = qemu_mallocz(sizeof(*s)); + struct omap_synctimer_s *s = g_malloc0(sizeof(*s)); omap_synctimer_reset(s); - omap_l4_attach(ta, 0, l4_register_io_memory( - omap_synctimer_readfn, omap_synctimer_writefn, s)); + memory_region_init_io(&s->iomem, &omap_synctimer_ops, s, "omap.synctimer", + omap_l4_region_size(ta, 0)); + omap_l4_attach(ta, 0, &s->iomem); return s; }