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1.1 root 1: /*
2: * TI OMAP processors UART emulation.
3: *
4: * Copyright (C) 2006-2008 Andrzej Zaborowski <[email protected]>
5: * Copyright (C) 2007-2009 Nokia Corporation
6: *
7: * This program is free software; you can redistribute it and/or
8: * modify it under the terms of the GNU General Public License as
9: * published by the Free Software Foundation; either version 2 or
10: * (at your option) version 3 of the License.
11: *
12: * This program is distributed in the hope that it will be useful,
13: * but WITHOUT ANY WARRANTY; without even the implied warranty of
14: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: * GNU General Public License for more details.
16: *
17: * You should have received a copy of the GNU General Public License along
18: * with this program; if not, see <http://www.gnu.org/licenses/>.
19: */
20: #include "qemu-char.h"
21: #include "hw.h"
22: #include "omap.h"
23: /* We use pc-style serial ports. */
24: #include "pc.h"
1.1.1.3 root 25: #include "exec-memory.h"
1.1 root 26:
27: /* UARTs */
28: struct omap_uart_s {
1.1.1.4 ! root 29: MemoryRegion iomem;
1.1 root 30: target_phys_addr_t base;
31: SerialState *serial; /* TODO */
32: struct omap_target_agent_s *ta;
33: omap_clk fclk;
34: qemu_irq irq;
35:
36: uint8_t eblr;
37: uint8_t syscontrol;
38: uint8_t wkup;
39: uint8_t cfps;
40: uint8_t mdr[2];
41: uint8_t scr;
42: uint8_t clksel;
43: };
44:
45: void omap_uart_reset(struct omap_uart_s *s)
46: {
47: s->eblr = 0x00;
48: s->syscontrol = 0;
49: s->wkup = 0x3f;
50: s->cfps = 0x69;
51: s->clksel = 0;
52: }
53:
54: struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
55: qemu_irq irq, omap_clk fclk, omap_clk iclk,
1.1.1.2 root 56: qemu_irq txdma, qemu_irq rxdma,
57: const char *label, CharDriverState *chr)
1.1 root 58: {
59: struct omap_uart_s *s = (struct omap_uart_s *)
1.1.1.3 root 60: g_malloc0(sizeof(struct omap_uart_s));
1.1 root 61:
62: s->base = base;
63: s->fclk = fclk;
64: s->irq = irq;
1.1.1.3 root 65: s->serial = serial_mm_init(get_system_memory(), base, 2, irq,
66: omap_clk_getrate(fclk)/16,
67: chr ?: qemu_chr_new(label, "null", NULL),
68: DEVICE_NATIVE_ENDIAN);
1.1 root 69: return s;
70: }
71:
1.1.1.4 ! root 72: static uint64_t omap_uart_read(void *opaque, target_phys_addr_t addr,
! 73: unsigned size)
1.1 root 74: {
75: struct omap_uart_s *s = (struct omap_uart_s *) opaque;
76:
1.1.1.4 ! root 77: if (size == 4) {
! 78: return omap_badwidth_read8(opaque, addr);
! 79: }
! 80:
1.1 root 81: switch (addr) {
82: case 0x20: /* MDR1 */
83: return s->mdr[0];
84: case 0x24: /* MDR2 */
85: return s->mdr[1];
86: case 0x40: /* SCR */
87: return s->scr;
88: case 0x44: /* SSR */
89: return 0x0;
90: case 0x48: /* EBLR (OMAP2) */
91: return s->eblr;
92: case 0x4C: /* OSC_12M_SEL (OMAP1) */
93: return s->clksel;
94: case 0x50: /* MVR */
95: return 0x30;
96: case 0x54: /* SYSC (OMAP2) */
97: return s->syscontrol;
98: case 0x58: /* SYSS (OMAP2) */
99: return 1;
100: case 0x5c: /* WER (OMAP2) */
101: return s->wkup;
102: case 0x60: /* CFPS (OMAP2) */
103: return s->cfps;
104: }
105:
106: OMAP_BAD_REG(addr);
107: return 0;
108: }
109:
110: static void omap_uart_write(void *opaque, target_phys_addr_t addr,
1.1.1.4 ! root 111: uint64_t value, unsigned size)
1.1 root 112: {
113: struct omap_uart_s *s = (struct omap_uart_s *) opaque;
114:
1.1.1.4 ! root 115: if (size == 4) {
! 116: return omap_badwidth_write8(opaque, addr, value);
! 117: }
! 118:
1.1 root 119: switch (addr) {
120: case 0x20: /* MDR1 */
121: s->mdr[0] = value & 0x7f;
122: break;
123: case 0x24: /* MDR2 */
124: s->mdr[1] = value & 0xff;
125: break;
126: case 0x40: /* SCR */
127: s->scr = value & 0xff;
128: break;
129: case 0x48: /* EBLR (OMAP2) */
130: s->eblr = value & 0xff;
131: break;
132: case 0x4C: /* OSC_12M_SEL (OMAP1) */
133: s->clksel = value & 1;
134: break;
135: case 0x44: /* SSR */
136: case 0x50: /* MVR */
137: case 0x58: /* SYSS (OMAP2) */
138: OMAP_RO_REG(addr);
139: break;
140: case 0x54: /* SYSC (OMAP2) */
141: s->syscontrol = value & 0x1d;
142: if (value & 2)
143: omap_uart_reset(s);
144: break;
145: case 0x5c: /* WER (OMAP2) */
146: s->wkup = value & 0x7f;
147: break;
148: case 0x60: /* CFPS (OMAP2) */
149: s->cfps = value & 0xff;
150: break;
151: default:
152: OMAP_BAD_REG(addr);
153: }
154: }
155:
1.1.1.4 ! root 156: static const MemoryRegionOps omap_uart_ops = {
! 157: .read = omap_uart_read,
! 158: .write = omap_uart_write,
! 159: .endianness = DEVICE_NATIVE_ENDIAN,
1.1 root 160: };
161:
1.1.1.4 ! root 162: struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
! 163: struct omap_target_agent_s *ta,
1.1 root 164: qemu_irq irq, omap_clk fclk, omap_clk iclk,
1.1.1.2 root 165: qemu_irq txdma, qemu_irq rxdma,
166: const char *label, CharDriverState *chr)
1.1 root 167: {
1.1.1.4 ! root 168: target_phys_addr_t base = omap_l4_attach(ta, 0, NULL);
1.1 root 169: struct omap_uart_s *s = omap_uart_init(base, irq,
1.1.1.2 root 170: fclk, iclk, txdma, rxdma, label, chr);
1.1.1.4 ! root 171:
! 172: memory_region_init_io(&s->iomem, &omap_uart_ops, s, "omap.uart", 0x100);
1.1 root 173:
174: s->ta = ta;
175:
1.1.1.4 ! root 176: memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
1.1 root 177:
178: return s;
179: }
180:
181: void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
182: {
183: /* TODO: Should reuse or destroy current s->serial */
1.1.1.3 root 184: s->serial = serial_mm_init(get_system_memory(), s->base, 2, s->irq,
1.1 root 185: omap_clk_getrate(s->fclk) / 16,
1.1.1.3 root 186: chr ?: qemu_chr_new("null", "null", NULL),
187: DEVICE_NATIVE_ENDIAN);
1.1 root 188: }
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