File:  [Qemu by Fabrice Bellard] / qemu / hw / omap_uart.c
Revision 1.1.1.2 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 18:38:55 2018 UTC (2 years, 3 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu1000, qemu0151, qemu0150, qemu0141, qemu0140, HEAD
qemu 0.14.0

    1: /*
    2:  * TI OMAP processors UART emulation.
    3:  *
    4:  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
    5:  * Copyright (C) 2007-2009 Nokia Corporation
    6:  *
    7:  * This program is free software; you can redistribute it and/or
    8:  * modify it under the terms of the GNU General Public License as
    9:  * published by the Free Software Foundation; either version 2 or
   10:  * (at your option) version 3 of the License.
   11:  *
   12:  * This program is distributed in the hope that it will be useful,
   13:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   14:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   15:  * GNU General Public License for more details.
   16:  *
   17:  * You should have received a copy of the GNU General Public License along
   18:  * with this program; if not, see <http://www.gnu.org/licenses/>.
   19:  */
   20: #include "qemu-char.h"
   21: #include "hw.h"
   22: #include "omap.h"
   23: /* We use pc-style serial ports.  */
   24: #include "pc.h"
   25: 
   26: /* UARTs */
   27: struct omap_uart_s {
   28:     target_phys_addr_t base;
   29:     SerialState *serial; /* TODO */
   30:     struct omap_target_agent_s *ta;
   31:     omap_clk fclk;
   32:     qemu_irq irq;
   33: 
   34:     uint8_t eblr;
   35:     uint8_t syscontrol;
   36:     uint8_t wkup;
   37:     uint8_t cfps;
   38:     uint8_t mdr[2];
   39:     uint8_t scr;
   40:     uint8_t clksel;
   41: };
   42: 
   43: void omap_uart_reset(struct omap_uart_s *s)
   44: {
   45:     s->eblr = 0x00;
   46:     s->syscontrol = 0;
   47:     s->wkup = 0x3f;
   48:     s->cfps = 0x69;
   49:     s->clksel = 0;
   50: }
   51: 
   52: struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
   53:                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
   54:                 qemu_irq txdma, qemu_irq rxdma,
   55:                 const char *label, CharDriverState *chr)
   56: {
   57:     struct omap_uart_s *s = (struct omap_uart_s *)
   58:             qemu_mallocz(sizeof(struct omap_uart_s));
   59: 
   60:     s->base = base;
   61:     s->fclk = fclk;
   62:     s->irq = irq;
   63: #ifdef TARGET_WORDS_BIGENDIAN
   64:     s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
   65:                                chr ?: qemu_chr_open(label, "null", NULL), 1,
   66:                                1);
   67: #else
   68:     s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
   69:                                chr ?: qemu_chr_open(label, "null", NULL), 1,
   70:                                0);
   71: #endif
   72:     return s;
   73: }
   74: 
   75: static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr)
   76: {
   77:     struct omap_uart_s *s = (struct omap_uart_s *) opaque;
   78: 
   79:     addr &= 0xff;
   80:     switch (addr) {
   81:     case 0x20:	/* MDR1 */
   82:         return s->mdr[0];
   83:     case 0x24:	/* MDR2 */
   84:         return s->mdr[1];
   85:     case 0x40:	/* SCR */
   86:         return s->scr;
   87:     case 0x44:	/* SSR */
   88:         return 0x0;
   89:     case 0x48:	/* EBLR (OMAP2) */
   90:         return s->eblr;
   91:     case 0x4C:	/* OSC_12M_SEL (OMAP1) */
   92:         return s->clksel;
   93:     case 0x50:	/* MVR */
   94:         return 0x30;
   95:     case 0x54:	/* SYSC (OMAP2) */
   96:         return s->syscontrol;
   97:     case 0x58:	/* SYSS (OMAP2) */
   98:         return 1;
   99:     case 0x5c:	/* WER (OMAP2) */
  100:         return s->wkup;
  101:     case 0x60:	/* CFPS (OMAP2) */
  102:         return s->cfps;
  103:     }
  104: 
  105:     OMAP_BAD_REG(addr);
  106:     return 0;
  107: }
  108: 
  109: static void omap_uart_write(void *opaque, target_phys_addr_t addr,
  110:                 uint32_t value)
  111: {
  112:     struct omap_uart_s *s = (struct omap_uart_s *) opaque;
  113: 
  114:     addr &= 0xff;
  115:     switch (addr) {
  116:     case 0x20:	/* MDR1 */
  117:         s->mdr[0] = value & 0x7f;
  118:         break;
  119:     case 0x24:	/* MDR2 */
  120:         s->mdr[1] = value & 0xff;
  121:         break;
  122:     case 0x40:	/* SCR */
  123:         s->scr = value & 0xff;
  124:         break;
  125:     case 0x48:	/* EBLR (OMAP2) */
  126:         s->eblr = value & 0xff;
  127:         break;
  128:     case 0x4C:	/* OSC_12M_SEL (OMAP1) */
  129:         s->clksel = value & 1;
  130:         break;
  131:     case 0x44:	/* SSR */
  132:     case 0x50:	/* MVR */
  133:     case 0x58:	/* SYSS (OMAP2) */
  134:         OMAP_RO_REG(addr);
  135:         break;
  136:     case 0x54:	/* SYSC (OMAP2) */
  137:         s->syscontrol = value & 0x1d;
  138:         if (value & 2)
  139:             omap_uart_reset(s);
  140:         break;
  141:     case 0x5c:	/* WER (OMAP2) */
  142:         s->wkup = value & 0x7f;
  143:         break;
  144:     case 0x60:	/* CFPS (OMAP2) */
  145:         s->cfps = value & 0xff;
  146:         break;
  147:     default:
  148:         OMAP_BAD_REG(addr);
  149:     }
  150: }
  151: 
  152: static CPUReadMemoryFunc * const omap_uart_readfn[] = {
  153:     omap_uart_read,
  154:     omap_uart_read,
  155:     omap_badwidth_read8,
  156: };
  157: 
  158: static CPUWriteMemoryFunc * const omap_uart_writefn[] = {
  159:     omap_uart_write,
  160:     omap_uart_write,
  161:     omap_badwidth_write8,
  162: };
  163: 
  164: struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
  165:                 qemu_irq irq, omap_clk fclk, omap_clk iclk,
  166:                 qemu_irq txdma, qemu_irq rxdma,
  167:                 const char *label, CharDriverState *chr)
  168: {
  169:     target_phys_addr_t base = omap_l4_attach(ta, 0, 0);
  170:     struct omap_uart_s *s = omap_uart_init(base, irq,
  171:                     fclk, iclk, txdma, rxdma, label, chr);
  172:     int iomemtype = cpu_register_io_memory(omap_uart_readfn,
  173:                     omap_uart_writefn, s, DEVICE_NATIVE_ENDIAN);
  174: 
  175:     s->ta = ta;
  176: 
  177:     cpu_register_physical_memory(base + 0x20, 0x100, iomemtype);
  178: 
  179:     return s;
  180: }
  181: 
  182: void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
  183: {
  184:     /* TODO: Should reuse or destroy current s->serial */
  185: #ifdef TARGET_WORDS_BIGENDIAN
  186:     s->serial = serial_mm_init(s->base, 2, s->irq,
  187:                                omap_clk_getrate(s->fclk) / 16,
  188:                                chr ?: qemu_chr_open("null", "null", NULL), 1,
  189:                                1);
  190: #else
  191:     s->serial = serial_mm_init(s->base, 2, s->irq,
  192:                                omap_clk_getrate(s->fclk) / 16,
  193:                                chr ?: qemu_chr_open("null", "null", NULL), 1,
  194:                                0);
  195: #endif
  196: }

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