Diff for /qemu/hw/openpic.c between versions 1.1.1.5 and 1.1.1.6

version 1.1.1.5, 2018/04/24 17:23:28 version 1.1.1.6, 2018/04/24 17:37:10
Line 1013  static uint32_t openpic_readl (void *opa Line 1013  static uint32_t openpic_readl (void *opa
     return retval;      return retval;
 }  }
   
 static CPUWriteMemoryFunc *openpic_write[] = {  static CPUWriteMemoryFunc * const openpic_write[] = {
     &openpic_buggy_write,      &openpic_buggy_write,
     &openpic_buggy_write,      &openpic_buggy_write,
     &openpic_writel,      &openpic_writel,
 };  };
   
 static CPUReadMemoryFunc *openpic_read[] = {  static CPUReadMemoryFunc * const openpic_read[] = {
     &openpic_buggy_read,      &openpic_buggy_read,
     &openpic_buggy_read,      &openpic_buggy_read,
     &openpic_readl,      &openpic_readl,
 };  };
   
 static void openpic_map(PCIDevice *pci_dev, int region_num,  static void openpic_map(PCIDevice *pci_dev, int region_num,
                         uint32_t addr, uint32_t size, int type)                          pcibus_t addr, pcibus_t size, int type)
 {  {
     openpic_t *opp;      openpic_t *opp;
   
Line 1202  qemu_irq *openpic_init (PCIBus *bus, int Line 1202  qemu_irq *openpic_init (PCIBus *bus, int
     if (bus) {      if (bus) {
         opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),          opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
                                                -1, NULL, NULL);                                                 -1, NULL, NULL);
         if (opp == NULL)  
             return NULL;  
         pci_conf = opp->pci_dev.config;          pci_conf = opp->pci_dev.config;
         pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);          pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
         pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2);          pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2);
Line 1213  qemu_irq *openpic_init (PCIBus *bus, int Line 1211  qemu_irq *openpic_init (PCIBus *bus, int
   
         /* Register I/O spaces */          /* Register I/O spaces */
         pci_register_bar((PCIDevice *)opp, 0, 0x40000,          pci_register_bar((PCIDevice *)opp, 0, 0x40000,
                                PCI_ADDRESS_SPACE_MEM, &openpic_map);                                 PCI_BASE_ADDRESS_SPACE_MEMORY, &openpic_map);
     } else {      } else {
         opp = qemu_mallocz(sizeof(openpic_t));          opp = qemu_mallocz(sizeof(openpic_t));
     }      }
Line 1254  qemu_irq *openpic_init (PCIBus *bus, int Line 1252  qemu_irq *openpic_init (PCIBus *bus, int
     opp->irq_raise = openpic_irq_raise;      opp->irq_raise = openpic_irq_raise;
     opp->reset = openpic_reset;      opp->reset = openpic_reset;
   
     opp->reset(opp);  
     if (pmem_index)      if (pmem_index)
         *pmem_index = opp->mem_index;          *pmem_index = opp->mem_index;
   
Line 1574  static uint32_t mpic_src_msi_read (void  Line 1571  static uint32_t mpic_src_msi_read (void 
     return retval;      return retval;
 }  }
   
 static CPUWriteMemoryFunc *mpic_glb_write[] = {  static CPUWriteMemoryFunc * const mpic_glb_write[] = {
     &openpic_buggy_write,      &openpic_buggy_write,
     &openpic_buggy_write,      &openpic_buggy_write,
     &openpic_gbl_write,      &openpic_gbl_write,
 };  };
   
 static CPUReadMemoryFunc *mpic_glb_read[] = {  static CPUReadMemoryFunc * const mpic_glb_read[] = {
     &openpic_buggy_read,      &openpic_buggy_read,
     &openpic_buggy_read,      &openpic_buggy_read,
     &openpic_gbl_read,      &openpic_gbl_read,
 };  };
   
 static CPUWriteMemoryFunc *mpic_tmr_write[] = {  static CPUWriteMemoryFunc * const mpic_tmr_write[] = {
     &openpic_buggy_write,      &openpic_buggy_write,
     &openpic_buggy_write,      &openpic_buggy_write,
     &mpic_timer_write,      &mpic_timer_write,
 };  };
   
 static CPUReadMemoryFunc *mpic_tmr_read[] = {  static CPUReadMemoryFunc * const mpic_tmr_read[] = {
     &openpic_buggy_read,      &openpic_buggy_read,
     &openpic_buggy_read,      &openpic_buggy_read,
     &mpic_timer_read,      &mpic_timer_read,
 };  };
   
 static CPUWriteMemoryFunc *mpic_cpu_write[] = {  static CPUWriteMemoryFunc * const mpic_cpu_write[] = {
     &openpic_buggy_write,      &openpic_buggy_write,
     &openpic_buggy_write,      &openpic_buggy_write,
     &openpic_cpu_write,      &openpic_cpu_write,
 };  };
   
 static CPUReadMemoryFunc *mpic_cpu_read[] = {  static CPUReadMemoryFunc * const mpic_cpu_read[] = {
     &openpic_buggy_read,      &openpic_buggy_read,
     &openpic_buggy_read,      &openpic_buggy_read,
     &openpic_cpu_read,      &openpic_cpu_read,
 };  };
   
 static CPUWriteMemoryFunc *mpic_ext_write[] = {  static CPUWriteMemoryFunc * const mpic_ext_write[] = {
     &openpic_buggy_write,      &openpic_buggy_write,
     &openpic_buggy_write,      &openpic_buggy_write,
     &mpic_src_ext_write,      &mpic_src_ext_write,
 };  };
   
 static CPUReadMemoryFunc *mpic_ext_read[] = {  static CPUReadMemoryFunc * const mpic_ext_read[] = {
     &openpic_buggy_read,      &openpic_buggy_read,
     &openpic_buggy_read,      &openpic_buggy_read,
     &mpic_src_ext_read,      &mpic_src_ext_read,
 };  };
   
 static CPUWriteMemoryFunc *mpic_int_write[] = {  static CPUWriteMemoryFunc * const mpic_int_write[] = {
     &openpic_buggy_write,      &openpic_buggy_write,
     &openpic_buggy_write,      &openpic_buggy_write,
     &mpic_src_int_write,      &mpic_src_int_write,
 };  };
   
 static CPUReadMemoryFunc *mpic_int_read[] = {  static CPUReadMemoryFunc * const mpic_int_read[] = {
     &openpic_buggy_read,      &openpic_buggy_read,
     &openpic_buggy_read,      &openpic_buggy_read,
     &mpic_src_int_read,      &mpic_src_int_read,
 };  };
   
 static CPUWriteMemoryFunc *mpic_msg_write[] = {  static CPUWriteMemoryFunc * const mpic_msg_write[] = {
     &openpic_buggy_write,      &openpic_buggy_write,
     &openpic_buggy_write,      &openpic_buggy_write,
     &mpic_src_msg_write,      &mpic_src_msg_write,
 };  };
   
 static CPUReadMemoryFunc *mpic_msg_read[] = {  static CPUReadMemoryFunc * const mpic_msg_read[] = {
     &openpic_buggy_read,      &openpic_buggy_read,
     &openpic_buggy_read,      &openpic_buggy_read,
     &mpic_src_msg_read,      &mpic_src_msg_read,
 };  };
 static CPUWriteMemoryFunc *mpic_msi_write[] = {  static CPUWriteMemoryFunc * const mpic_msi_write[] = {
     &openpic_buggy_write,      &openpic_buggy_write,
     &openpic_buggy_write,      &openpic_buggy_write,
     &mpic_src_msi_write,      &mpic_src_msi_write,
 };  };
   
 static CPUReadMemoryFunc *mpic_msi_read[] = {  static CPUReadMemoryFunc * const mpic_msi_read[] = {
     &openpic_buggy_read,      &openpic_buggy_read,
     &openpic_buggy_read,      &openpic_buggy_read,
     &mpic_src_msi_read,      &mpic_src_msi_read,
Line 1663  qemu_irq *mpic_init (target_phys_addr_t  Line 1660  qemu_irq *mpic_init (target_phys_addr_t 
     openpic_t *mpp;      openpic_t *mpp;
     int i;      int i;
     struct {      struct {
         CPUReadMemoryFunc **read;          CPUReadMemoryFunc * const *read;
         CPUWriteMemoryFunc **write;          CPUWriteMemoryFunc * const *write;
         target_phys_addr_t start_addr;          target_phys_addr_t start_addr;
         ram_addr_t size;          ram_addr_t size;
     } const list[] = {      } const list[] = {
Line 1709  qemu_irq *mpic_init (target_phys_addr_t  Line 1706  qemu_irq *mpic_init (target_phys_addr_t 
   
     register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);      register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);
     qemu_register_reset(mpic_reset, mpp);      qemu_register_reset(mpic_reset, mpp);
     mpp->reset(mpp);  
   
     return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);      return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
   

Removed from v.1.1.1.5  
changed lines
  Added in v.1.1.1.6


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