Diff for /qemu/hw/parallel.c between versions 1.1.1.3 and 1.1.1.4

version 1.1.1.3, 2018/04/24 16:48:34 version 1.1.1.4, 2018/04/24 16:52:56
Line 75  struct ParallelState { Line 75  struct ParallelState {
     int epp_timeout;      int epp_timeout;
     uint32_t last_read_offset; /* For debugging */      uint32_t last_read_offset; /* For debugging */
     /* Memory-mapped interface */      /* Memory-mapped interface */
     target_phys_addr_t base;  
     int it_shift;      int it_shift;
 };  };
   
Line 101  parallel_ioport_write_sw(void *opaque, u Line 100  parallel_ioport_write_sw(void *opaque, u
         parallel_update_irq(s);          parallel_update_irq(s);
         break;          break;
     case PARA_REG_CTR:      case PARA_REG_CTR:
           val |= 0xc0;
         if ((val & PARA_CTR_INIT) == 0 ) {          if ((val & PARA_CTR_INIT) == 0 ) {
             s->status = PARA_STS_BUSY;              s->status = PARA_STS_BUSY;
             s->status |= PARA_STS_ACK;              s->status |= PARA_STS_ACK;
Line 128  static void parallel_ioport_write_hw(voi Line 128  static void parallel_ioport_write_hw(voi
 {  {
     ParallelState *s = opaque;      ParallelState *s = opaque;
     uint8_t parm = val;      uint8_t parm = val;
       int dir;
   
     /* Sometimes programs do several writes for timing purposes on old      /* Sometimes programs do several writes for timing purposes on old
        HW. Take care not to waste time on writes that do nothing. */         HW. Take care not to waste time on writes that do nothing. */
Line 153  static void parallel_ioport_write_hw(voi Line 154  static void parallel_ioport_write_hw(voi
         if (s->control == val)          if (s->control == val)
             return;              return;
         pdebug("wc%02x\n", val);          pdebug("wc%02x\n", val);
   
           if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
               if (val & PARA_CTR_DIR) {
                   dir = 1;
               } else {
                   dir = 0;
               }
               qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
               parm &= ~PARA_CTR_DIR;
           }
   
         qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);          qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
         s->control = val;          s->control = val;
         break;          break;
Line 406  static uint32_t parallel_ioport_ecp_read Line 418  static uint32_t parallel_ioport_ecp_read
     return ret;      return ret;
 }  }
   
 static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)  static void parallel_reset(void *opaque)
 {  {
       ParallelState *s = opaque;
   
     s->datar = ~0;      s->datar = ~0;
     s->dataw = ~0;      s->dataw = ~0;
     s->status = PARA_STS_BUSY;      s->status = PARA_STS_BUSY;
     s->status |= PARA_STS_ACK;      s->status |= PARA_STS_ACK;
     s->status |= PARA_STS_ONLINE;      s->status |= PARA_STS_ONLINE;
     s->status |= PARA_STS_ERROR;      s->status |= PARA_STS_ERROR;
       s->status |= PARA_STS_TMOUT;
     s->control = PARA_CTR_SELECT;      s->control = PARA_CTR_SELECT;
     s->control |= PARA_CTR_INIT;      s->control |= PARA_CTR_INIT;
     s->irq = irq;      s->control |= 0xc0;
     s->irq_pending = 0;      s->irq_pending = 0;
     s->chr = chr;  
     s->hw_driver = 0;      s->hw_driver = 0;
     s->epp_timeout = 0;      s->epp_timeout = 0;
     s->last_read_offset = ~0U;      s->last_read_offset = ~0U;
Line 431  ParallelState *parallel_init(int base, q Line 445  ParallelState *parallel_init(int base, q
     uint8_t dummy;      uint8_t dummy;
   
     s = qemu_mallocz(sizeof(ParallelState));      s = qemu_mallocz(sizeof(ParallelState));
     if (!s)      s->irq = irq;
         return NULL;      s->chr = chr;
     parallel_reset(s, irq, chr);      parallel_reset(s);
       qemu_register_reset(parallel_reset, s);
   
     if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {      if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
         s->hw_driver = 1;          s->hw_driver = 1;
Line 462  static uint32_t parallel_mm_readb (void  Line 477  static uint32_t parallel_mm_readb (void 
 {  {
     ParallelState *s = opaque;      ParallelState *s = opaque;
   
     return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;      return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
 }  }
   
 static void parallel_mm_writeb (void *opaque,  static void parallel_mm_writeb (void *opaque,
Line 470  static void parallel_mm_writeb (void *op Line 485  static void parallel_mm_writeb (void *op
 {  {
     ParallelState *s = opaque;      ParallelState *s = opaque;
   
     parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);      parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
 }  }
   
 static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)  static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
 {  {
     ParallelState *s = opaque;      ParallelState *s = opaque;
   
     return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;      return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
 }  }
   
 static void parallel_mm_writew (void *opaque,  static void parallel_mm_writew (void *opaque,
Line 485  static void parallel_mm_writew (void *op Line 500  static void parallel_mm_writew (void *op
 {  {
     ParallelState *s = opaque;      ParallelState *s = opaque;
   
     parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);      parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
 }  }
   
 static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)  static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
 {  {
     ParallelState *s = opaque;      ParallelState *s = opaque;
   
     return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);      return parallel_ioport_read_sw(s, addr >> s->it_shift);
 }  }
   
 static void parallel_mm_writel (void *opaque,  static void parallel_mm_writel (void *opaque,
Line 500  static void parallel_mm_writel (void *op Line 515  static void parallel_mm_writel (void *op
 {  {
     ParallelState *s = opaque;      ParallelState *s = opaque;
   
     parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);      parallel_ioport_write_sw(s, addr >> s->it_shift, value);
 }  }
   
 static CPUReadMemoryFunc *parallel_mm_read_sw[] = {  static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
Line 522  ParallelState *parallel_mm_init(target_p Line 537  ParallelState *parallel_mm_init(target_p
     int io_sw;      int io_sw;
   
     s = qemu_mallocz(sizeof(ParallelState));      s = qemu_mallocz(sizeof(ParallelState));
     if (!s)      s->irq = irq;
         return NULL;      s->chr = chr;
     parallel_reset(s, irq, chr);  
     s->base = base;  
     s->it_shift = it_shift;      s->it_shift = it_shift;
       parallel_reset(s);
       qemu_register_reset(parallel_reset, s);
   
     io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);      io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
     cpu_register_physical_memory(base, 8 << it_shift, io_sw);      cpu_register_physical_memory(base, 8 << it_shift, io_sw);

Removed from v.1.1.1.3  
changed lines
  Added in v.1.1.1.4


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