Diff for /qemu/hw/parallel.c between versions 1.1.1.5 and 1.1.1.6

version 1.1.1.5, 2018/04/24 17:24:00 version 1.1.1.6, 2018/04/24 17:38:04
Line 78  struct ParallelState { Line 78  struct ParallelState {
     int it_shift;      int it_shift;
 };  };
   
   typedef struct ISAParallelState {
       ISADevice dev;
       uint32_t index;
       uint32_t iobase;
       uint32_t isairq;
       ParallelState state;
   } ISAParallelState;
   
 static void parallel_update_irq(ParallelState *s)  static void parallel_update_irq(ParallelState *s)
 {  {
     if (s->irq_pending)      if (s->irq_pending)
Line 438  static void parallel_reset(void *opaque) Line 446  static void parallel_reset(void *opaque)
     s->last_read_offset = ~0U;      s->last_read_offset = ~0U;
 }  }
   
 /* If fd is zero, it means that the parallel device uses the console */  static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)  
   static int parallel_isa_initfn(ISADevice *dev)
 {  {
     ParallelState *s;      static int index;
       ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev);
       ParallelState *s = &isa->state;
       int base;
     uint8_t dummy;      uint8_t dummy;
   
     s = qemu_mallocz(sizeof(ParallelState));      if (!s->chr) {
     s->irq = irq;          fprintf(stderr, "Can't create parallel device, empty char device\n");
     s->chr = chr;          exit(1);
     parallel_reset(s);      }
   
       if (isa->index == -1)
           isa->index = index;
       if (isa->index >= MAX_PARALLEL_PORTS)
           return -1;
       if (isa->iobase == -1)
           isa->iobase = isa_parallel_io[isa->index];
       index++;
   
       base = isa->iobase;
       isa_init_irq(dev, &s->irq, isa->isairq);
     qemu_register_reset(parallel_reset, s);      qemu_register_reset(parallel_reset, s);
   
     if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {      if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
         s->hw_driver = 1;          s->hw_driver = 1;
         s->status = dummy;          s->status = dummy;
     }      }
Line 469  ParallelState *parallel_init(int base, q Line 492  ParallelState *parallel_init(int base, q
         register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);          register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
         register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);          register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
     }      }
     return s;      return 0;
   }
   
   ParallelState *parallel_init(int index, CharDriverState *chr)
   {
       ISADevice *dev;
   
       dev = isa_create("isa-parallel");
       qdev_prop_set_uint32(&dev->qdev, "index", index);
       qdev_prop_set_chr(&dev->qdev, "chardev", chr);
       if (qdev_init(&dev->qdev) < 0)
           return NULL;
       return &DO_UPCAST(ISAParallelState, dev, dev)->state;
 }  }
   
 /* Memory mapped interface */  /* Memory mapped interface */
Line 518  static void parallel_mm_writel (void *op Line 553  static void parallel_mm_writel (void *op
     parallel_ioport_write_sw(s, addr >> s->it_shift, value);      parallel_ioport_write_sw(s, addr >> s->it_shift, value);
 }  }
   
 static CPUReadMemoryFunc *parallel_mm_read_sw[] = {  static CPUReadMemoryFunc * const parallel_mm_read_sw[] = {
     &parallel_mm_readb,      &parallel_mm_readb,
     &parallel_mm_readw,      &parallel_mm_readw,
     &parallel_mm_readl,      &parallel_mm_readl,
 };  };
   
 static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {  static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
     &parallel_mm_writeb,      &parallel_mm_writeb,
     &parallel_mm_writew,      &parallel_mm_writew,
     &parallel_mm_writel,      &parallel_mm_writel,
Line 540  ParallelState *parallel_mm_init(target_p Line 575  ParallelState *parallel_mm_init(target_p
     s->irq = irq;      s->irq = irq;
     s->chr = chr;      s->chr = chr;
     s->it_shift = it_shift;      s->it_shift = it_shift;
     parallel_reset(s);  
     qemu_register_reset(parallel_reset, s);      qemu_register_reset(parallel_reset, s);
   
     io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);      io_sw = cpu_register_io_memory(parallel_mm_read_sw, parallel_mm_write_sw, s);
     cpu_register_physical_memory(base, 8 << it_shift, io_sw);      cpu_register_physical_memory(base, 8 << it_shift, io_sw);
     return s;      return s;
 }  }
   
   static ISADeviceInfo parallel_isa_info = {
       .qdev.name  = "isa-parallel",
       .qdev.size  = sizeof(ISAParallelState),
       .init       = parallel_isa_initfn,
       .qdev.props = (Property[]) {
           DEFINE_PROP_UINT32("index", ISAParallelState, index,   -1),
           DEFINE_PROP_HEX32("iobase", ISAParallelState, iobase,  -1),
           DEFINE_PROP_UINT32("irq",   ISAParallelState, isairq,  7),
           DEFINE_PROP_CHR("chardev",  ISAParallelState, state.chr),
           DEFINE_PROP_END_OF_LIST(),
       },
   };
   
   static void parallel_register_devices(void)
   {
       isa_qdev_register(&parallel_isa_info);
   }
   
   device_init(parallel_register_devices)

Removed from v.1.1.1.5  
changed lines
  Added in v.1.1.1.6


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