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1.1 root 1: /*
2: * QEMU PC System Emulator
1.1.1.6 root 3: *
1.1 root 4: * Copyright (c) 2003-2004 Fabrice Bellard
1.1.1.6 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.6 root 24: #include "hw.h"
25: #include "pc.h"
26: #include "fdc.h"
27: #include "pci.h"
28: #include "block.h"
29: #include "sysemu.h"
30: #include "audio/audio.h"
31: #include "net.h"
32: #include "smbus.h"
33: #include "boards.h"
1.1.1.7 root 34: #include "console.h"
35: #include "fw_cfg.h"
36: #include "virtio-blk.h"
37: #include "virtio-balloon.h"
38: #include "virtio-console.h"
39: #include "hpet_emul.h"
1.1 root 40:
41: /* output Bochs bios info messages */
42: //#define DEBUG_BIOS
43:
44: #define BIOS_FILENAME "bios.bin"
45: #define VGABIOS_FILENAME "vgabios.bin"
46: #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
47:
1.1.1.7 root 48: #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
49:
1.1.1.6 root 50: /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
51: #define ACPI_DATA_SIZE 0x10000
1.1.1.7 root 52: #define BIOS_CFG_IOPORT 0x510
53: #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
1.1.1.6 root 54:
55: #define MAX_IDE_BUS 2
1.1 root 56:
1.1.1.7 root 57: extern uint8_t *acpi_tables;
58: extern size_t acpi_tables_len;
59:
1.1 root 60: static fdctrl_t *floppy_controller;
61: static RTCState *rtc_state;
62: static PITState *pit;
63: static IOAPICState *ioapic;
1.1.1.5 root 64: static PCIDevice *i440fx_state;
1.1 root 65:
1.1.1.9 root 66: typedef struct rom_reset_data {
67: uint8_t *data;
68: target_phys_addr_t addr;
69: unsigned size;
70: } RomResetData;
71:
72: static void option_rom_reset(void *_rrd)
73: {
74: RomResetData *rrd = _rrd;
75:
76: cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
77: }
78:
79: static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
80: {
81: RomResetData *rrd = qemu_malloc(sizeof *rrd);
82:
83: rrd->data = qemu_malloc(size);
84: cpu_physical_memory_read(addr, rrd->data, size);
85: rrd->addr = addr;
86: rrd->size = size;
87: qemu_register_reset(option_rom_reset, rrd);
88: }
89:
1.1 root 90: static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
91: {
92: }
93:
94: /* MSDOS compatibility mode FPU exception support */
1.1.1.6 root 95: static qemu_irq ferr_irq;
1.1 root 96: /* XXX: add IGNNE support */
97: void cpu_set_ferr(CPUX86State *s)
98: {
1.1.1.6 root 99: qemu_irq_raise(ferr_irq);
1.1 root 100: }
101:
102: static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
103: {
1.1.1.6 root 104: qemu_irq_lower(ferr_irq);
1.1 root 105: }
106:
107: /* TSC handling */
108: uint64_t cpu_get_tsc(CPUX86State *env)
109: {
1.1.1.4 root 110: /* Note: when using kqemu, it is more logical to return the host TSC
111: because kqemu does not trap the RDTSC instruction for
112: performance reasons */
1.1.1.7 root 113: #ifdef USE_KQEMU
1.1.1.4 root 114: if (env->kqemu_enabled) {
115: return cpu_get_real_ticks();
1.1.1.6 root 116: } else
1.1.1.4 root 117: #endif
118: {
119: return cpu_get_ticks();
120: }
1.1 root 121: }
122:
1.1.1.5 root 123: /* SMM support */
124: void cpu_smm_update(CPUState *env)
125: {
126: if (i440fx_state && env == first_cpu)
127: i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
128: }
129:
130:
1.1 root 131: /* IRQ handling */
132: int cpu_get_pic_interrupt(CPUState *env)
133: {
134: int intno;
135:
136: intno = apic_get_interrupt(env);
137: if (intno >= 0) {
138: /* set irq request if a PIC irq is still pending */
139: /* XXX: improve that */
1.1.1.6 root 140: pic_update_irq(isa_pic);
1.1 root 141: return intno;
142: }
143: /* read the irq from the PIC */
1.1.1.6 root 144: if (!apic_accept_pic_intr(env))
145: return -1;
146:
1.1 root 147: intno = pic_read_irq(isa_pic);
148: return intno;
149: }
150:
1.1.1.6 root 151: static void pic_irq_request(void *opaque, int irq, int level)
1.1 root 152: {
1.1.1.7 root 153: CPUState *env = first_cpu;
154:
155: if (env->apic_state) {
156: while (env) {
157: if (apic_accept_pic_intr(env))
158: apic_deliver_pic_intr(env, level);
159: env = env->next_cpu;
160: }
161: } else {
162: if (level)
163: cpu_interrupt(env, CPU_INTERRUPT_HARD);
164: else
165: cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
166: }
1.1 root 167: }
168:
169: /* PC cmos mappings */
170:
171: #define REG_EQUIPMENT_BYTE 0x14
172:
173: static int cmos_get_fd_drive_type(int fd0)
174: {
175: int val;
176:
177: switch (fd0) {
178: case 0:
179: /* 1.44 Mb 3"5 drive */
180: val = 4;
181: break;
182: case 1:
183: /* 2.88 Mb 3"5 drive */
184: val = 5;
185: break;
186: case 2:
187: /* 1.2 Mb 5"5 drive */
188: val = 2;
189: break;
190: default:
191: val = 0;
192: break;
193: }
194: return val;
195: }
196:
1.1.1.6 root 197: static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
1.1 root 198: {
199: RTCState *s = rtc_state;
200: int cylinders, heads, sectors;
201: bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors);
202: rtc_set_memory(s, type_ofs, 47);
203: rtc_set_memory(s, info_ofs, cylinders);
204: rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
205: rtc_set_memory(s, info_ofs + 2, heads);
206: rtc_set_memory(s, info_ofs + 3, 0xff);
207: rtc_set_memory(s, info_ofs + 4, 0xff);
208: rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
209: rtc_set_memory(s, info_ofs + 6, cylinders);
210: rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
211: rtc_set_memory(s, info_ofs + 8, sectors);
212: }
213:
1.1.1.6 root 214: /* convert boot_device letter to something recognizable by the bios */
215: static int boot_device2nibble(char boot_device)
216: {
217: switch(boot_device) {
218: case 'a':
219: case 'b':
220: return 0x01; /* floppy boot */
221: case 'c':
222: return 0x02; /* hard drive boot */
223: case 'd':
224: return 0x03; /* CD-ROM boot */
225: case 'n':
226: return 0x04; /* Network boot */
227: }
228: return 0;
229: }
230:
1.1.1.7 root 231: /* copy/pasted from cmos_init, should be made a general function
232: and used there as well */
233: static int pc_boot_set(void *opaque, const char *boot_device)
234: {
235: #define PC_MAX_BOOT_DEVICES 3
236: RTCState *s = (RTCState *)opaque;
237: int nbds, bds[3] = { 0, };
238: int i;
239:
240: nbds = strlen(boot_device);
241: if (nbds > PC_MAX_BOOT_DEVICES) {
242: term_printf("Too many boot devices for PC\n");
243: return(1);
244: }
245: for (i = 0; i < nbds; i++) {
246: bds[i] = boot_device2nibble(boot_device[i]);
247: if (bds[i] == 0) {
248: term_printf("Invalid boot device for PC: '%c'\n",
249: boot_device[i]);
250: return(1);
251: }
252: }
253: rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
254: rtc_set_memory(s, 0x38, (bds[2] << 4));
255: return(0);
256: }
257:
1.1 root 258: /* hd_table must contain 4 block drivers */
1.1.1.7 root 259: static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
260: const char *boot_device, BlockDriverState **hd_table)
1.1 root 261: {
262: RTCState *s = rtc_state;
1.1.1.6 root 263: int nbds, bds[3] = { 0, };
1.1 root 264: int val;
265: int fd0, fd1, nb;
266: int i;
267:
268: /* various important CMOS locations needed by PC/Bochs bios */
269:
270: /* memory size */
271: val = 640; /* base memory in K */
272: rtc_set_memory(s, 0x15, val);
273: rtc_set_memory(s, 0x16, val >> 8);
274:
275: val = (ram_size / 1024) - 1024;
276: if (val > 65535)
277: val = 65535;
278: rtc_set_memory(s, 0x17, val);
279: rtc_set_memory(s, 0x18, val >> 8);
280: rtc_set_memory(s, 0x30, val);
281: rtc_set_memory(s, 0x31, val >> 8);
282:
1.1.1.7 root 283: if (above_4g_mem_size) {
284: rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
285: rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
286: rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
287: }
288:
1.1 root 289: if (ram_size > (16 * 1024 * 1024))
290: val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
291: else
292: val = 0;
293: if (val > 65535)
294: val = 65535;
295: rtc_set_memory(s, 0x34, val);
296: rtc_set_memory(s, 0x35, val >> 8);
1.1.1.6 root 297:
1.1.1.7 root 298: /* set the number of CPU */
299: rtc_set_memory(s, 0x5f, smp_cpus - 1);
300:
1.1.1.6 root 301: /* set boot devices, and disable floppy signature check if requested */
302: #define PC_MAX_BOOT_DEVICES 3
303: nbds = strlen(boot_device);
304: if (nbds > PC_MAX_BOOT_DEVICES) {
305: fprintf(stderr, "Too many boot devices for PC\n");
306: exit(1);
1.1 root 307: }
1.1.1.6 root 308: for (i = 0; i < nbds; i++) {
309: bds[i] = boot_device2nibble(boot_device[i]);
310: if (bds[i] == 0) {
311: fprintf(stderr, "Invalid boot device for PC: '%c'\n",
312: boot_device[i]);
313: exit(1);
314: }
315: }
316: rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
317: rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
1.1 root 318:
319: /* floppy type */
320:
321: fd0 = fdctrl_get_drive_type(floppy_controller, 0);
322: fd1 = fdctrl_get_drive_type(floppy_controller, 1);
323:
324: val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
325: rtc_set_memory(s, 0x10, val);
1.1.1.6 root 326:
1.1 root 327: val = 0;
328: nb = 0;
329: if (fd0 < 3)
330: nb++;
331: if (fd1 < 3)
332: nb++;
333: switch (nb) {
334: case 0:
335: break;
336: case 1:
337: val |= 0x01; /* 1 drive, ready for boot */
338: break;
339: case 2:
340: val |= 0x41; /* 2 drives, ready for boot */
341: break;
342: }
343: val |= 0x02; /* FPU is there */
344: val |= 0x04; /* PS/2 mouse installed */
345: rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
346:
347: /* hard drives */
348:
349: rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
350: if (hd_table[0])
351: cmos_init_hd(0x19, 0x1b, hd_table[0]);
1.1.1.6 root 352: if (hd_table[1])
1.1 root 353: cmos_init_hd(0x1a, 0x24, hd_table[1]);
354:
355: val = 0;
356: for (i = 0; i < 4; i++) {
357: if (hd_table[i]) {
358: int cylinders, heads, sectors, translation;
359: /* NOTE: bdrv_get_geometry_hint() returns the physical
360: geometry. It is always such that: 1 <= sects <= 63, 1
361: <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
362: geometry can be different if a translation is done. */
363: translation = bdrv_get_translation_hint(hd_table[i]);
364: if (translation == BIOS_ATA_TRANSLATION_AUTO) {
365: bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors);
366: if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
367: /* No translation. */
368: translation = 0;
369: } else {
370: /* LBA translation. */
371: translation = 1;
372: }
373: } else {
374: translation--;
375: }
376: val |= translation << (i * 2);
377: }
378: }
379: rtc_set_memory(s, 0x39, val);
380: }
381:
1.1.1.2 root 382: void ioport_set_a20(int enable)
383: {
384: /* XXX: send to all CPUs ? */
385: cpu_x86_set_a20(first_cpu, enable);
386: }
387:
388: int ioport_get_a20(void)
389: {
390: return ((first_cpu->a20_mask >> 20) & 1);
391: }
392:
1.1 root 393: static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
394: {
1.1.1.2 root 395: ioport_set_a20((val >> 1) & 1);
1.1 root 396: /* XXX: bit 0 is fast reset */
397: }
398:
399: static uint32_t ioport92_read(void *opaque, uint32_t addr)
400: {
1.1.1.2 root 401: return ioport_get_a20() << 1;
1.1 root 402: }
403:
404: /***********************************************************/
405: /* Bochs BIOS debug ports */
406:
1.1.1.6 root 407: static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
1.1 root 408: {
409: static const char shutdown_str[8] = "Shutdown";
410: static int shutdown_index = 0;
1.1.1.6 root 411:
1.1 root 412: switch(addr) {
413: /* Bochs BIOS messages */
414: case 0x400:
415: case 0x401:
416: fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
417: exit(1);
418: case 0x402:
419: case 0x403:
420: #ifdef DEBUG_BIOS
421: fprintf(stderr, "%c", val);
422: #endif
423: break;
424: case 0x8900:
425: /* same as Bochs power off */
426: if (val == shutdown_str[shutdown_index]) {
427: shutdown_index++;
428: if (shutdown_index == 8) {
429: shutdown_index = 0;
430: qemu_system_shutdown_request();
431: }
432: } else {
433: shutdown_index = 0;
434: }
435: break;
436:
437: /* LGPL'ed VGA BIOS messages */
438: case 0x501:
439: case 0x502:
440: fprintf(stderr, "VGA BIOS panic, line %d\n", val);
441: exit(1);
442: case 0x500:
443: case 0x503:
444: #ifdef DEBUG_BIOS
445: fprintf(stderr, "%c", val);
446: #endif
447: break;
448: }
449: }
450:
1.1.1.6 root 451: static void bochs_bios_init(void)
1.1 root 452: {
1.1.1.7 root 453: void *fw_cfg;
454:
1.1 root 455: register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
456: register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
457: register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
458: register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
459: register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
460:
461: register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
462: register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
463: register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
464: register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
1.1.1.7 root 465:
466: fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
467: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
468: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
469: fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, acpi_tables, acpi_tables_len);
1.1 root 470: }
471:
1.1.1.6 root 472: /* Generate an initial boot sector which sets state and jump to
473: a specified vector */
1.1.1.9 root 474: static void generate_bootsect(target_phys_addr_t option_rom,
1.1.1.7 root 475: uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
1.1.1.6 root 476: {
1.1.1.7 root 477: uint8_t rom[512], *p, *reloc;
478: uint8_t sum;
1.1.1.6 root 479: int i;
480:
1.1.1.7 root 481: memset(rom, 0, sizeof(rom));
1.1.1.6 root 482:
1.1.1.7 root 483: p = rom;
484: /* Make sure we have an option rom signature */
485: *p++ = 0x55;
486: *p++ = 0xaa;
487:
488: /* ROM size in sectors*/
489: *p++ = 1;
490:
491: /* Hook int19 */
492:
493: *p++ = 0x50; /* push ax */
494: *p++ = 0x1e; /* push ds */
495: *p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */
496: *p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */
497:
498: *p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */
499: *p++ = 0x64; *p++ = 0x00;
500: reloc = p;
501: *p++ = 0x00; *p++ = 0x00;
502:
503: *p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */
504: *p++ = 0x66; *p++ = 0x00;
505:
506: *p++ = 0x1f; /* pop ds */
507: *p++ = 0x58; /* pop ax */
508: *p++ = 0xcb; /* lret */
509:
1.1.1.6 root 510: /* Actual code */
1.1.1.7 root 511: *reloc = (p - rom);
512:
1.1.1.6 root 513: *p++ = 0xfa; /* CLI */
514: *p++ = 0xfc; /* CLD */
515:
516: for (i = 0; i < 6; i++) {
517: if (i == 1) /* Skip CS */
518: continue;
519:
520: *p++ = 0xb8; /* MOV AX,imm16 */
521: *p++ = segs[i];
522: *p++ = segs[i] >> 8;
523: *p++ = 0x8e; /* MOV <seg>,AX */
524: *p++ = 0xc0 + (i << 3);
525: }
526:
527: for (i = 0; i < 8; i++) {
528: *p++ = 0x66; /* 32-bit operand size */
529: *p++ = 0xb8 + i; /* MOV <reg>,imm32 */
530: *p++ = gpr[i];
531: *p++ = gpr[i] >> 8;
532: *p++ = gpr[i] >> 16;
533: *p++ = gpr[i] >> 24;
534: }
535:
536: *p++ = 0xea; /* JMP FAR */
537: *p++ = ip; /* IP */
538: *p++ = ip >> 8;
539: *p++ = segs[1]; /* CS */
540: *p++ = segs[1] >> 8;
541:
1.1.1.7 root 542: /* sign rom */
543: sum = 0;
544: for (i = 0; i < (sizeof(rom) - 1); i++)
545: sum += rom[i];
546: rom[sizeof(rom) - 1] = -sum;
1.1 root 547:
1.1.1.9 root 548: cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
549: option_rom_setup_reset(option_rom, sizeof (rom));
1.1 root 550: }
551:
1.1.1.6 root 552: static long get_file_size(FILE *f)
553: {
554: long where, size;
555:
556: /* XXX: on Unix systems, using fstat() probably makes more sense */
557:
558: where = ftell(f);
559: fseek(f, 0, SEEK_END);
560: size = ftell(f);
561: fseek(f, where, SEEK_SET);
562:
563: return size;
564: }
565:
1.1.1.9 root 566: static void load_linux(target_phys_addr_t option_rom,
1.1.1.7 root 567: const char *kernel_filename,
1.1.1.6 root 568: const char *initrd_filename,
1.1.1.10! root 569: const char *kernel_cmdline,
! 570: target_phys_addr_t max_ram_size)
1.1.1.6 root 571: {
572: uint16_t protocol;
573: uint32_t gpr[8];
574: uint16_t seg[6];
575: uint16_t real_seg;
576: int setup_size, kernel_size, initrd_size, cmdline_size;
577: uint32_t initrd_max;
578: uint8_t header[1024];
1.1.1.7 root 579: target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr;
1.1.1.6 root 580: FILE *f, *fi;
581:
582: /* Align to 16 bytes as a paranoia measure */
583: cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
584:
585: /* load the kernel header */
586: f = fopen(kernel_filename, "rb");
587: if (!f || !(kernel_size = get_file_size(f)) ||
588: fread(header, 1, 1024, f) != 1024) {
589: fprintf(stderr, "qemu: could not load kernel '%s'\n",
590: kernel_filename);
591: exit(1);
592: }
593:
594: /* kernel protocol version */
595: #if 0
596: fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
597: #endif
598: if (ldl_p(header+0x202) == 0x53726448)
599: protocol = lduw_p(header+0x206);
600: else
601: protocol = 0;
602:
603: if (protocol < 0x200 || !(header[0x211] & 0x01)) {
604: /* Low kernel */
1.1.1.7 root 605: real_addr = 0x90000;
606: cmdline_addr = 0x9a000 - cmdline_size;
607: prot_addr = 0x10000;
1.1.1.6 root 608: } else if (protocol < 0x202) {
609: /* High but ancient kernel */
1.1.1.7 root 610: real_addr = 0x90000;
611: cmdline_addr = 0x9a000 - cmdline_size;
612: prot_addr = 0x100000;
1.1.1.6 root 613: } else {
614: /* High and recent kernel */
1.1.1.7 root 615: real_addr = 0x10000;
616: cmdline_addr = 0x20000;
617: prot_addr = 0x100000;
1.1.1.6 root 618: }
619:
620: #if 0
621: fprintf(stderr,
1.1.1.7 root 622: "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
623: "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
624: "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
625: real_addr,
626: cmdline_addr,
627: prot_addr);
1.1.1.6 root 628: #endif
629:
630: /* highest address for loading the initrd */
631: if (protocol >= 0x203)
632: initrd_max = ldl_p(header+0x22c);
633: else
634: initrd_max = 0x37ffffff;
635:
1.1.1.10! root 636: if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
! 637: initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
1.1.1.6 root 638:
639: /* kernel command line */
1.1.1.7 root 640: pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
1.1.1.6 root 641:
642: if (protocol >= 0x202) {
1.1.1.7 root 643: stl_p(header+0x228, cmdline_addr);
1.1.1.6 root 644: } else {
645: stw_p(header+0x20, 0xA33F);
646: stw_p(header+0x22, cmdline_addr-real_addr);
647: }
648:
649: /* loader type */
650: /* High nybble = B reserved for Qemu; low nybble is revision number.
651: If this code is substantially changed, you may want to consider
652: incrementing the revision. */
653: if (protocol >= 0x200)
654: header[0x210] = 0xB0;
655:
656: /* heap */
657: if (protocol >= 0x201) {
658: header[0x211] |= 0x80; /* CAN_USE_HEAP */
659: stw_p(header+0x224, cmdline_addr-real_addr-0x200);
660: }
661:
662: /* load initrd */
663: if (initrd_filename) {
664: if (protocol < 0x200) {
665: fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
666: exit(1);
667: }
668:
669: fi = fopen(initrd_filename, "rb");
670: if (!fi) {
671: fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
672: initrd_filename);
673: exit(1);
674: }
675:
676: initrd_size = get_file_size(fi);
1.1.1.7 root 677: initrd_addr = (initrd_max-initrd_size) & ~4095;
1.1.1.6 root 678:
1.1.1.7 root 679: if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
1.1.1.6 root 680: fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
681: initrd_filename);
682: exit(1);
683: }
684: fclose(fi);
685:
1.1.1.7 root 686: stl_p(header+0x218, initrd_addr);
1.1.1.6 root 687: stl_p(header+0x21c, initrd_size);
688: }
689:
690: /* store the finalized header and load the rest of the kernel */
1.1.1.7 root 691: cpu_physical_memory_write(real_addr, header, 1024);
1.1.1.6 root 692:
693: setup_size = header[0x1f1];
694: if (setup_size == 0)
695: setup_size = 4;
696:
697: setup_size = (setup_size+1)*512;
698: kernel_size -= setup_size; /* Size of protected-mode code */
699:
1.1.1.7 root 700: if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) ||
701: !fread_targphys_ok(prot_addr, kernel_size, f)) {
1.1.1.6 root 702: fprintf(stderr, "qemu: read error on kernel '%s'\n",
703: kernel_filename);
704: exit(1);
705: }
706: fclose(f);
707:
708: /* generate bootsector to set up the initial register state */
1.1.1.7 root 709: real_seg = real_addr >> 4;
1.1.1.6 root 710: seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
711: seg[1] = real_seg+0x20; /* CS */
712: memset(gpr, 0, sizeof gpr);
713: gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */
714:
1.1.1.9 root 715: option_rom_setup_reset(real_addr, setup_size);
716: option_rom_setup_reset(prot_addr, kernel_size);
717: option_rom_setup_reset(cmdline_addr, cmdline_size);
718: if (initrd_filename)
719: option_rom_setup_reset(initrd_addr, initrd_size);
720:
1.1.1.7 root 721: generate_bootsect(option_rom, gpr, seg, 0);
1.1.1.6 root 722: }
723:
1.1.1.2 root 724: static void main_cpu_reset(void *opaque)
725: {
726: CPUState *env = opaque;
727: cpu_reset(env);
728: }
729:
1.1 root 730: static const int ide_iobase[2] = { 0x1f0, 0x170 };
731: static const int ide_iobase2[2] = { 0x3f6, 0x376 };
732: static const int ide_irq[2] = { 14, 15 };
733:
734: #define NE2000_NB_MAX 6
735:
736: static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
737: static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
738:
739: static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
740: static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
741:
742: static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
743: static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
744:
1.1.1.2 root 745: #ifdef HAS_AUDIO
1.1.1.6 root 746: static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
1.1.1.2 root 747: {
748: struct soundhw *c;
749: int audio_enabled = 0;
750:
751: for (c = soundhw; !audio_enabled && c->name; ++c) {
752: audio_enabled = c->enabled;
753: }
754:
755: if (audio_enabled) {
756: AudioState *s;
757:
758: s = AUD_init ();
759: if (s) {
760: for (c = soundhw; c->name; ++c) {
761: if (c->enabled) {
762: if (c->isa) {
1.1.1.6 root 763: c->init.init_isa (s, pic);
1.1.1.2 root 764: }
765: else {
766: if (pci_bus) {
767: c->init.init_pci (pci_bus, s);
768: }
769: }
770: }
771: }
772: }
773: }
774: }
775: #endif
776:
1.1.1.6 root 777: static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
1.1.1.3 root 778: {
779: static int nb_ne2k = 0;
780:
781: if (nb_ne2k == NE2000_NB_MAX)
782: return;
1.1.1.6 root 783: isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
1.1.1.3 root 784: nb_ne2k++;
785: }
786:
1.1 root 787: /* PC hardware initialisation */
1.1.1.7 root 788: static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
789: const char *boot_device,
1.1 root 790: const char *kernel_filename, const char *kernel_cmdline,
1.1.1.2 root 791: const char *initrd_filename,
1.1.1.6 root 792: int pci_enabled, const char *cpu_model)
1.1 root 793: {
794: char buf[1024];
1.1.1.6 root 795: int ret, linux_boot, i;
796: ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset;
1.1.1.7 root 797: ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
1.1.1.6 root 798: int bios_size, isa_bios_size, vga_bios_size;
1.1 root 799: PCIBus *pci_bus;
1.1.1.4 root 800: int piix3_devfn = -1;
1.1.1.2 root 801: CPUState *env;
1.1.1.6 root 802: qemu_irq *cpu_irq;
803: qemu_irq *i8259;
804: int index;
805: BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
806: BlockDriverState *fd[MAX_FD];
1.1 root 807:
1.1.1.7 root 808: if (ram_size >= 0xe0000000 ) {
809: above_4g_mem_size = ram_size - 0xe0000000;
810: below_4g_mem_size = 0xe0000000;
811: } else {
812: below_4g_mem_size = ram_size;
813: }
814:
1.1 root 815: linux_boot = (kernel_filename != NULL);
816:
1.1.1.2 root 817: /* init CPUs */
1.1.1.6 root 818: if (cpu_model == NULL) {
819: #ifdef TARGET_X86_64
820: cpu_model = "qemu64";
821: #else
822: cpu_model = "qemu32";
823: #endif
824: }
825:
1.1.1.2 root 826: for(i = 0; i < smp_cpus; i++) {
1.1.1.6 root 827: env = cpu_init(cpu_model);
828: if (!env) {
829: fprintf(stderr, "Unable to find x86 CPU definition\n");
830: exit(1);
831: }
1.1.1.2 root 832: if (i != 0)
1.1.1.7 root 833: env->halted = 1;
1.1.1.2 root 834: if (smp_cpus > 1) {
835: /* XXX: enable it in all cases */
836: env->cpuid_features |= CPUID_APIC;
837: }
838: qemu_register_reset(main_cpu_reset, env);
839: if (pci_enabled) {
840: apic_init(env);
841: }
842: }
843:
1.1.1.7 root 844: vmport_init();
845:
1.1 root 846: /* allocate RAM */
1.1.1.7 root 847: ram_addr = qemu_ram_alloc(0xa0000);
848: cpu_register_physical_memory(0, 0xa0000, ram_addr);
849:
850: /* Allocate, even though we won't register, so we don't break the
851: * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
852: * and some bios areas, which will be registered later
853: */
854: ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
855: ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
856: cpu_register_physical_memory(0x100000,
857: below_4g_mem_size - 0x100000,
858: ram_addr);
859:
860: /* above 4giga memory allocation */
861: if (above_4g_mem_size > 0) {
862: ram_addr = qemu_ram_alloc(above_4g_mem_size);
863: cpu_register_physical_memory(0x100000000ULL,
864: above_4g_mem_size,
865: ram_addr);
866: }
867:
1.1 root 868:
1.1.1.6 root 869: /* allocate VGA RAM */
870: vga_ram_addr = qemu_ram_alloc(vga_ram_size);
1.1 root 871:
1.1.1.6 root 872: /* BIOS load */
873: if (bios_name == NULL)
874: bios_name = BIOS_FILENAME;
875: snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1.1 root 876: bios_size = get_image_size(buf);
1.1.1.6 root 877: if (bios_size <= 0 ||
878: (bios_size % 65536) != 0) {
1.1 root 879: goto bios_error;
880: }
1.1.1.6 root 881: bios_offset = qemu_ram_alloc(bios_size);
1.1 root 882: ret = load_image(buf, phys_ram_base + bios_offset);
883: if (ret != bios_size) {
884: bios_error:
1.1.1.6 root 885: fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
1.1 root 886: exit(1);
887: }
888:
1.1.1.7 root 889: if (cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled) {
890: /* VGA BIOS load */
891: if (cirrus_vga_enabled) {
892: snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME);
893: } else {
894: snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
895: }
896: vga_bios_size = get_image_size(buf);
897: if (vga_bios_size <= 0 || vga_bios_size > 65536)
898: goto vga_bios_error;
899: vga_bios_offset = qemu_ram_alloc(65536);
900:
901: ret = load_image(buf, phys_ram_base + vga_bios_offset);
902: if (ret != vga_bios_size) {
903: vga_bios_error:
904: fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf);
905: exit(1);
906: }
1.1.1.6 root 907:
1.1.1.7 root 908: /* setup basic memory access */
909: cpu_register_physical_memory(0xc0000, 0x10000,
910: vga_bios_offset | IO_MEM_ROM);
911: }
1.1 root 912:
913: /* map the last 128KB of the BIOS in ISA space */
914: isa_bios_size = bios_size;
915: if (isa_bios_size > (128 * 1024))
916: isa_bios_size = 128 * 1024;
1.1.1.6 root 917: cpu_register_physical_memory(0x100000 - isa_bios_size,
918: isa_bios_size,
1.1 root 919: (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
1.1.1.5 root 920:
1.1.1.6 root 921: {
922: ram_addr_t option_rom_offset;
923: int size, offset;
924:
925: offset = 0;
1.1.1.7 root 926: if (linux_boot) {
927: option_rom_offset = qemu_ram_alloc(TARGET_PAGE_SIZE);
928: cpu_register_physical_memory(0xd0000, TARGET_PAGE_SIZE,
1.1.1.8 root 929: option_rom_offset);
1.1.1.10! root 930: load_linux(0xd0000,
! 931: kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1.1.1.7 root 932: offset = TARGET_PAGE_SIZE;
933: }
934:
1.1.1.6 root 935: for (i = 0; i < nb_option_roms; i++) {
936: size = get_image_size(option_rom[i]);
937: if (size < 0) {
938: fprintf(stderr, "Could not load option rom '%s'\n",
939: option_rom[i]);
940: exit(1);
941: }
942: if (size > (0x10000 - offset))
943: goto option_rom_error;
944: option_rom_offset = qemu_ram_alloc(size);
945: ret = load_image(option_rom[i], phys_ram_base + option_rom_offset);
946: if (ret != size) {
947: option_rom_error:
948: fprintf(stderr, "Too many option ROMS\n");
949: exit(1);
950: }
951: size = (size + 4095) & ~4095;
952: cpu_register_physical_memory(0xd0000 + offset,
953: size, option_rom_offset | IO_MEM_ROM);
954: offset += size;
955: }
1.1.1.5 root 956: }
957:
1.1 root 958: /* map all the bios at the top of memory */
1.1.1.6 root 959: cpu_register_physical_memory((uint32_t)(-bios_size),
1.1 root 960: bios_size, bios_offset | IO_MEM_ROM);
1.1.1.6 root 961:
1.1 root 962: bochs_bios_init();
963:
1.1.1.7 root 964: cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
1.1.1.6 root 965: i8259 = i8259_init(cpu_irq[0]);
966: ferr_irq = i8259[13];
1.1 root 967:
968: if (pci_enabled) {
1.1.1.6 root 969: pci_bus = i440fx_init(&i440fx_state, i8259);
1.1.1.5 root 970: piix3_devfn = piix3_init(pci_bus, -1);
1.1 root 971: } else {
972: pci_bus = NULL;
973: }
974:
975: /* init basic PC hardware */
976: register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
977:
978: register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
979:
980: if (cirrus_vga_enabled) {
981: if (pci_enabled) {
1.1.1.6 root 982: pci_cirrus_vga_init(pci_bus,
1.1.1.7 root 983: phys_ram_base + vga_ram_addr,
1.1.1.6 root 984: vga_ram_addr, vga_ram_size);
1.1 root 985: } else {
1.1.1.7 root 986: isa_cirrus_vga_init(phys_ram_base + vga_ram_addr,
1.1.1.6 root 987: vga_ram_addr, vga_ram_size);
1.1 root 988: }
1.1.1.6 root 989: } else if (vmsvga_enabled) {
990: if (pci_enabled)
1.1.1.7 root 991: pci_vmsvga_init(pci_bus, phys_ram_base + vga_ram_addr,
992: vga_ram_addr, vga_ram_size);
1.1.1.6 root 993: else
994: fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1.1.1.7 root 995: } else if (std_vga_enabled) {
1.1.1.5 root 996: if (pci_enabled) {
1.1.1.7 root 997: pci_vga_init(pci_bus, phys_ram_base + vga_ram_addr,
1.1.1.6 root 998: vga_ram_addr, vga_ram_size, 0, 0);
1.1.1.5 root 999: } else {
1.1.1.7 root 1000: isa_vga_init(phys_ram_base + vga_ram_addr,
1.1.1.6 root 1001: vga_ram_addr, vga_ram_size);
1.1.1.5 root 1002: }
1.1 root 1003: }
1004:
1.1.1.7 root 1005: rtc_state = rtc_init(0x70, i8259[8], 2000);
1006:
1007: qemu_register_boot_set(pc_boot_set, rtc_state);
1.1 root 1008:
1009: register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1010: register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1011:
1012: if (pci_enabled) {
1013: ioapic = ioapic_init();
1014: }
1.1.1.6 root 1015: pit = pit_init(0x40, i8259[0]);
1.1.1.3 root 1016: pcspk_init(pit);
1.1.1.7 root 1017: if (!no_hpet) {
1018: hpet_init(i8259);
1019: }
1.1 root 1020: if (pci_enabled) {
1021: pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
1022: }
1023:
1024: for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1025: if (serial_hds[i]) {
1.1.1.7 root 1026: serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
1027: serial_hds[i]);
1.1 root 1028: }
1029: }
1030:
1031: for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1032: if (parallel_hds[i]) {
1.1.1.6 root 1033: parallel_init(parallel_io[i], i8259[parallel_irq[i]],
1034: parallel_hds[i]);
1.1 root 1035: }
1036: }
1037:
1.1.1.3 root 1038: for(i = 0; i < nb_nics; i++) {
1.1.1.7 root 1039: NICInfo *nd = &nd_table[i];
1040:
1041: if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1.1.1.6 root 1042: pc_init_ne2k_isa(nd, i8259);
1.1.1.7 root 1043: else
1044: pci_nic_init(pci_bus, nd, -1, "ne2k_pci");
1.1.1.3 root 1045: }
1.1 root 1046:
1.1.1.7 root 1047: qemu_system_hot_add_init();
1048:
1.1.1.6 root 1049: if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1050: fprintf(stderr, "qemu: too many IDE bus\n");
1051: exit(1);
1052: }
1053:
1054: for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1055: index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1056: if (index != -1)
1057: hd[i] = drives_table[index].bdrv;
1058: else
1059: hd[i] = NULL;
1060: }
1061:
1.1.1.3 root 1062: if (pci_enabled) {
1.1.1.6 root 1063: pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
1.1.1.3 root 1064: } else {
1.1.1.6 root 1065: for(i = 0; i < MAX_IDE_BUS; i++) {
1066: isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
1067: hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1.1 root 1068: }
1069: }
1070:
1.1.1.6 root 1071: i8042_init(i8259[1], i8259[12], 0x60);
1.1 root 1072: DMA_init(0);
1.1.1.2 root 1073: #ifdef HAS_AUDIO
1.1.1.6 root 1074: audio_init(pci_enabled ? pci_bus : NULL, i8259);
1.1 root 1075: #endif
1076:
1.1.1.6 root 1077: for(i = 0; i < MAX_FD; i++) {
1078: index = drive_get_index(IF_FLOPPY, 0, i);
1079: if (index != -1)
1080: fd[i] = drives_table[index].bdrv;
1081: else
1082: fd[i] = NULL;
1083: }
1084: floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1.1 root 1085:
1.1.1.7 root 1086: cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1.1 root 1087:
1.1.1.2 root 1088: if (pci_enabled && usb_enabled) {
1.1.1.6 root 1089: usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1.1.1.4 root 1090: }
1091:
1092: if (pci_enabled && acpi_enabled) {
1.1.1.5 root 1093: uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1.1.1.6 root 1094: i2c_bus *smbus;
1095:
1096: /* TODO: Populate SPD eeprom data. */
1.1.1.7 root 1097: smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1.1.1.5 root 1098: for (i = 0; i < 8; i++) {
1.1.1.6 root 1099: smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
1.1.1.5 root 1100: }
1101: }
1.1.1.6 root 1102:
1.1.1.5 root 1103: if (i440fx_state) {
1104: i440fx_init_memory_mappings(i440fx_state);
1.1.1.2 root 1105: }
1.1.1.6 root 1106:
1.1.1.4 root 1107: if (pci_enabled) {
1.1.1.6 root 1108: int max_bus;
1109: int bus, unit;
1.1.1.4 root 1110: void *scsi;
1111:
1.1.1.6 root 1112: max_bus = drive_get_max_bus(IF_SCSI);
1113:
1114: for (bus = 0; bus <= max_bus; bus++) {
1115: scsi = lsi_scsi_init(pci_bus, -1);
1116: for (unit = 0; unit < LSI_MAX_DEVS; unit++) {
1117: index = drive_get_index(IF_SCSI, bus, unit);
1118: if (index == -1)
1119: continue;
1120: lsi_scsi_attach(scsi, drives_table[index].bdrv, unit);
1121: }
1122: }
1.1.1.4 root 1123: }
1.1.1.7 root 1124:
1125: /* Add virtio block devices */
1126: if (pci_enabled) {
1127: int index;
1128: int unit_id = 0;
1129:
1130: while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
1131: virtio_blk_init(pci_bus, drives_table[index].bdrv);
1132: unit_id++;
1133: }
1134: }
1135:
1136: /* Add virtio balloon device */
1137: if (pci_enabled)
1138: virtio_balloon_init(pci_bus);
1139:
1140: /* Add virtio console devices */
1141: if (pci_enabled) {
1142: for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1143: if (virtcon_hds[i])
1144: virtio_console_init(pci_bus, virtcon_hds[i]);
1145: }
1146: }
1.1 root 1147: }
1148:
1.1.1.7 root 1149: static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
1150: const char *boot_device,
1.1.1.6 root 1151: const char *kernel_filename,
1.1.1.2 root 1152: const char *kernel_cmdline,
1.1.1.6 root 1153: const char *initrd_filename,
1154: const char *cpu_model)
1.1.1.2 root 1155: {
1.1.1.7 root 1156: pc_init1(ram_size, vga_ram_size, boot_device,
1.1.1.2 root 1157: kernel_filename, kernel_cmdline,
1.1.1.6 root 1158: initrd_filename, 1, cpu_model);
1.1.1.2 root 1159: }
1160:
1.1.1.7 root 1161: static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
1162: const char *boot_device,
1.1.1.6 root 1163: const char *kernel_filename,
1.1.1.2 root 1164: const char *kernel_cmdline,
1.1.1.6 root 1165: const char *initrd_filename,
1166: const char *cpu_model)
1.1.1.2 root 1167: {
1.1.1.7 root 1168: pc_init1(ram_size, vga_ram_size, boot_device,
1.1.1.2 root 1169: kernel_filename, kernel_cmdline,
1.1.1.6 root 1170: initrd_filename, 0, cpu_model);
1.1.1.2 root 1171: }
1172:
1.1.1.7 root 1173: /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1174: BIOS will read it and start S3 resume at POST Entry */
1175: void cmos_set_s3_resume(void)
1176: {
1177: if (rtc_state)
1178: rtc_set_memory(rtc_state, 0xF, 0xFE);
1179: }
1180:
1.1 root 1181: QEMUMachine pc_machine = {
1.1.1.7 root 1182: .name = "pc",
1183: .desc = "Standard PC",
1184: .init = pc_init_pci,
1185: .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1186: .max_cpus = 255,
1.1.1.2 root 1187: };
1188:
1189: QEMUMachine isapc_machine = {
1.1.1.7 root 1190: .name = "isapc",
1191: .desc = "ISA-only PC",
1192: .init = pc_init_isa,
1193: .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1194: .max_cpus = 1,
1.1 root 1195: };
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