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1.1 root 1: /*
2: * QEMU PC System Emulator
1.1.1.6 root 3: *
1.1 root 4: * Copyright (c) 2003-2004 Fabrice Bellard
1.1.1.6 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.6 root 24: #include "hw.h"
25: #include "pc.h"
1.1.1.15 root 26: #include "apic.h"
1.1.1.6 root 27: #include "fdc.h"
1.1.1.15 root 28: #include "ide.h"
1.1.1.6 root 29: #include "pci.h"
1.1.1.12 root 30: #include "vmware_vga.h"
1.1.1.11 root 31: #include "monitor.h"
1.1.1.7 root 32: #include "fw_cfg.h"
33: #include "hpet_emul.h"
1.1.1.11 root 34: #include "smbios.h"
1.1.1.12 root 35: #include "loader.h"
36: #include "elf.h"
1.1.1.15 root 37: #include "multiboot.h"
38: #include "mc146818rtc.h"
39: #include "msix.h"
40: #include "sysbus.h"
41: #include "sysemu.h"
1.1.1.16 root 42: #include "blockdev.h"
43: #include "ui/qemu-spice.h"
1.1 root 44:
45: /* output Bochs bios info messages */
46: //#define DEBUG_BIOS
47:
1.1.1.15 root 48: /* debug PC/ISA interrupts */
49: //#define DEBUG_IRQ
50:
51: #ifdef DEBUG_IRQ
52: #define DPRINTF(fmt, ...) \
53: do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
54: #else
55: #define DPRINTF(fmt, ...)
56: #endif
1.1.1.11 root 57:
1.1 root 58: #define BIOS_FILENAME "bios.bin"
59:
1.1.1.7 root 60: #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
61:
1.1.1.6 root 62: /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
63: #define ACPI_DATA_SIZE 0x10000
1.1.1.7 root 64: #define BIOS_CFG_IOPORT 0x510
65: #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
1.1.1.11 root 66: #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
1.1.1.12 root 67: #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
1.1.1.15 root 68: #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
69: #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
70:
71: #define MSI_ADDR_BASE 0xfee00000
1.1.1.6 root 72:
1.1.1.15 root 73: #define E820_NR_ENTRIES 16
1.1 root 74:
1.1.1.15 root 75: struct e820_entry {
76: uint64_t address;
77: uint64_t length;
78: uint32_t type;
1.1.1.16 root 79: } __attribute((__packed__, __aligned__(4)));
1.1.1.15 root 80:
81: struct e820_table {
82: uint32_t count;
83: struct e820_entry entry[E820_NR_ENTRIES];
1.1.1.16 root 84: } __attribute((__packed__, __aligned__(4)));
1.1.1.9 root 85:
1.1.1.15 root 86: static struct e820_table e820_table;
1.1.1.18! root 87: struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
1.1.1.15 root 88:
89: void isa_irq_handler(void *opaque, int n, int level)
1.1.1.9 root 90: {
1.1.1.12 root 91: IsaIrqState *isa = (IsaIrqState *)opaque;
1.1.1.9 root 92:
1.1.1.15 root 93: DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n);
1.1.1.12 root 94: if (n < 16) {
95: qemu_set_irq(isa->i8259[n], level);
96: }
97: if (isa->ioapic)
98: qemu_set_irq(isa->ioapic[n], level);
99: };
1.1.1.9 root 100:
1.1 root 101: static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
102: {
103: }
104:
105: /* MSDOS compatibility mode FPU exception support */
1.1.1.6 root 106: static qemu_irq ferr_irq;
1.1.1.15 root 107:
108: void pc_register_ferr_irq(qemu_irq irq)
109: {
110: ferr_irq = irq;
111: }
112:
1.1 root 113: /* XXX: add IGNNE support */
114: void cpu_set_ferr(CPUX86State *s)
115: {
1.1.1.6 root 116: qemu_irq_raise(ferr_irq);
1.1 root 117: }
118:
119: static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
120: {
1.1.1.6 root 121: qemu_irq_lower(ferr_irq);
1.1 root 122: }
123:
124: /* TSC handling */
125: uint64_t cpu_get_tsc(CPUX86State *env)
126: {
1.1.1.12 root 127: return cpu_get_ticks();
1.1 root 128: }
129:
1.1.1.5 root 130: /* SMM support */
1.1.1.15 root 131:
132: static cpu_set_smm_t smm_set;
133: static void *smm_arg;
134:
135: void cpu_smm_register(cpu_set_smm_t callback, void *arg)
136: {
137: assert(smm_set == NULL);
138: assert(smm_arg == NULL);
139: smm_set = callback;
140: smm_arg = arg;
141: }
142:
1.1.1.5 root 143: void cpu_smm_update(CPUState *env)
144: {
1.1.1.15 root 145: if (smm_set && smm_arg && env == first_cpu)
146: smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
1.1.1.5 root 147: }
148:
149:
1.1 root 150: /* IRQ handling */
151: int cpu_get_pic_interrupt(CPUState *env)
152: {
153: int intno;
154:
1.1.1.15 root 155: intno = apic_get_interrupt(env->apic_state);
1.1 root 156: if (intno >= 0) {
157: /* set irq request if a PIC irq is still pending */
158: /* XXX: improve that */
1.1.1.6 root 159: pic_update_irq(isa_pic);
1.1 root 160: return intno;
161: }
162: /* read the irq from the PIC */
1.1.1.15 root 163: if (!apic_accept_pic_intr(env->apic_state)) {
1.1.1.6 root 164: return -1;
1.1.1.15 root 165: }
1.1.1.6 root 166:
1.1 root 167: intno = pic_read_irq(isa_pic);
168: return intno;
169: }
170:
1.1.1.6 root 171: static void pic_irq_request(void *opaque, int irq, int level)
1.1 root 172: {
1.1.1.7 root 173: CPUState *env = first_cpu;
174:
1.1.1.15 root 175: DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
1.1.1.7 root 176: if (env->apic_state) {
177: while (env) {
1.1.1.15 root 178: if (apic_accept_pic_intr(env->apic_state)) {
179: apic_deliver_pic_intr(env->apic_state, level);
180: }
1.1.1.7 root 181: env = env->next_cpu;
182: }
183: } else {
184: if (level)
185: cpu_interrupt(env, CPU_INTERRUPT_HARD);
186: else
187: cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
188: }
1.1 root 189: }
190:
191: /* PC cmos mappings */
192:
193: #define REG_EQUIPMENT_BYTE 0x14
194:
1.1.1.18! root 195: static int cmos_get_fd_drive_type(FDriveType fd0)
1.1 root 196: {
197: int val;
198:
199: switch (fd0) {
1.1.1.18! root 200: case FDRIVE_DRV_144:
1.1 root 201: /* 1.44 Mb 3"5 drive */
202: val = 4;
203: break;
1.1.1.18! root 204: case FDRIVE_DRV_288:
1.1 root 205: /* 2.88 Mb 3"5 drive */
206: val = 5;
207: break;
1.1.1.18! root 208: case FDRIVE_DRV_120:
1.1 root 209: /* 1.2 Mb 5"5 drive */
210: val = 2;
211: break;
1.1.1.18! root 212: case FDRIVE_DRV_NONE:
1.1 root 213: default:
214: val = 0;
215: break;
216: }
217: return val;
218: }
219:
1.1.1.15 root 220: static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
221: ISADevice *s)
1.1 root 222: {
223: int cylinders, heads, sectors;
224: bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors);
225: rtc_set_memory(s, type_ofs, 47);
226: rtc_set_memory(s, info_ofs, cylinders);
227: rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
228: rtc_set_memory(s, info_ofs + 2, heads);
229: rtc_set_memory(s, info_ofs + 3, 0xff);
230: rtc_set_memory(s, info_ofs + 4, 0xff);
231: rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
232: rtc_set_memory(s, info_ofs + 6, cylinders);
233: rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
234: rtc_set_memory(s, info_ofs + 8, sectors);
235: }
236:
1.1.1.6 root 237: /* convert boot_device letter to something recognizable by the bios */
238: static int boot_device2nibble(char boot_device)
239: {
240: switch(boot_device) {
241: case 'a':
242: case 'b':
243: return 0x01; /* floppy boot */
244: case 'c':
245: return 0x02; /* hard drive boot */
246: case 'd':
247: return 0x03; /* CD-ROM boot */
248: case 'n':
249: return 0x04; /* Network boot */
250: }
251: return 0;
252: }
253:
1.1.1.15 root 254: static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
1.1.1.7 root 255: {
256: #define PC_MAX_BOOT_DEVICES 3
257: int nbds, bds[3] = { 0, };
258: int i;
259:
260: nbds = strlen(boot_device);
261: if (nbds > PC_MAX_BOOT_DEVICES) {
1.1.1.15 root 262: error_report("Too many boot devices for PC");
1.1.1.7 root 263: return(1);
264: }
265: for (i = 0; i < nbds; i++) {
266: bds[i] = boot_device2nibble(boot_device[i]);
267: if (bds[i] == 0) {
1.1.1.15 root 268: error_report("Invalid boot device for PC: '%c'",
269: boot_device[i]);
1.1.1.7 root 270: return(1);
271: }
272: }
273: rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
1.1.1.15 root 274: rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
1.1.1.7 root 275: return(0);
276: }
277:
1.1.1.15 root 278: static int pc_boot_set(void *opaque, const char *boot_device)
1.1 root 279: {
1.1.1.15 root 280: return set_boot_dev(opaque, boot_device, 0);
281: }
282:
283: typedef struct pc_cmos_init_late_arg {
284: ISADevice *rtc_state;
285: BusState *idebus0, *idebus1;
286: } pc_cmos_init_late_arg;
287:
288: static void pc_cmos_init_late(void *opaque)
289: {
290: pc_cmos_init_late_arg *arg = opaque;
291: ISADevice *s = arg->rtc_state;
1.1 root 292: int val;
1.1.1.15 root 293: BlockDriverState *hd_table[4];
1.1 root 294: int i;
295:
1.1.1.15 root 296: ide_get_bs(hd_table, arg->idebus0);
297: ide_get_bs(hd_table + 2, arg->idebus1);
298:
299: rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
300: if (hd_table[0])
301: cmos_init_hd(0x19, 0x1b, hd_table[0], s);
302: if (hd_table[1])
303: cmos_init_hd(0x1a, 0x24, hd_table[1], s);
304:
305: val = 0;
306: for (i = 0; i < 4; i++) {
307: if (hd_table[i]) {
308: int cylinders, heads, sectors, translation;
309: /* NOTE: bdrv_get_geometry_hint() returns the physical
310: geometry. It is always such that: 1 <= sects <= 63, 1
311: <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
312: geometry can be different if a translation is done. */
313: translation = bdrv_get_translation_hint(hd_table[i]);
314: if (translation == BIOS_ATA_TRANSLATION_AUTO) {
315: bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors);
316: if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
317: /* No translation. */
318: translation = 0;
319: } else {
320: /* LBA translation. */
321: translation = 1;
322: }
323: } else {
324: translation--;
325: }
326: val |= translation << (i * 2);
327: }
328: }
329: rtc_set_memory(s, 0x39, val);
330:
331: qemu_unregister_reset(pc_cmos_init_late, opaque);
332: }
333:
334: void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
335: const char *boot_device,
336: BusState *idebus0, BusState *idebus1,
1.1.1.18! root 337: ISADevice *s)
1.1.1.15 root 338: {
1.1.1.18! root 339: int val, nb, nb_heads, max_track, last_sect, i;
! 340: FDriveType fd_type[2];
! 341: DriveInfo *fd[2];
1.1.1.15 root 342: static pc_cmos_init_late_arg arg;
343:
1.1 root 344: /* various important CMOS locations needed by PC/Bochs bios */
345:
346: /* memory size */
347: val = 640; /* base memory in K */
348: rtc_set_memory(s, 0x15, val);
349: rtc_set_memory(s, 0x16, val >> 8);
350:
351: val = (ram_size / 1024) - 1024;
352: if (val > 65535)
353: val = 65535;
354: rtc_set_memory(s, 0x17, val);
355: rtc_set_memory(s, 0x18, val >> 8);
356: rtc_set_memory(s, 0x30, val);
357: rtc_set_memory(s, 0x31, val >> 8);
358:
1.1.1.7 root 359: if (above_4g_mem_size) {
360: rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
361: rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
362: rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
363: }
364:
1.1 root 365: if (ram_size > (16 * 1024 * 1024))
366: val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
367: else
368: val = 0;
369: if (val > 65535)
370: val = 65535;
371: rtc_set_memory(s, 0x34, val);
372: rtc_set_memory(s, 0x35, val >> 8);
1.1.1.6 root 373:
1.1.1.7 root 374: /* set the number of CPU */
375: rtc_set_memory(s, 0x5f, smp_cpus - 1);
376:
1.1.1.6 root 377: /* set boot devices, and disable floppy signature check if requested */
1.1.1.15 root 378: if (set_boot_dev(s, boot_device, fd_bootchk)) {
1.1.1.6 root 379: exit(1);
1.1 root 380: }
381:
382: /* floppy type */
1.1.1.18! root 383: for (i = 0; i < 2; i++) {
! 384: fd[i] = drive_get(IF_FLOPPY, 0, i);
! 385: if (fd[i] && bdrv_is_inserted(fd[i]->bdrv)) {
! 386: bdrv_get_floppy_geometry_hint(fd[i]->bdrv, &nb_heads, &max_track,
! 387: &last_sect, FDRIVE_DRV_NONE,
! 388: &fd_type[i]);
! 389: } else {
! 390: fd_type[i] = FDRIVE_DRV_NONE;
! 391: }
! 392: }
! 393: val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
! 394: cmos_get_fd_drive_type(fd_type[1]);
1.1 root 395: rtc_set_memory(s, 0x10, val);
1.1.1.6 root 396:
1.1 root 397: val = 0;
398: nb = 0;
1.1.1.18! root 399: if (fd_type[0] < FDRIVE_DRV_NONE) {
1.1 root 400: nb++;
1.1.1.18! root 401: }
! 402: if (fd_type[1] < FDRIVE_DRV_NONE) {
1.1 root 403: nb++;
1.1.1.18! root 404: }
1.1 root 405: switch (nb) {
406: case 0:
407: break;
408: case 1:
409: val |= 0x01; /* 1 drive, ready for boot */
410: break;
411: case 2:
412: val |= 0x41; /* 2 drives, ready for boot */
413: break;
414: }
415: val |= 0x02; /* FPU is there */
416: val |= 0x04; /* PS/2 mouse installed */
417: rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
418:
419: /* hard drives */
1.1.1.15 root 420: arg.rtc_state = s;
421: arg.idebus0 = idebus0;
422: arg.idebus1 = idebus1;
423: qemu_register_reset(pc_cmos_init_late, &arg);
1.1.1.2 root 424: }
425:
1.1.1.16 root 426: /* port 92 stuff: could be split off */
427: typedef struct Port92State {
428: ISADevice dev;
429: uint8_t outport;
430: qemu_irq *a20_out;
431: } Port92State;
432:
433: static void port92_write(void *opaque, uint32_t addr, uint32_t val)
434: {
435: Port92State *s = opaque;
436:
437: DPRINTF("port92: write 0x%02x\n", val);
438: s->outport = val;
439: qemu_set_irq(*s->a20_out, (val >> 1) & 1);
440: if (val & 1) {
441: qemu_system_reset_request();
442: }
443: }
444:
445: static uint32_t port92_read(void *opaque, uint32_t addr)
446: {
447: Port92State *s = opaque;
448: uint32_t ret;
449:
450: ret = s->outport;
451: DPRINTF("port92: read 0x%02x\n", ret);
452: return ret;
453: }
454:
455: static void port92_init(ISADevice *dev, qemu_irq *a20_out)
456: {
457: Port92State *s = DO_UPCAST(Port92State, dev, dev);
458:
459: s->a20_out = a20_out;
460: }
461:
462: static const VMStateDescription vmstate_port92_isa = {
463: .name = "port92",
464: .version_id = 1,
465: .minimum_version_id = 1,
466: .minimum_version_id_old = 1,
467: .fields = (VMStateField []) {
468: VMSTATE_UINT8(outport, Port92State),
469: VMSTATE_END_OF_LIST()
470: }
471: };
472:
473: static void port92_reset(DeviceState *d)
474: {
475: Port92State *s = container_of(d, Port92State, dev.qdev);
476:
477: s->outport &= ~1;
478: }
479:
480: static int port92_initfn(ISADevice *dev)
481: {
482: Port92State *s = DO_UPCAST(Port92State, dev, dev);
483:
484: register_ioport_read(0x92, 1, 1, port92_read, s);
485: register_ioport_write(0x92, 1, 1, port92_write, s);
486: isa_init_ioport(dev, 0x92);
487: s->outport = 0;
488: return 0;
489: }
490:
491: static ISADeviceInfo port92_info = {
492: .qdev.name = "port92",
493: .qdev.size = sizeof(Port92State),
494: .qdev.vmsd = &vmstate_port92_isa,
495: .qdev.no_user = 1,
496: .qdev.reset = port92_reset,
497: .init = port92_initfn,
498: };
499:
500: static void port92_register(void)
501: {
502: isa_qdev_register(&port92_info);
503: }
504: device_init(port92_register)
505:
1.1.1.15 root 506: static void handle_a20_line_change(void *opaque, int irq, int level)
1.1.1.2 root 507: {
1.1.1.15 root 508: CPUState *cpu = opaque;
1.1.1.2 root 509:
1.1.1.15 root 510: /* XXX: send to all CPUs ? */
1.1.1.16 root 511: /* XXX: add logic to handle multiple A20 line sources */
1.1.1.15 root 512: cpu_x86_set_a20(cpu, level);
1.1 root 513: }
514:
515: /***********************************************************/
516: /* Bochs BIOS debug ports */
517:
1.1.1.6 root 518: static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
1.1 root 519: {
520: static const char shutdown_str[8] = "Shutdown";
521: static int shutdown_index = 0;
1.1.1.6 root 522:
1.1 root 523: switch(addr) {
524: /* Bochs BIOS messages */
525: case 0x400:
526: case 0x401:
1.1.1.16 root 527: /* used to be panic, now unused */
528: break;
1.1 root 529: case 0x402:
530: case 0x403:
531: #ifdef DEBUG_BIOS
532: fprintf(stderr, "%c", val);
533: #endif
534: break;
535: case 0x8900:
536: /* same as Bochs power off */
537: if (val == shutdown_str[shutdown_index]) {
538: shutdown_index++;
539: if (shutdown_index == 8) {
540: shutdown_index = 0;
541: qemu_system_shutdown_request();
542: }
543: } else {
544: shutdown_index = 0;
545: }
546: break;
547:
548: /* LGPL'ed VGA BIOS messages */
549: case 0x501:
550: case 0x502:
551: fprintf(stderr, "VGA BIOS panic, line %d\n", val);
552: exit(1);
553: case 0x500:
554: case 0x503:
555: #ifdef DEBUG_BIOS
556: fprintf(stderr, "%c", val);
557: #endif
558: break;
559: }
560: }
561:
1.1.1.15 root 562: int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
563: {
1.1.1.16 root 564: int index = le32_to_cpu(e820_table.count);
1.1.1.15 root 565: struct e820_entry *entry;
566:
567: if (index >= E820_NR_ENTRIES)
568: return -EBUSY;
1.1.1.16 root 569: entry = &e820_table.entry[index++];
1.1.1.15 root 570:
1.1.1.16 root 571: entry->address = cpu_to_le64(address);
572: entry->length = cpu_to_le64(length);
573: entry->type = cpu_to_le32(type);
1.1.1.15 root 574:
1.1.1.16 root 575: e820_table.count = cpu_to_le32(index);
576: return index;
1.1.1.15 root 577: }
578:
1.1.1.11 root 579: static void *bochs_bios_init(void)
1.1 root 580: {
1.1.1.7 root 581: void *fw_cfg;
1.1.1.11 root 582: uint8_t *smbios_table;
583: size_t smbios_len;
584: uint64_t *numa_fw_cfg;
585: int i, j;
1.1.1.7 root 586:
1.1 root 587: register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
588: register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
589: register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
590: register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
591: register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
592:
593: register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
594: register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
595: register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
596: register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
1.1.1.7 root 597:
598: fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
1.1.1.11 root 599:
1.1.1.7 root 600: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
601: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1.1.1.11 root 602: fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
603: acpi_tables_len);
1.1.1.12 root 604: fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
1.1.1.11 root 605:
606: smbios_table = smbios_get_table(&smbios_len);
607: if (smbios_table)
608: fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
609: smbios_table, smbios_len);
1.1.1.15 root 610: fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
611: sizeof(struct e820_table));
1.1.1.11 root 612:
1.1.1.15 root 613: fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
614: sizeof(struct hpet_fw_config));
1.1.1.11 root 615: /* allocate memory for the NUMA channel: one (64bit) word for the number
616: * of nodes, one word for each VCPU->node and one word for each node to
617: * hold the amount of memory.
618: */
619: numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
620: numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
621: for (i = 0; i < smp_cpus; i++) {
622: for (j = 0; j < nb_numa_nodes; j++) {
623: if (node_cpumask[j] & (1 << i)) {
624: numa_fw_cfg[i + 1] = cpu_to_le64(j);
625: break;
626: }
627: }
628: }
629: for (i = 0; i < nb_numa_nodes; i++) {
630: numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
631: }
632: fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
633: (1 + smp_cpus + nb_numa_nodes) * 8);
634:
635: return fw_cfg;
1.1 root 636: }
637:
1.1.1.6 root 638: static long get_file_size(FILE *f)
639: {
640: long where, size;
641:
642: /* XXX: on Unix systems, using fstat() probably makes more sense */
643:
644: where = ftell(f);
645: fseek(f, 0, SEEK_END);
646: size = ftell(f);
647: fseek(f, where, SEEK_SET);
648:
649: return size;
650: }
651:
1.1.1.11 root 652: static void load_linux(void *fw_cfg,
1.1.1.7 root 653: const char *kernel_filename,
1.1.1.6 root 654: const char *initrd_filename,
1.1.1.10 root 655: const char *kernel_cmdline,
1.1.1.12 root 656: target_phys_addr_t max_ram_size)
1.1.1.6 root 657: {
658: uint16_t protocol;
1.1.1.11 root 659: int setup_size, kernel_size, initrd_size = 0, cmdline_size;
1.1.1.6 root 660: uint32_t initrd_max;
1.1.1.12 root 661: uint8_t header[8192], *setup, *kernel, *initrd_data;
1.1.1.11 root 662: target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
1.1.1.12 root 663: FILE *f;
1.1.1.11 root 664: char *vmode;
1.1.1.6 root 665:
666: /* Align to 16 bytes as a paranoia measure */
667: cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
668:
669: /* load the kernel header */
670: f = fopen(kernel_filename, "rb");
671: if (!f || !(kernel_size = get_file_size(f)) ||
1.1.1.11 root 672: fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
673: MIN(ARRAY_SIZE(header), kernel_size)) {
1.1.1.12 root 674: fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
675: kernel_filename, strerror(errno));
1.1.1.6 root 676: exit(1);
677: }
678:
679: /* kernel protocol version */
680: #if 0
681: fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
682: #endif
683: if (ldl_p(header+0x202) == 0x53726448)
684: protocol = lduw_p(header+0x206);
1.1.1.11 root 685: else {
686: /* This looks like a multiboot kernel. If it is, let's stop
687: treating it like a Linux kernel. */
1.1.1.15 root 688: if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
689: kernel_cmdline, kernel_size, header))
1.1.1.12 root 690: return;
1.1.1.6 root 691: protocol = 0;
1.1.1.11 root 692: }
1.1.1.6 root 693:
694: if (protocol < 0x200 || !(header[0x211] & 0x01)) {
695: /* Low kernel */
1.1.1.7 root 696: real_addr = 0x90000;
697: cmdline_addr = 0x9a000 - cmdline_size;
698: prot_addr = 0x10000;
1.1.1.6 root 699: } else if (protocol < 0x202) {
700: /* High but ancient kernel */
1.1.1.7 root 701: real_addr = 0x90000;
702: cmdline_addr = 0x9a000 - cmdline_size;
703: prot_addr = 0x100000;
1.1.1.6 root 704: } else {
705: /* High and recent kernel */
1.1.1.7 root 706: real_addr = 0x10000;
707: cmdline_addr = 0x20000;
708: prot_addr = 0x100000;
1.1.1.6 root 709: }
710:
711: #if 0
712: fprintf(stderr,
1.1.1.7 root 713: "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
714: "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
715: "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
716: real_addr,
717: cmdline_addr,
718: prot_addr);
1.1.1.6 root 719: #endif
720:
721: /* highest address for loading the initrd */
722: if (protocol >= 0x203)
723: initrd_max = ldl_p(header+0x22c);
724: else
725: initrd_max = 0x37ffffff;
726:
1.1.1.10 root 727: if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
728: initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
1.1.1.6 root 729:
1.1.1.12 root 730: fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
731: fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
732: fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
733: (uint8_t*)strdup(kernel_cmdline),
734: strlen(kernel_cmdline)+1);
1.1.1.6 root 735:
736: if (protocol >= 0x202) {
1.1.1.7 root 737: stl_p(header+0x228, cmdline_addr);
1.1.1.6 root 738: } else {
739: stw_p(header+0x20, 0xA33F);
740: stw_p(header+0x22, cmdline_addr-real_addr);
741: }
742:
1.1.1.11 root 743: /* handle vga= parameter */
744: vmode = strstr(kernel_cmdline, "vga=");
745: if (vmode) {
746: unsigned int video_mode;
747: /* skip "vga=" */
748: vmode += 4;
749: if (!strncmp(vmode, "normal", 6)) {
750: video_mode = 0xffff;
751: } else if (!strncmp(vmode, "ext", 3)) {
752: video_mode = 0xfffe;
753: } else if (!strncmp(vmode, "ask", 3)) {
754: video_mode = 0xfffd;
755: } else {
756: video_mode = strtol(vmode, NULL, 0);
757: }
758: stw_p(header+0x1fa, video_mode);
759: }
760:
1.1.1.6 root 761: /* loader type */
762: /* High nybble = B reserved for Qemu; low nybble is revision number.
763: If this code is substantially changed, you may want to consider
764: incrementing the revision. */
765: if (protocol >= 0x200)
766: header[0x210] = 0xB0;
767:
768: /* heap */
769: if (protocol >= 0x201) {
770: header[0x211] |= 0x80; /* CAN_USE_HEAP */
771: stw_p(header+0x224, cmdline_addr-real_addr-0x200);
772: }
773:
774: /* load initrd */
775: if (initrd_filename) {
776: if (protocol < 0x200) {
777: fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
778: exit(1);
779: }
780:
1.1.1.12 root 781: initrd_size = get_image_size(initrd_filename);
1.1.1.15 root 782: if (initrd_size < 0) {
783: fprintf(stderr, "qemu: error reading initrd %s\n",
784: initrd_filename);
785: exit(1);
786: }
787:
1.1.1.12 root 788: initrd_addr = (initrd_max-initrd_size) & ~4095;
1.1.1.6 root 789:
1.1.1.12 root 790: initrd_data = qemu_malloc(initrd_size);
791: load_image(initrd_filename, initrd_data);
1.1.1.6 root 792:
1.1.1.12 root 793: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
794: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
795: fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
1.1.1.6 root 796:
1.1.1.7 root 797: stl_p(header+0x218, initrd_addr);
1.1.1.6 root 798: stl_p(header+0x21c, initrd_size);
799: }
800:
1.1.1.12 root 801: /* load kernel and setup */
1.1.1.6 root 802: setup_size = header[0x1f1];
803: if (setup_size == 0)
804: setup_size = 4;
805: setup_size = (setup_size+1)*512;
1.1.1.12 root 806: kernel_size -= setup_size;
1.1.1.11 root 807:
1.1.1.12 root 808: setup = qemu_malloc(setup_size);
809: kernel = qemu_malloc(kernel_size);
810: fseek(f, 0, SEEK_SET);
1.1.1.15 root 811: if (fread(setup, 1, setup_size, f) != setup_size) {
812: fprintf(stderr, "fread() failed\n");
813: exit(1);
814: }
815: if (fread(kernel, 1, kernel_size, f) != kernel_size) {
816: fprintf(stderr, "fread() failed\n");
817: exit(1);
818: }
1.1.1.6 root 819: fclose(f);
1.1.1.12 root 820: memcpy(setup, header, MIN(sizeof(header), setup_size));
821:
822: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
823: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
824: fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1.1.1.6 root 825:
1.1.1.12 root 826: fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
827: fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
828: fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1.1.1.9 root 829:
1.1.1.16 root 830: option_rom[nb_option_roms].name = "linuxboot.bin";
831: option_rom[nb_option_roms].bootindex = 0;
1.1.1.12 root 832: nb_option_roms++;
1.1.1.6 root 833: }
834:
1.1 root 835: #define NE2000_NB_MAX 6
836:
1.1.1.12 root 837: static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
838: 0x280, 0x380 };
839: static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1.1 root 840:
1.1.1.12 root 841: static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
842: static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
1.1 root 843:
1.1.1.15 root 844: void pc_init_ne2k_isa(NICInfo *nd)
1.1.1.3 root 845: {
846: static int nb_ne2k = 0;
847:
848: if (nb_ne2k == NE2000_NB_MAX)
849: return;
1.1.1.12 root 850: isa_ne2000_init(ne2000_io[nb_ne2k],
851: ne2000_irq[nb_ne2k], nd);
1.1.1.3 root 852: nb_ne2k++;
853: }
854:
1.1.1.11 root 855: int cpu_is_bsp(CPUState *env)
856: {
1.1.1.15 root 857: /* We hard-wire the BSP to the first CPU. */
858: return env->cpu_index == 0;
859: }
860:
861: DeviceState *cpu_get_current_apic(void)
862: {
863: if (cpu_single_env) {
864: return cpu_single_env->apic_state;
865: } else {
866: return NULL;
867: }
868: }
869:
870: static DeviceState *apic_init(void *env, uint8_t apic_id)
871: {
872: DeviceState *dev;
873: SysBusDevice *d;
874: static int apic_mapped;
875:
876: dev = qdev_create(NULL, "apic");
877: qdev_prop_set_uint8(dev, "id", apic_id);
878: qdev_prop_set_ptr(dev, "cpu_env", env);
879: qdev_init_nofail(dev);
880: d = sysbus_from_qdev(dev);
881:
882: /* XXX: mapping more APICs at the same memory location */
883: if (apic_mapped == 0) {
884: /* NOTE: the APIC is directly connected to the CPU - it is not
885: on the global memory bus. */
886: /* XXX: what if the base changes? */
887: sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
888: apic_mapped = 1;
889: }
890:
891: msix_supported = 1;
892:
893: return dev;
894: }
895:
896: /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
897: BIOS will read it and start S3 resume at POST Entry */
898: void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
899: {
900: ISADevice *s = opaque;
901:
902: if (level) {
903: rtc_set_memory(s, 0xF, 0xFE);
904: }
905: }
906:
907: void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
908: {
909: CPUState *s = opaque;
910:
911: if (level) {
912: cpu_interrupt(s, CPU_INTERRUPT_SMI);
913: }
914: }
915:
916: static void pc_cpu_reset(void *opaque)
917: {
918: CPUState *env = opaque;
919:
920: cpu_reset(env);
921: env->halted = !cpu_is_bsp(env);
1.1.1.11 root 922: }
923:
924: static CPUState *pc_new_cpu(const char *cpu_model)
925: {
926: CPUState *env;
927:
928: env = cpu_init(cpu_model);
929: if (!env) {
930: fprintf(stderr, "Unable to find x86 CPU definition\n");
931: exit(1);
932: }
933: if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
934: env->cpuid_apic_id = env->cpu_index;
1.1.1.15 root 935: env->apic_state = apic_init(env, env->cpuid_apic_id);
1.1.1.11 root 936: }
1.1.1.15 root 937: qemu_register_reset(pc_cpu_reset, env);
938: pc_cpu_reset(env);
1.1.1.11 root 939: return env;
940: }
941:
1.1.1.15 root 942: void pc_cpus_init(const char *cpu_model)
943: {
944: int i;
945:
946: /* init CPUs */
947: if (cpu_model == NULL) {
948: #ifdef TARGET_X86_64
949: cpu_model = "qemu64";
950: #else
951: cpu_model = "qemu32";
952: #endif
953: }
954:
955: for(i = 0; i < smp_cpus; i++) {
956: pc_new_cpu(cpu_model);
957: }
958: }
959:
1.1.1.18! root 960: void pc_memory_init(const char *kernel_filename,
1.1.1.15 root 961: const char *kernel_cmdline,
962: const char *initrd_filename,
1.1.1.18! root 963: ram_addr_t below_4g_mem_size,
! 964: ram_addr_t above_4g_mem_size)
1.1 root 965: {
1.1.1.11 root 966: char *filename;
1.1.1.6 root 967: int ret, linux_boot, i;
1.1.1.11 root 968: ram_addr_t ram_addr, bios_offset, option_rom_offset;
1.1.1.12 root 969: int bios_size, isa_bios_size;
1.1.1.11 root 970: void *fw_cfg;
1.1 root 971:
1.1.1.15 root 972: linux_boot = (kernel_filename != NULL);
1.1.1.7 root 973:
1.1 root 974: /* allocate RAM */
1.1.1.15 root 975: ram_addr = qemu_ram_alloc(NULL, "pc.ram",
976: below_4g_mem_size + above_4g_mem_size);
1.1.1.7 root 977: cpu_register_physical_memory(0, 0xa0000, ram_addr);
978: cpu_register_physical_memory(0x100000,
979: below_4g_mem_size - 0x100000,
1.1.1.15 root 980: ram_addr + 0x100000);
1.1.1.7 root 981: if (above_4g_mem_size > 0) {
1.1.1.15 root 982: cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size,
983: ram_addr + below_4g_mem_size);
1.1.1.7 root 984: }
1.1 root 985:
1.1.1.6 root 986: /* BIOS load */
987: if (bios_name == NULL)
988: bios_name = BIOS_FILENAME;
1.1.1.11 root 989: filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
990: if (filename) {
991: bios_size = get_image_size(filename);
992: } else {
993: bios_size = -1;
994: }
1.1.1.6 root 995: if (bios_size <= 0 ||
996: (bios_size % 65536) != 0) {
1.1 root 997: goto bios_error;
998: }
1.1.1.15 root 999: bios_offset = qemu_ram_alloc(NULL, "pc.bios", bios_size);
1.1.1.16 root 1000: ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
1.1.1.12 root 1001: if (ret != 0) {
1.1 root 1002: bios_error:
1.1.1.11 root 1003: fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1.1 root 1004: exit(1);
1005: }
1.1.1.11 root 1006: if (filename) {
1007: qemu_free(filename);
1.1.1.7 root 1008: }
1.1 root 1009: /* map the last 128KB of the BIOS in ISA space */
1010: isa_bios_size = bios_size;
1011: if (isa_bios_size > (128 * 1024))
1012: isa_bios_size = 128 * 1024;
1.1.1.6 root 1013: cpu_register_physical_memory(0x100000 - isa_bios_size,
1014: isa_bios_size,
1.1 root 1015: (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
1.1.1.5 root 1016:
1.1.1.15 root 1017: option_rom_offset = qemu_ram_alloc(NULL, "pc.rom", PC_ROM_SIZE);
1.1.1.12 root 1018: cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
1.1.1.5 root 1019:
1.1 root 1020: /* map all the bios at the top of memory */
1.1.1.6 root 1021: cpu_register_physical_memory((uint32_t)(-bios_size),
1.1 root 1022: bios_size, bios_offset | IO_MEM_ROM);
1.1.1.6 root 1023:
1.1.1.11 root 1024: fw_cfg = bochs_bios_init();
1.1.1.13 root 1025: rom_set_fw(fw_cfg);
1.1.1.11 root 1026:
1027: if (linux_boot) {
1.1.1.12 root 1028: load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1.1.1.11 root 1029: }
1030:
1031: for (i = 0; i < nb_option_roms; i++) {
1.1.1.16 root 1032: rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1.1.1.11 root 1033: }
1.1.1.15 root 1034: }
1.1 root 1035:
1.1.1.15 root 1036: qemu_irq *pc_allocate_cpu_irq(void)
1037: {
1038: return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1039: }
1.1 root 1040:
1.1.1.15 root 1041: void pc_vga_init(PCIBus *pci_bus)
1042: {
1.1 root 1043: if (cirrus_vga_enabled) {
1.1.1.15 root 1044: if (pci_bus) {
1.1.1.11 root 1045: pci_cirrus_vga_init(pci_bus);
1.1 root 1046: } else {
1.1.1.11 root 1047: isa_cirrus_vga_init();
1.1 root 1048: }
1.1.1.6 root 1049: } else if (vmsvga_enabled) {
1.1.1.18! root 1050: if (pci_bus) {
! 1051: if (!pci_vmsvga_init(pci_bus)) {
! 1052: fprintf(stderr, "Warning: vmware_vga not available,"
! 1053: " using standard VGA instead\n");
! 1054: pci_vga_init(pci_bus);
! 1055: }
! 1056: } else {
1.1.1.6 root 1057: fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1.1.1.18! root 1058: }
1.1.1.16 root 1059: #ifdef CONFIG_SPICE
1060: } else if (qxl_enabled) {
1061: if (pci_bus)
1062: pci_create_simple(pci_bus, -1, "qxl-vga");
1063: else
1064: fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
1065: #endif
1.1.1.7 root 1066: } else if (std_vga_enabled) {
1.1.1.15 root 1067: if (pci_bus) {
1.1.1.16 root 1068: pci_vga_init(pci_bus);
1.1.1.5 root 1069: } else {
1.1.1.11 root 1070: isa_vga_init();
1.1.1.5 root 1071: }
1.1 root 1072: }
1.1.1.18! root 1073:
! 1074: /*
! 1075: * sga does not suppress normal vga output. So a machine can have both a
! 1076: * vga card and sga manually enabled. Output will be seen on both.
! 1077: * For nographic case, sga is enabled at all times
! 1078: */
! 1079: if (display_type == DT_NOGRAPHIC) {
! 1080: isa_create_simple("sga");
! 1081: }
1.1.1.15 root 1082: }
1.1 root 1083:
1.1.1.15 root 1084: static void cpu_request_exit(void *opaque, int irq, int level)
1085: {
1086: CPUState *env = cpu_single_env;
1.1.1.7 root 1087:
1.1.1.15 root 1088: if (env && level) {
1089: cpu_exit(env);
1090: }
1091: }
1092:
1093: void pc_basic_device_init(qemu_irq *isa_irq,
1.1.1.18! root 1094: ISADevice **rtc_state,
! 1095: bool no_vmport)
1.1.1.15 root 1096: {
1097: int i;
1098: DriveInfo *fd[MAX_FD];
1099: qemu_irq rtc_irq = NULL;
1100: qemu_irq *a20_line;
1.1.1.18! root 1101: ISADevice *i8042, *port92, *vmmouse, *pit;
1.1.1.15 root 1102: qemu_irq *cpu_exit_irq;
1103:
1104: register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1105:
1106: register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1.1 root 1107:
1.1.1.15 root 1108: if (!no_hpet) {
1.1.1.18! root 1109: DeviceState *hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1.1 root 1110:
1.1.1.18! root 1111: if (hpet) {
! 1112: for (i = 0; i < 24; i++) {
! 1113: sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);
! 1114: }
! 1115: rtc_irq = qdev_get_gpio_in(hpet, 0);
1.1.1.15 root 1116: }
1.1 root 1117: }
1.1.1.15 root 1118: *rtc_state = rtc_init(2000, rtc_irq);
1119:
1120: qemu_register_boot_set(pc_boot_set, *rtc_state);
1121:
1.1.1.18! root 1122: pit = pit_init(0x40, 0);
1.1.1.3 root 1123: pcspk_init(pit);
1.1 root 1124:
1125: for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1126: if (serial_hds[i]) {
1.1.1.12 root 1127: serial_isa_init(i, serial_hds[i]);
1.1 root 1128: }
1129: }
1130:
1131: for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1132: if (parallel_hds[i]) {
1.1.1.12 root 1133: parallel_init(i, parallel_hds[i]);
1.1 root 1134: }
1135: }
1136:
1.1.1.16 root 1137: a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1.1.1.15 root 1138: i8042 = isa_create_simple("i8042");
1.1.1.16 root 1139: i8042_setup_a20_line(i8042, &a20_line[0]);
1.1.1.18! root 1140: if (!no_vmport) {
! 1141: vmport_init();
! 1142: vmmouse = isa_try_create("vmmouse");
! 1143: } else {
! 1144: vmmouse = NULL;
! 1145: }
! 1146: if (vmmouse) {
! 1147: qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
! 1148: qdev_init_nofail(&vmmouse->qdev);
! 1149: }
1.1.1.16 root 1150: port92 = isa_create_simple("port92");
1151: port92_init(port92, &a20_line[1]);
1.1.1.7 root 1152:
1.1.1.15 root 1153: cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1154: DMA_init(0, cpu_exit_irq);
1.1 root 1155:
1.1.1.6 root 1156: for(i = 0; i < MAX_FD; i++) {
1.1.1.12 root 1157: fd[i] = drive_get(IF_FLOPPY, 0, i);
1.1.1.6 root 1158: }
1.1.1.18! root 1159: fdctrl_init_isa(fd);
1.1 root 1160: }
1161:
1.1.1.15 root 1162: void pc_pci_device_init(PCIBus *pci_bus)
1.1.1.7 root 1163: {
1.1.1.15 root 1164: int max_bus;
1165: int bus;
1.1.1.7 root 1166:
1.1.1.15 root 1167: max_bus = drive_get_max_bus(IF_SCSI);
1168: for (bus = 0; bus <= max_bus; bus++) {
1169: pci_create_simple(pci_bus, -1, "lsi53c895a");
1.1.1.13 root 1170: }
1.1.1.11 root 1171: }
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