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1.1 root 1: /*
2: * QEMU PC System Emulator
1.1.1.6 root 3: *
1.1 root 4: * Copyright (c) 2003-2004 Fabrice Bellard
1.1.1.6 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.6 root 24: #include "hw.h"
25: #include "pc.h"
1.1.1.15 root 26: #include "apic.h"
1.1.1.6 root 27: #include "fdc.h"
1.1.1.15 root 28: #include "ide.h"
1.1.1.6 root 29: #include "pci.h"
1.1.1.12 root 30: #include "vmware_vga.h"
1.1.1.11 root 31: #include "monitor.h"
1.1.1.7 root 32: #include "fw_cfg.h"
33: #include "hpet_emul.h"
1.1.1.11 root 34: #include "smbios.h"
1.1.1.12 root 35: #include "loader.h"
36: #include "elf.h"
1.1.1.15 root 37: #include "multiboot.h"
38: #include "mc146818rtc.h"
1.1.1.20! root 39: #include "i8254.h"
! 40: #include "pcspk.h"
! 41: #include "msi.h"
1.1.1.15 root 42: #include "sysbus.h"
43: #include "sysemu.h"
1.1.1.20! root 44: #include "kvm.h"
! 45: #include "xen.h"
1.1.1.16 root 46: #include "blockdev.h"
47: #include "ui/qemu-spice.h"
1.1.1.19 root 48: #include "memory.h"
49: #include "exec-memory.h"
1.1.1.20! root 50: #include "arch_init.h"
1.1 root 51:
52: /* output Bochs bios info messages */
53: //#define DEBUG_BIOS
54:
1.1.1.15 root 55: /* debug PC/ISA interrupts */
56: //#define DEBUG_IRQ
57:
58: #ifdef DEBUG_IRQ
59: #define DPRINTF(fmt, ...) \
60: do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
61: #else
62: #define DPRINTF(fmt, ...)
63: #endif
1.1.1.11 root 64:
1.1.1.6 root 65: /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
66: #define ACPI_DATA_SIZE 0x10000
1.1.1.7 root 67: #define BIOS_CFG_IOPORT 0x510
68: #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
1.1.1.11 root 69: #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
1.1.1.12 root 70: #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
1.1.1.15 root 71: #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
72: #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
73:
74: #define MSI_ADDR_BASE 0xfee00000
1.1.1.6 root 75:
1.1.1.15 root 76: #define E820_NR_ENTRIES 16
1.1 root 77:
1.1.1.15 root 78: struct e820_entry {
79: uint64_t address;
80: uint64_t length;
81: uint32_t type;
1.1.1.19 root 82: } QEMU_PACKED __attribute((__aligned__(4)));
1.1.1.15 root 83:
84: struct e820_table {
85: uint32_t count;
86: struct e820_entry entry[E820_NR_ENTRIES];
1.1.1.19 root 87: } QEMU_PACKED __attribute((__aligned__(4)));
1.1.1.9 root 88:
1.1.1.15 root 89: static struct e820_table e820_table;
1.1.1.18 root 90: struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
1.1.1.15 root 91:
1.1.1.19 root 92: void gsi_handler(void *opaque, int n, int level)
1.1.1.9 root 93: {
1.1.1.19 root 94: GSIState *s = opaque;
1.1.1.9 root 95:
1.1.1.19 root 96: DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
97: if (n < ISA_NUM_IRQS) {
98: qemu_set_irq(s->i8259_irq[n], level);
1.1.1.12 root 99: }
1.1.1.19 root 100: qemu_set_irq(s->ioapic_irq[n], level);
101: }
1.1.1.9 root 102:
1.1 root 103: static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
104: {
105: }
106:
107: /* MSDOS compatibility mode FPU exception support */
1.1.1.6 root 108: static qemu_irq ferr_irq;
1.1.1.15 root 109:
110: void pc_register_ferr_irq(qemu_irq irq)
111: {
112: ferr_irq = irq;
113: }
114:
1.1 root 115: /* XXX: add IGNNE support */
116: void cpu_set_ferr(CPUX86State *s)
117: {
1.1.1.6 root 118: qemu_irq_raise(ferr_irq);
1.1 root 119: }
120:
121: static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
122: {
1.1.1.6 root 123: qemu_irq_lower(ferr_irq);
1.1 root 124: }
125:
126: /* TSC handling */
127: uint64_t cpu_get_tsc(CPUX86State *env)
128: {
1.1.1.12 root 129: return cpu_get_ticks();
1.1 root 130: }
131:
1.1.1.5 root 132: /* SMM support */
1.1.1.15 root 133:
134: static cpu_set_smm_t smm_set;
135: static void *smm_arg;
136:
137: void cpu_smm_register(cpu_set_smm_t callback, void *arg)
138: {
139: assert(smm_set == NULL);
140: assert(smm_arg == NULL);
141: smm_set = callback;
142: smm_arg = arg;
143: }
144:
1.1.1.20! root 145: void cpu_smm_update(CPUX86State *env)
1.1.1.5 root 146: {
1.1.1.15 root 147: if (smm_set && smm_arg && env == first_cpu)
148: smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
1.1.1.5 root 149: }
150:
151:
1.1 root 152: /* IRQ handling */
1.1.1.20! root 153: int cpu_get_pic_interrupt(CPUX86State *env)
1.1 root 154: {
155: int intno;
156:
1.1.1.15 root 157: intno = apic_get_interrupt(env->apic_state);
1.1 root 158: if (intno >= 0) {
159: return intno;
160: }
161: /* read the irq from the PIC */
1.1.1.15 root 162: if (!apic_accept_pic_intr(env->apic_state)) {
1.1.1.6 root 163: return -1;
1.1.1.15 root 164: }
1.1.1.6 root 165:
1.1 root 166: intno = pic_read_irq(isa_pic);
167: return intno;
168: }
169:
1.1.1.6 root 170: static void pic_irq_request(void *opaque, int irq, int level)
1.1 root 171: {
1.1.1.20! root 172: CPUX86State *env = first_cpu;
1.1.1.7 root 173:
1.1.1.15 root 174: DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
1.1.1.7 root 175: if (env->apic_state) {
176: while (env) {
1.1.1.15 root 177: if (apic_accept_pic_intr(env->apic_state)) {
178: apic_deliver_pic_intr(env->apic_state, level);
179: }
1.1.1.7 root 180: env = env->next_cpu;
181: }
182: } else {
183: if (level)
184: cpu_interrupt(env, CPU_INTERRUPT_HARD);
185: else
186: cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
187: }
1.1 root 188: }
189:
190: /* PC cmos mappings */
191:
192: #define REG_EQUIPMENT_BYTE 0x14
193:
1.1.1.18 root 194: static int cmos_get_fd_drive_type(FDriveType fd0)
1.1 root 195: {
196: int val;
197:
198: switch (fd0) {
1.1.1.18 root 199: case FDRIVE_DRV_144:
1.1 root 200: /* 1.44 Mb 3"5 drive */
201: val = 4;
202: break;
1.1.1.18 root 203: case FDRIVE_DRV_288:
1.1 root 204: /* 2.88 Mb 3"5 drive */
205: val = 5;
206: break;
1.1.1.18 root 207: case FDRIVE_DRV_120:
1.1 root 208: /* 1.2 Mb 5"5 drive */
209: val = 2;
210: break;
1.1.1.18 root 211: case FDRIVE_DRV_NONE:
1.1 root 212: default:
213: val = 0;
214: break;
215: }
216: return val;
217: }
218:
1.1.1.15 root 219: static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
220: ISADevice *s)
1.1 root 221: {
222: int cylinders, heads, sectors;
223: bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors);
224: rtc_set_memory(s, type_ofs, 47);
225: rtc_set_memory(s, info_ofs, cylinders);
226: rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
227: rtc_set_memory(s, info_ofs + 2, heads);
228: rtc_set_memory(s, info_ofs + 3, 0xff);
229: rtc_set_memory(s, info_ofs + 4, 0xff);
230: rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
231: rtc_set_memory(s, info_ofs + 6, cylinders);
232: rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
233: rtc_set_memory(s, info_ofs + 8, sectors);
234: }
235:
1.1.1.6 root 236: /* convert boot_device letter to something recognizable by the bios */
237: static int boot_device2nibble(char boot_device)
238: {
239: switch(boot_device) {
240: case 'a':
241: case 'b':
242: return 0x01; /* floppy boot */
243: case 'c':
244: return 0x02; /* hard drive boot */
245: case 'd':
246: return 0x03; /* CD-ROM boot */
247: case 'n':
248: return 0x04; /* Network boot */
249: }
250: return 0;
251: }
252:
1.1.1.15 root 253: static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
1.1.1.7 root 254: {
255: #define PC_MAX_BOOT_DEVICES 3
256: int nbds, bds[3] = { 0, };
257: int i;
258:
259: nbds = strlen(boot_device);
260: if (nbds > PC_MAX_BOOT_DEVICES) {
1.1.1.15 root 261: error_report("Too many boot devices for PC");
1.1.1.7 root 262: return(1);
263: }
264: for (i = 0; i < nbds; i++) {
265: bds[i] = boot_device2nibble(boot_device[i]);
266: if (bds[i] == 0) {
1.1.1.15 root 267: error_report("Invalid boot device for PC: '%c'",
268: boot_device[i]);
1.1.1.7 root 269: return(1);
270: }
271: }
272: rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
1.1.1.15 root 273: rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
1.1.1.7 root 274: return(0);
275: }
276:
1.1.1.15 root 277: static int pc_boot_set(void *opaque, const char *boot_device)
1.1 root 278: {
1.1.1.15 root 279: return set_boot_dev(opaque, boot_device, 0);
280: }
281:
282: typedef struct pc_cmos_init_late_arg {
283: ISADevice *rtc_state;
284: BusState *idebus0, *idebus1;
285: } pc_cmos_init_late_arg;
286:
287: static void pc_cmos_init_late(void *opaque)
288: {
289: pc_cmos_init_late_arg *arg = opaque;
290: ISADevice *s = arg->rtc_state;
1.1 root 291: int val;
1.1.1.15 root 292: BlockDriverState *hd_table[4];
1.1 root 293: int i;
294:
1.1.1.15 root 295: ide_get_bs(hd_table, arg->idebus0);
296: ide_get_bs(hd_table + 2, arg->idebus1);
297:
298: rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
299: if (hd_table[0])
300: cmos_init_hd(0x19, 0x1b, hd_table[0], s);
301: if (hd_table[1])
302: cmos_init_hd(0x1a, 0x24, hd_table[1], s);
303:
304: val = 0;
305: for (i = 0; i < 4; i++) {
306: if (hd_table[i]) {
307: int cylinders, heads, sectors, translation;
308: /* NOTE: bdrv_get_geometry_hint() returns the physical
309: geometry. It is always such that: 1 <= sects <= 63, 1
310: <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
311: geometry can be different if a translation is done. */
312: translation = bdrv_get_translation_hint(hd_table[i]);
313: if (translation == BIOS_ATA_TRANSLATION_AUTO) {
314: bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors);
315: if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
316: /* No translation. */
317: translation = 0;
318: } else {
319: /* LBA translation. */
320: translation = 1;
321: }
322: } else {
323: translation--;
324: }
325: val |= translation << (i * 2);
326: }
327: }
328: rtc_set_memory(s, 0x39, val);
329:
330: qemu_unregister_reset(pc_cmos_init_late, opaque);
331: }
332:
333: void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
334: const char *boot_device,
1.1.1.19 root 335: ISADevice *floppy, BusState *idebus0, BusState *idebus1,
1.1.1.18 root 336: ISADevice *s)
1.1.1.15 root 337: {
1.1.1.18 root 338: int val, nb, nb_heads, max_track, last_sect, i;
1.1.1.19 root 339: FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
1.1.1.20! root 340: FDriveRate rate;
1.1.1.19 root 341: BlockDriverState *fd[MAX_FD];
1.1.1.15 root 342: static pc_cmos_init_late_arg arg;
343:
1.1 root 344: /* various important CMOS locations needed by PC/Bochs bios */
345:
346: /* memory size */
347: val = 640; /* base memory in K */
348: rtc_set_memory(s, 0x15, val);
349: rtc_set_memory(s, 0x16, val >> 8);
350:
351: val = (ram_size / 1024) - 1024;
352: if (val > 65535)
353: val = 65535;
354: rtc_set_memory(s, 0x17, val);
355: rtc_set_memory(s, 0x18, val >> 8);
356: rtc_set_memory(s, 0x30, val);
357: rtc_set_memory(s, 0x31, val >> 8);
358:
1.1.1.7 root 359: if (above_4g_mem_size) {
360: rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
361: rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
362: rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
363: }
364:
1.1 root 365: if (ram_size > (16 * 1024 * 1024))
366: val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
367: else
368: val = 0;
369: if (val > 65535)
370: val = 65535;
371: rtc_set_memory(s, 0x34, val);
372: rtc_set_memory(s, 0x35, val >> 8);
1.1.1.6 root 373:
1.1.1.7 root 374: /* set the number of CPU */
375: rtc_set_memory(s, 0x5f, smp_cpus - 1);
376:
1.1.1.6 root 377: /* set boot devices, and disable floppy signature check if requested */
1.1.1.15 root 378: if (set_boot_dev(s, boot_device, fd_bootchk)) {
1.1.1.6 root 379: exit(1);
1.1 root 380: }
381:
382: /* floppy type */
1.1.1.19 root 383: if (floppy) {
384: fdc_get_bs(fd, floppy);
385: for (i = 0; i < 2; i++) {
1.1.1.20! root 386: if (fd[i]) {
1.1.1.19 root 387: bdrv_get_floppy_geometry_hint(fd[i], &nb_heads, &max_track,
388: &last_sect, FDRIVE_DRV_NONE,
1.1.1.20! root 389: &fd_type[i], &rate);
1.1.1.19 root 390: }
1.1.1.18 root 391: }
392: }
393: val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
394: cmos_get_fd_drive_type(fd_type[1]);
1.1 root 395: rtc_set_memory(s, 0x10, val);
1.1.1.6 root 396:
1.1 root 397: val = 0;
398: nb = 0;
1.1.1.18 root 399: if (fd_type[0] < FDRIVE_DRV_NONE) {
1.1 root 400: nb++;
1.1.1.18 root 401: }
402: if (fd_type[1] < FDRIVE_DRV_NONE) {
1.1 root 403: nb++;
1.1.1.18 root 404: }
1.1 root 405: switch (nb) {
406: case 0:
407: break;
408: case 1:
409: val |= 0x01; /* 1 drive, ready for boot */
410: break;
411: case 2:
412: val |= 0x41; /* 2 drives, ready for boot */
413: break;
414: }
415: val |= 0x02; /* FPU is there */
416: val |= 0x04; /* PS/2 mouse installed */
417: rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
418:
419: /* hard drives */
1.1.1.15 root 420: arg.rtc_state = s;
421: arg.idebus0 = idebus0;
422: arg.idebus1 = idebus1;
423: qemu_register_reset(pc_cmos_init_late, &arg);
1.1.1.2 root 424: }
425:
1.1.1.16 root 426: /* port 92 stuff: could be split off */
427: typedef struct Port92State {
428: ISADevice dev;
1.1.1.19 root 429: MemoryRegion io;
1.1.1.16 root 430: uint8_t outport;
431: qemu_irq *a20_out;
432: } Port92State;
433:
434: static void port92_write(void *opaque, uint32_t addr, uint32_t val)
435: {
436: Port92State *s = opaque;
437:
438: DPRINTF("port92: write 0x%02x\n", val);
439: s->outport = val;
440: qemu_set_irq(*s->a20_out, (val >> 1) & 1);
441: if (val & 1) {
442: qemu_system_reset_request();
443: }
444: }
445:
446: static uint32_t port92_read(void *opaque, uint32_t addr)
447: {
448: Port92State *s = opaque;
449: uint32_t ret;
450:
451: ret = s->outport;
452: DPRINTF("port92: read 0x%02x\n", ret);
453: return ret;
454: }
455:
456: static void port92_init(ISADevice *dev, qemu_irq *a20_out)
457: {
458: Port92State *s = DO_UPCAST(Port92State, dev, dev);
459:
460: s->a20_out = a20_out;
461: }
462:
463: static const VMStateDescription vmstate_port92_isa = {
464: .name = "port92",
465: .version_id = 1,
466: .minimum_version_id = 1,
467: .minimum_version_id_old = 1,
468: .fields = (VMStateField []) {
469: VMSTATE_UINT8(outport, Port92State),
470: VMSTATE_END_OF_LIST()
471: }
472: };
473:
474: static void port92_reset(DeviceState *d)
475: {
476: Port92State *s = container_of(d, Port92State, dev.qdev);
477:
478: s->outport &= ~1;
479: }
480:
1.1.1.19 root 481: static const MemoryRegionPortio port92_portio[] = {
482: { 0, 1, 1, .read = port92_read, .write = port92_write },
483: PORTIO_END_OF_LIST(),
484: };
485:
486: static const MemoryRegionOps port92_ops = {
487: .old_portio = port92_portio
488: };
489:
1.1.1.16 root 490: static int port92_initfn(ISADevice *dev)
491: {
492: Port92State *s = DO_UPCAST(Port92State, dev, dev);
493:
1.1.1.19 root 494: memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
495: isa_register_ioport(dev, &s->io, 0x92);
496:
1.1.1.16 root 497: s->outport = 0;
498: return 0;
499: }
500:
1.1.1.20! root 501: static void port92_class_initfn(ObjectClass *klass, void *data)
! 502: {
! 503: DeviceClass *dc = DEVICE_CLASS(klass);
! 504: ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
! 505: ic->init = port92_initfn;
! 506: dc->no_user = 1;
! 507: dc->reset = port92_reset;
! 508: dc->vmsd = &vmstate_port92_isa;
! 509: }
! 510:
! 511: static TypeInfo port92_info = {
! 512: .name = "port92",
! 513: .parent = TYPE_ISA_DEVICE,
! 514: .instance_size = sizeof(Port92State),
! 515: .class_init = port92_class_initfn,
1.1.1.16 root 516: };
517:
1.1.1.20! root 518: static void port92_register_types(void)
1.1.1.16 root 519: {
1.1.1.20! root 520: type_register_static(&port92_info);
1.1.1.16 root 521: }
1.1.1.20! root 522:
! 523: type_init(port92_register_types)
1.1.1.16 root 524:
1.1.1.15 root 525: static void handle_a20_line_change(void *opaque, int irq, int level)
1.1.1.2 root 526: {
1.1.1.20! root 527: CPUX86State *cpu = opaque;
1.1.1.2 root 528:
1.1.1.15 root 529: /* XXX: send to all CPUs ? */
1.1.1.16 root 530: /* XXX: add logic to handle multiple A20 line sources */
1.1.1.15 root 531: cpu_x86_set_a20(cpu, level);
1.1 root 532: }
533:
534: /***********************************************************/
535: /* Bochs BIOS debug ports */
536:
1.1.1.6 root 537: static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
1.1 root 538: {
539: static const char shutdown_str[8] = "Shutdown";
540: static int shutdown_index = 0;
1.1.1.6 root 541:
1.1 root 542: switch(addr) {
543: /* Bochs BIOS messages */
544: case 0x400:
545: case 0x401:
1.1.1.16 root 546: /* used to be panic, now unused */
547: break;
1.1 root 548: case 0x402:
549: case 0x403:
550: #ifdef DEBUG_BIOS
551: fprintf(stderr, "%c", val);
552: #endif
553: break;
554: case 0x8900:
555: /* same as Bochs power off */
556: if (val == shutdown_str[shutdown_index]) {
557: shutdown_index++;
558: if (shutdown_index == 8) {
559: shutdown_index = 0;
560: qemu_system_shutdown_request();
561: }
562: } else {
563: shutdown_index = 0;
564: }
565: break;
566:
567: /* LGPL'ed VGA BIOS messages */
568: case 0x501:
569: case 0x502:
1.1.1.19 root 570: exit((val << 1) | 1);
1.1 root 571: case 0x500:
572: case 0x503:
573: #ifdef DEBUG_BIOS
574: fprintf(stderr, "%c", val);
575: #endif
576: break;
577: }
578: }
579:
1.1.1.15 root 580: int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
581: {
1.1.1.16 root 582: int index = le32_to_cpu(e820_table.count);
1.1.1.15 root 583: struct e820_entry *entry;
584:
585: if (index >= E820_NR_ENTRIES)
586: return -EBUSY;
1.1.1.16 root 587: entry = &e820_table.entry[index++];
1.1.1.15 root 588:
1.1.1.16 root 589: entry->address = cpu_to_le64(address);
590: entry->length = cpu_to_le64(length);
591: entry->type = cpu_to_le32(type);
1.1.1.15 root 592:
1.1.1.16 root 593: e820_table.count = cpu_to_le32(index);
594: return index;
1.1.1.15 root 595: }
596:
1.1.1.11 root 597: static void *bochs_bios_init(void)
1.1 root 598: {
1.1.1.7 root 599: void *fw_cfg;
1.1.1.11 root 600: uint8_t *smbios_table;
601: size_t smbios_len;
602: uint64_t *numa_fw_cfg;
603: int i, j;
1.1.1.7 root 604:
1.1 root 605: register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
606: register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
607: register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
608: register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
609: register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
610:
1.1.1.19 root 611: register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
1.1 root 612: register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
613: register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
614: register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
615: register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
1.1.1.7 root 616:
617: fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
1.1.1.11 root 618:
1.1.1.7 root 619: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
620: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1.1.1.11 root 621: fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
622: acpi_tables_len);
1.1.1.20! root 623: fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
1.1.1.11 root 624:
625: smbios_table = smbios_get_table(&smbios_len);
626: if (smbios_table)
627: fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
628: smbios_table, smbios_len);
1.1.1.15 root 629: fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
630: sizeof(struct e820_table));
1.1.1.11 root 631:
1.1.1.15 root 632: fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
633: sizeof(struct hpet_fw_config));
1.1.1.11 root 634: /* allocate memory for the NUMA channel: one (64bit) word for the number
635: * of nodes, one word for each VCPU->node and one word for each node to
636: * hold the amount of memory.
637: */
1.1.1.20! root 638: numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8);
1.1.1.11 root 639: numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
1.1.1.20! root 640: for (i = 0; i < max_cpus; i++) {
1.1.1.11 root 641: for (j = 0; j < nb_numa_nodes; j++) {
642: if (node_cpumask[j] & (1 << i)) {
643: numa_fw_cfg[i + 1] = cpu_to_le64(j);
644: break;
645: }
646: }
647: }
648: for (i = 0; i < nb_numa_nodes; i++) {
1.1.1.20! root 649: numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
1.1.1.11 root 650: }
651: fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
1.1.1.20! root 652: (1 + max_cpus + nb_numa_nodes) * 8);
1.1.1.11 root 653:
654: return fw_cfg;
1.1 root 655: }
656:
1.1.1.6 root 657: static long get_file_size(FILE *f)
658: {
659: long where, size;
660:
661: /* XXX: on Unix systems, using fstat() probably makes more sense */
662:
663: where = ftell(f);
664: fseek(f, 0, SEEK_END);
665: size = ftell(f);
666: fseek(f, where, SEEK_SET);
667:
668: return size;
669: }
670:
1.1.1.11 root 671: static void load_linux(void *fw_cfg,
1.1.1.7 root 672: const char *kernel_filename,
1.1.1.6 root 673: const char *initrd_filename,
1.1.1.10 root 674: const char *kernel_cmdline,
1.1.1.12 root 675: target_phys_addr_t max_ram_size)
1.1.1.6 root 676: {
677: uint16_t protocol;
1.1.1.11 root 678: int setup_size, kernel_size, initrd_size = 0, cmdline_size;
1.1.1.6 root 679: uint32_t initrd_max;
1.1.1.12 root 680: uint8_t header[8192], *setup, *kernel, *initrd_data;
1.1.1.11 root 681: target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
1.1.1.12 root 682: FILE *f;
1.1.1.11 root 683: char *vmode;
1.1.1.6 root 684:
685: /* Align to 16 bytes as a paranoia measure */
686: cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
687:
688: /* load the kernel header */
689: f = fopen(kernel_filename, "rb");
690: if (!f || !(kernel_size = get_file_size(f)) ||
1.1.1.11 root 691: fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
692: MIN(ARRAY_SIZE(header), kernel_size)) {
1.1.1.12 root 693: fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
694: kernel_filename, strerror(errno));
1.1.1.6 root 695: exit(1);
696: }
697:
698: /* kernel protocol version */
699: #if 0
700: fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
701: #endif
702: if (ldl_p(header+0x202) == 0x53726448)
703: protocol = lduw_p(header+0x206);
1.1.1.11 root 704: else {
705: /* This looks like a multiboot kernel. If it is, let's stop
706: treating it like a Linux kernel. */
1.1.1.15 root 707: if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
708: kernel_cmdline, kernel_size, header))
1.1.1.12 root 709: return;
1.1.1.6 root 710: protocol = 0;
1.1.1.11 root 711: }
1.1.1.6 root 712:
713: if (protocol < 0x200 || !(header[0x211] & 0x01)) {
714: /* Low kernel */
1.1.1.7 root 715: real_addr = 0x90000;
716: cmdline_addr = 0x9a000 - cmdline_size;
717: prot_addr = 0x10000;
1.1.1.6 root 718: } else if (protocol < 0x202) {
719: /* High but ancient kernel */
1.1.1.7 root 720: real_addr = 0x90000;
721: cmdline_addr = 0x9a000 - cmdline_size;
722: prot_addr = 0x100000;
1.1.1.6 root 723: } else {
724: /* High and recent kernel */
1.1.1.7 root 725: real_addr = 0x10000;
726: cmdline_addr = 0x20000;
727: prot_addr = 0x100000;
1.1.1.6 root 728: }
729:
730: #if 0
731: fprintf(stderr,
1.1.1.7 root 732: "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
733: "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
734: "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
735: real_addr,
736: cmdline_addr,
737: prot_addr);
1.1.1.6 root 738: #endif
739:
740: /* highest address for loading the initrd */
741: if (protocol >= 0x203)
742: initrd_max = ldl_p(header+0x22c);
743: else
744: initrd_max = 0x37ffffff;
745:
1.1.1.10 root 746: if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
747: initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
1.1.1.6 root 748:
1.1.1.12 root 749: fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
750: fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
751: fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
752: (uint8_t*)strdup(kernel_cmdline),
753: strlen(kernel_cmdline)+1);
1.1.1.6 root 754:
755: if (protocol >= 0x202) {
1.1.1.7 root 756: stl_p(header+0x228, cmdline_addr);
1.1.1.6 root 757: } else {
758: stw_p(header+0x20, 0xA33F);
759: stw_p(header+0x22, cmdline_addr-real_addr);
760: }
761:
1.1.1.11 root 762: /* handle vga= parameter */
763: vmode = strstr(kernel_cmdline, "vga=");
764: if (vmode) {
765: unsigned int video_mode;
766: /* skip "vga=" */
767: vmode += 4;
768: if (!strncmp(vmode, "normal", 6)) {
769: video_mode = 0xffff;
770: } else if (!strncmp(vmode, "ext", 3)) {
771: video_mode = 0xfffe;
772: } else if (!strncmp(vmode, "ask", 3)) {
773: video_mode = 0xfffd;
774: } else {
775: video_mode = strtol(vmode, NULL, 0);
776: }
777: stw_p(header+0x1fa, video_mode);
778: }
779:
1.1.1.6 root 780: /* loader type */
1.1.1.20! root 781: /* High nybble = B reserved for QEMU; low nybble is revision number.
1.1.1.6 root 782: If this code is substantially changed, you may want to consider
783: incrementing the revision. */
784: if (protocol >= 0x200)
785: header[0x210] = 0xB0;
786:
787: /* heap */
788: if (protocol >= 0x201) {
789: header[0x211] |= 0x80; /* CAN_USE_HEAP */
790: stw_p(header+0x224, cmdline_addr-real_addr-0x200);
791: }
792:
793: /* load initrd */
794: if (initrd_filename) {
795: if (protocol < 0x200) {
796: fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
797: exit(1);
798: }
799:
1.1.1.12 root 800: initrd_size = get_image_size(initrd_filename);
1.1.1.15 root 801: if (initrd_size < 0) {
802: fprintf(stderr, "qemu: error reading initrd %s\n",
803: initrd_filename);
804: exit(1);
805: }
806:
1.1.1.12 root 807: initrd_addr = (initrd_max-initrd_size) & ~4095;
1.1.1.6 root 808:
1.1.1.19 root 809: initrd_data = g_malloc(initrd_size);
1.1.1.12 root 810: load_image(initrd_filename, initrd_data);
1.1.1.6 root 811:
1.1.1.12 root 812: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
813: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
814: fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
1.1.1.6 root 815:
1.1.1.7 root 816: stl_p(header+0x218, initrd_addr);
1.1.1.6 root 817: stl_p(header+0x21c, initrd_size);
818: }
819:
1.1.1.12 root 820: /* load kernel and setup */
1.1.1.6 root 821: setup_size = header[0x1f1];
822: if (setup_size == 0)
823: setup_size = 4;
824: setup_size = (setup_size+1)*512;
1.1.1.12 root 825: kernel_size -= setup_size;
1.1.1.11 root 826:
1.1.1.19 root 827: setup = g_malloc(setup_size);
828: kernel = g_malloc(kernel_size);
1.1.1.12 root 829: fseek(f, 0, SEEK_SET);
1.1.1.15 root 830: if (fread(setup, 1, setup_size, f) != setup_size) {
831: fprintf(stderr, "fread() failed\n");
832: exit(1);
833: }
834: if (fread(kernel, 1, kernel_size, f) != kernel_size) {
835: fprintf(stderr, "fread() failed\n");
836: exit(1);
837: }
1.1.1.6 root 838: fclose(f);
1.1.1.12 root 839: memcpy(setup, header, MIN(sizeof(header), setup_size));
840:
841: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
842: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
843: fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
1.1.1.6 root 844:
1.1.1.12 root 845: fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
846: fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
847: fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
1.1.1.9 root 848:
1.1.1.16 root 849: option_rom[nb_option_roms].name = "linuxboot.bin";
850: option_rom[nb_option_roms].bootindex = 0;
1.1.1.12 root 851: nb_option_roms++;
1.1.1.6 root 852: }
853:
1.1 root 854: #define NE2000_NB_MAX 6
855:
1.1.1.12 root 856: static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
857: 0x280, 0x380 };
858: static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1.1 root 859:
1.1.1.12 root 860: static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
861: static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
1.1 root 862:
1.1.1.20! root 863: void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
1.1.1.3 root 864: {
865: static int nb_ne2k = 0;
866:
867: if (nb_ne2k == NE2000_NB_MAX)
868: return;
1.1.1.20! root 869: isa_ne2000_init(bus, ne2000_io[nb_ne2k],
1.1.1.12 root 870: ne2000_irq[nb_ne2k], nd);
1.1.1.3 root 871: nb_ne2k++;
872: }
873:
1.1.1.20! root 874: int cpu_is_bsp(CPUX86State *env)
1.1.1.11 root 875: {
1.1.1.15 root 876: /* We hard-wire the BSP to the first CPU. */
877: return env->cpu_index == 0;
878: }
879:
880: DeviceState *cpu_get_current_apic(void)
881: {
882: if (cpu_single_env) {
883: return cpu_single_env->apic_state;
884: } else {
885: return NULL;
886: }
887: }
888:
889: static DeviceState *apic_init(void *env, uint8_t apic_id)
890: {
891: DeviceState *dev;
892: static int apic_mapped;
893:
1.1.1.20! root 894: if (kvm_irqchip_in_kernel()) {
! 895: dev = qdev_create(NULL, "kvm-apic");
! 896: } else if (xen_enabled()) {
! 897: dev = qdev_create(NULL, "xen-apic");
! 898: } else {
! 899: dev = qdev_create(NULL, "apic");
! 900: }
! 901:
1.1.1.15 root 902: qdev_prop_set_uint8(dev, "id", apic_id);
903: qdev_prop_set_ptr(dev, "cpu_env", env);
904: qdev_init_nofail(dev);
905:
906: /* XXX: mapping more APICs at the same memory location */
907: if (apic_mapped == 0) {
908: /* NOTE: the APIC is directly connected to the CPU - it is not
909: on the global memory bus. */
910: /* XXX: what if the base changes? */
1.1.1.20! root 911: sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE);
1.1.1.15 root 912: apic_mapped = 1;
913: }
914:
1.1.1.20! root 915: /* KVM does not support MSI yet. */
! 916: if (!kvm_irqchip_in_kernel()) {
! 917: msi_supported = true;
! 918: }
1.1.1.15 root 919:
1.1.1.20! root 920: if (xen_msi_support()) {
! 921: msi_supported = true;
1.1.1.15 root 922: }
1.1.1.20! root 923:
! 924: return dev;
1.1.1.15 root 925: }
926:
927: void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
928: {
1.1.1.20! root 929: CPUX86State *s = opaque;
1.1.1.15 root 930:
931: if (level) {
932: cpu_interrupt(s, CPU_INTERRUPT_SMI);
933: }
934: }
935:
936: static void pc_cpu_reset(void *opaque)
937: {
1.1.1.20! root 938: CPUX86State *env = opaque;
1.1.1.15 root 939:
1.1.1.20! root 940: cpu_state_reset(env);
1.1.1.15 root 941: env->halted = !cpu_is_bsp(env);
1.1.1.11 root 942: }
943:
1.1.1.20! root 944: static CPUX86State *pc_new_cpu(const char *cpu_model)
1.1.1.11 root 945: {
1.1.1.20! root 946: CPUX86State *env;
1.1.1.11 root 947:
948: env = cpu_init(cpu_model);
949: if (!env) {
950: fprintf(stderr, "Unable to find x86 CPU definition\n");
951: exit(1);
952: }
953: if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
1.1.1.15 root 954: env->apic_state = apic_init(env, env->cpuid_apic_id);
1.1.1.11 root 955: }
1.1.1.15 root 956: qemu_register_reset(pc_cpu_reset, env);
957: pc_cpu_reset(env);
1.1.1.11 root 958: return env;
959: }
960:
1.1.1.15 root 961: void pc_cpus_init(const char *cpu_model)
962: {
963: int i;
964:
965: /* init CPUs */
966: if (cpu_model == NULL) {
967: #ifdef TARGET_X86_64
968: cpu_model = "qemu64";
969: #else
970: cpu_model = "qemu32";
971: #endif
972: }
973:
974: for(i = 0; i < smp_cpus; i++) {
975: pc_new_cpu(cpu_model);
976: }
977: }
978:
1.1.1.19 root 979: void pc_memory_init(MemoryRegion *system_memory,
980: const char *kernel_filename,
1.1.1.15 root 981: const char *kernel_cmdline,
982: const char *initrd_filename,
1.1.1.18 root 983: ram_addr_t below_4g_mem_size,
1.1.1.19 root 984: ram_addr_t above_4g_mem_size,
985: MemoryRegion *rom_memory,
986: MemoryRegion **ram_memory)
1.1 root 987: {
1.1.1.20! root 988: int linux_boot, i;
! 989: MemoryRegion *ram, *option_rom_mr;
1.1.1.19 root 990: MemoryRegion *ram_below_4g, *ram_above_4g;
1.1.1.11 root 991: void *fw_cfg;
1.1 root 992:
1.1.1.15 root 993: linux_boot = (kernel_filename != NULL);
1.1.1.7 root 994:
1.1.1.19 root 995: /* Allocate RAM. We allocate it as a single memory region and use
1.1.1.20! root 996: * aliases to address portions of it, mostly for backwards compatibility
1.1.1.19 root 997: * with older qemus that used qemu_ram_alloc().
998: */
999: ram = g_malloc(sizeof(*ram));
1.1.1.20! root 1000: memory_region_init_ram(ram, "pc.ram",
1.1.1.19 root 1001: below_4g_mem_size + above_4g_mem_size);
1.1.1.20! root 1002: vmstate_register_ram_global(ram);
1.1.1.19 root 1003: *ram_memory = ram;
1004: ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1005: memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
1006: 0, below_4g_mem_size);
1007: memory_region_add_subregion(system_memory, 0, ram_below_4g);
1.1.1.7 root 1008: if (above_4g_mem_size > 0) {
1.1.1.19 root 1009: ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1010: memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
1011: below_4g_mem_size, above_4g_mem_size);
1012: memory_region_add_subregion(system_memory, 0x100000000ULL,
1013: ram_above_4g);
1.1.1.7 root 1014: }
1.1 root 1015:
1.1.1.20! root 1016:
! 1017: /* Initialize PC system firmware */
! 1018: pc_system_firmware_init(rom_memory);
1.1.1.19 root 1019:
1020: option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1.1.1.20! root 1021: memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
! 1022: vmstate_register_ram_global(option_rom_mr);
1.1.1.19 root 1023: memory_region_add_subregion_overlap(rom_memory,
1024: PC_ROM_MIN_VGA,
1025: option_rom_mr,
1026: 1);
1.1.1.5 root 1027:
1.1.1.11 root 1028: fw_cfg = bochs_bios_init();
1.1.1.13 root 1029: rom_set_fw(fw_cfg);
1.1.1.11 root 1030:
1031: if (linux_boot) {
1.1.1.12 root 1032: load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1.1.1.11 root 1033: }
1034:
1035: for (i = 0; i < nb_option_roms; i++) {
1.1.1.16 root 1036: rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1.1.1.11 root 1037: }
1.1.1.15 root 1038: }
1.1 root 1039:
1.1.1.15 root 1040: qemu_irq *pc_allocate_cpu_irq(void)
1041: {
1042: return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1043: }
1.1 root 1044:
1.1.1.20! root 1045: DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1.1.1.15 root 1046: {
1.1.1.20! root 1047: DeviceState *dev = NULL;
! 1048:
1.1 root 1049: if (cirrus_vga_enabled) {
1.1.1.15 root 1050: if (pci_bus) {
1.1.1.20! root 1051: dev = pci_cirrus_vga_init(pci_bus);
1.1 root 1052: } else {
1.1.1.20! root 1053: dev = &isa_create_simple(isa_bus, "isa-cirrus-vga")->qdev;
1.1 root 1054: }
1.1.1.6 root 1055: } else if (vmsvga_enabled) {
1.1.1.18 root 1056: if (pci_bus) {
1.1.1.20! root 1057: dev = pci_vmsvga_init(pci_bus);
1.1.1.18 root 1058: } else {
1.1.1.6 root 1059: fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1.1.1.18 root 1060: }
1.1.1.16 root 1061: #ifdef CONFIG_SPICE
1062: } else if (qxl_enabled) {
1.1.1.20! root 1063: if (pci_bus) {
! 1064: dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev;
! 1065: } else {
1.1.1.16 root 1066: fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
1.1.1.20! root 1067: }
1.1.1.16 root 1068: #endif
1.1.1.7 root 1069: } else if (std_vga_enabled) {
1.1.1.15 root 1070: if (pci_bus) {
1.1.1.20! root 1071: dev = pci_vga_init(pci_bus);
1.1.1.5 root 1072: } else {
1.1.1.20! root 1073: dev = isa_vga_init(isa_bus);
1.1.1.5 root 1074: }
1.1 root 1075: }
1.1.1.20! root 1076:
! 1077: return dev;
1.1.1.15 root 1078: }
1.1 root 1079:
1.1.1.15 root 1080: static void cpu_request_exit(void *opaque, int irq, int level)
1081: {
1.1.1.20! root 1082: CPUX86State *env = cpu_single_env;
1.1.1.7 root 1083:
1.1.1.15 root 1084: if (env && level) {
1085: cpu_exit(env);
1086: }
1087: }
1088:
1.1.1.20! root 1089: void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1.1.1.18 root 1090: ISADevice **rtc_state,
1.1.1.19 root 1091: ISADevice **floppy,
1.1.1.18 root 1092: bool no_vmport)
1.1.1.15 root 1093: {
1094: int i;
1095: DriveInfo *fd[MAX_FD];
1.1.1.20! root 1096: DeviceState *hpet = NULL;
! 1097: int pit_isa_irq = 0;
! 1098: qemu_irq pit_alt_irq = NULL;
1.1.1.15 root 1099: qemu_irq rtc_irq = NULL;
1100: qemu_irq *a20_line;
1.1.1.20! root 1101: ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1.1.1.15 root 1102: qemu_irq *cpu_exit_irq;
1103:
1104: register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1105:
1106: register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1.1 root 1107:
1.1.1.20! root 1108: /*
! 1109: * Check if an HPET shall be created.
! 1110: *
! 1111: * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
! 1112: * when the HPET wants to take over. Thus we have to disable the latter.
! 1113: */
! 1114: if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
! 1115: hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1.1 root 1116:
1.1.1.18 root 1117: if (hpet) {
1.1.1.19 root 1118: for (i = 0; i < GSI_NUM_PINS; i++) {
1119: sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]);
1.1.1.18 root 1120: }
1.1.1.20! root 1121: pit_isa_irq = -1;
! 1122: pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
! 1123: rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1.1.1.15 root 1124: }
1.1 root 1125: }
1.1.1.20! root 1126: *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1.1.1.15 root 1127:
1128: qemu_register_boot_set(pc_boot_set, *rtc_state);
1129:
1.1.1.20! root 1130: if (!xen_enabled()) {
! 1131: if (kvm_irqchip_in_kernel()) {
! 1132: pit = kvm_pit_init(isa_bus, 0x40);
! 1133: } else {
! 1134: pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
! 1135: }
! 1136: if (hpet) {
! 1137: /* connect PIT to output control line of the HPET */
! 1138: qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0));
! 1139: }
! 1140: pcspk_init(isa_bus, pit);
! 1141: }
1.1 root 1142:
1143: for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1144: if (serial_hds[i]) {
1.1.1.20! root 1145: serial_isa_init(isa_bus, i, serial_hds[i]);
1.1 root 1146: }
1147: }
1148:
1149: for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1150: if (parallel_hds[i]) {
1.1.1.20! root 1151: parallel_init(isa_bus, i, parallel_hds[i]);
1.1 root 1152: }
1153: }
1154:
1.1.1.16 root 1155: a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1.1.1.20! root 1156: i8042 = isa_create_simple(isa_bus, "i8042");
1.1.1.16 root 1157: i8042_setup_a20_line(i8042, &a20_line[0]);
1.1.1.18 root 1158: if (!no_vmport) {
1.1.1.20! root 1159: vmport_init(isa_bus);
! 1160: vmmouse = isa_try_create(isa_bus, "vmmouse");
1.1.1.18 root 1161: } else {
1162: vmmouse = NULL;
1163: }
1164: if (vmmouse) {
1165: qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1166: qdev_init_nofail(&vmmouse->qdev);
1167: }
1.1.1.20! root 1168: port92 = isa_create_simple(isa_bus, "port92");
1.1.1.16 root 1169: port92_init(port92, &a20_line[1]);
1.1.1.7 root 1170:
1.1.1.15 root 1171: cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1172: DMA_init(0, cpu_exit_irq);
1.1 root 1173:
1.1.1.6 root 1174: for(i = 0; i < MAX_FD; i++) {
1.1.1.12 root 1175: fd[i] = drive_get(IF_FLOPPY, 0, i);
1.1.1.6 root 1176: }
1.1.1.20! root 1177: *floppy = fdctrl_init_isa(isa_bus, fd);
1.1 root 1178: }
1179:
1.1.1.15 root 1180: void pc_pci_device_init(PCIBus *pci_bus)
1.1.1.7 root 1181: {
1.1.1.15 root 1182: int max_bus;
1183: int bus;
1.1.1.7 root 1184:
1.1.1.15 root 1185: max_bus = drive_get_max_bus(IF_SCSI);
1186: for (bus = 0; bus <= max_bus; bus++) {
1187: pci_create_simple(pci_bus, -1, "lsi53c895a");
1.1.1.13 root 1188: }
1.1.1.11 root 1189: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.