File:  [Qemu by Fabrice Bellard] / qemu / hw / pc.c
Revision 1.1.1.17 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 18:46:35 2018 UTC (2 years, 4 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu0150, qemu0141, HEAD
qemu 0.14.1

    1: /*
    2:  * QEMU PC System Emulator
    3:  *
    4:  * Copyright (c) 2003-2004 Fabrice Bellard
    5:  *
    6:  * Permission is hereby granted, free of charge, to any person obtaining a copy
    7:  * of this software and associated documentation files (the "Software"), to deal
    8:  * in the Software without restriction, including without limitation the rights
    9:  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   10:  * copies of the Software, and to permit persons to whom the Software is
   11:  * furnished to do so, subject to the following conditions:
   12:  *
   13:  * The above copyright notice and this permission notice shall be included in
   14:  * all copies or substantial portions of the Software.
   15:  *
   16:  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   17:  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   18:  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
   19:  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   20:  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   21:  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   22:  * THE SOFTWARE.
   23:  */
   24: #include "hw.h"
   25: #include "pc.h"
   26: #include "apic.h"
   27: #include "fdc.h"
   28: #include "ide.h"
   29: #include "pci.h"
   30: #include "vmware_vga.h"
   31: #include "monitor.h"
   32: #include "fw_cfg.h"
   33: #include "hpet_emul.h"
   34: #include "smbios.h"
   35: #include "loader.h"
   36: #include "elf.h"
   37: #include "multiboot.h"
   38: #include "mc146818rtc.h"
   39: #include "msix.h"
   40: #include "sysbus.h"
   41: #include "sysemu.h"
   42: #include "blockdev.h"
   43: #include "ui/qemu-spice.h"
   44: 
   45: /* output Bochs bios info messages */
   46: //#define DEBUG_BIOS
   47: 
   48: /* debug PC/ISA interrupts */
   49: //#define DEBUG_IRQ
   50: 
   51: #ifdef DEBUG_IRQ
   52: #define DPRINTF(fmt, ...)                                       \
   53:     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
   54: #else
   55: #define DPRINTF(fmt, ...)
   56: #endif
   57: 
   58: #define BIOS_FILENAME "bios.bin"
   59: 
   60: #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
   61: 
   62: /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
   63: #define ACPI_DATA_SIZE       0x10000
   64: #define BIOS_CFG_IOPORT 0x510
   65: #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
   66: #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
   67: #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
   68: #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
   69: #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
   70: 
   71: #define MSI_ADDR_BASE 0xfee00000
   72: 
   73: #define E820_NR_ENTRIES		16
   74: 
   75: struct e820_entry {
   76:     uint64_t address;
   77:     uint64_t length;
   78:     uint32_t type;
   79: } __attribute((__packed__, __aligned__(4)));
   80: 
   81: struct e820_table {
   82:     uint32_t count;
   83:     struct e820_entry entry[E820_NR_ENTRIES];
   84: } __attribute((__packed__, __aligned__(4)));
   85: 
   86: static struct e820_table e820_table;
   87: 
   88: void isa_irq_handler(void *opaque, int n, int level)
   89: {
   90:     IsaIrqState *isa = (IsaIrqState *)opaque;
   91: 
   92:     DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n);
   93:     if (n < 16) {
   94:         qemu_set_irq(isa->i8259[n], level);
   95:     }
   96:     if (isa->ioapic)
   97:         qemu_set_irq(isa->ioapic[n], level);
   98: };
   99: 
  100: static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
  101: {
  102: }
  103: 
  104: /* MSDOS compatibility mode FPU exception support */
  105: static qemu_irq ferr_irq;
  106: 
  107: void pc_register_ferr_irq(qemu_irq irq)
  108: {
  109:     ferr_irq = irq;
  110: }
  111: 
  112: /* XXX: add IGNNE support */
  113: void cpu_set_ferr(CPUX86State *s)
  114: {
  115:     qemu_irq_raise(ferr_irq);
  116: }
  117: 
  118: static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
  119: {
  120:     qemu_irq_lower(ferr_irq);
  121: }
  122: 
  123: /* TSC handling */
  124: uint64_t cpu_get_tsc(CPUX86State *env)
  125: {
  126:     return cpu_get_ticks();
  127: }
  128: 
  129: /* SMM support */
  130: 
  131: static cpu_set_smm_t smm_set;
  132: static void *smm_arg;
  133: 
  134: void cpu_smm_register(cpu_set_smm_t callback, void *arg)
  135: {
  136:     assert(smm_set == NULL);
  137:     assert(smm_arg == NULL);
  138:     smm_set = callback;
  139:     smm_arg = arg;
  140: }
  141: 
  142: void cpu_smm_update(CPUState *env)
  143: {
  144:     if (smm_set && smm_arg && env == first_cpu)
  145:         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
  146: }
  147: 
  148: 
  149: /* IRQ handling */
  150: int cpu_get_pic_interrupt(CPUState *env)
  151: {
  152:     int intno;
  153: 
  154:     intno = apic_get_interrupt(env->apic_state);
  155:     if (intno >= 0) {
  156:         /* set irq request if a PIC irq is still pending */
  157:         /* XXX: improve that */
  158:         pic_update_irq(isa_pic);
  159:         return intno;
  160:     }
  161:     /* read the irq from the PIC */
  162:     if (!apic_accept_pic_intr(env->apic_state)) {
  163:         return -1;
  164:     }
  165: 
  166:     intno = pic_read_irq(isa_pic);
  167:     return intno;
  168: }
  169: 
  170: static void pic_irq_request(void *opaque, int irq, int level)
  171: {
  172:     CPUState *env = first_cpu;
  173: 
  174:     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
  175:     if (env->apic_state) {
  176:         while (env) {
  177:             if (apic_accept_pic_intr(env->apic_state)) {
  178:                 apic_deliver_pic_intr(env->apic_state, level);
  179:             }
  180:             env = env->next_cpu;
  181:         }
  182:     } else {
  183:         if (level)
  184:             cpu_interrupt(env, CPU_INTERRUPT_HARD);
  185:         else
  186:             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  187:     }
  188: }
  189: 
  190: /* PC cmos mappings */
  191: 
  192: #define REG_EQUIPMENT_BYTE          0x14
  193: 
  194: static int cmos_get_fd_drive_type(int fd0)
  195: {
  196:     int val;
  197: 
  198:     switch (fd0) {
  199:     case 0:
  200:         /* 1.44 Mb 3"5 drive */
  201:         val = 4;
  202:         break;
  203:     case 1:
  204:         /* 2.88 Mb 3"5 drive */
  205:         val = 5;
  206:         break;
  207:     case 2:
  208:         /* 1.2 Mb 5"5 drive */
  209:         val = 2;
  210:         break;
  211:     default:
  212:         val = 0;
  213:         break;
  214:     }
  215:     return val;
  216: }
  217: 
  218: static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
  219:                          ISADevice *s)
  220: {
  221:     int cylinders, heads, sectors;
  222:     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
  223:     rtc_set_memory(s, type_ofs, 47);
  224:     rtc_set_memory(s, info_ofs, cylinders);
  225:     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
  226:     rtc_set_memory(s, info_ofs + 2, heads);
  227:     rtc_set_memory(s, info_ofs + 3, 0xff);
  228:     rtc_set_memory(s, info_ofs + 4, 0xff);
  229:     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
  230:     rtc_set_memory(s, info_ofs + 6, cylinders);
  231:     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
  232:     rtc_set_memory(s, info_ofs + 8, sectors);
  233: }
  234: 
  235: /* convert boot_device letter to something recognizable by the bios */
  236: static int boot_device2nibble(char boot_device)
  237: {
  238:     switch(boot_device) {
  239:     case 'a':
  240:     case 'b':
  241:         return 0x01; /* floppy boot */
  242:     case 'c':
  243:         return 0x02; /* hard drive boot */
  244:     case 'd':
  245:         return 0x03; /* CD-ROM boot */
  246:     case 'n':
  247:         return 0x04; /* Network boot */
  248:     }
  249:     return 0;
  250: }
  251: 
  252: static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
  253: {
  254: #define PC_MAX_BOOT_DEVICES 3
  255:     int nbds, bds[3] = { 0, };
  256:     int i;
  257: 
  258:     nbds = strlen(boot_device);
  259:     if (nbds > PC_MAX_BOOT_DEVICES) {
  260:         error_report("Too many boot devices for PC");
  261:         return(1);
  262:     }
  263:     for (i = 0; i < nbds; i++) {
  264:         bds[i] = boot_device2nibble(boot_device[i]);
  265:         if (bds[i] == 0) {
  266:             error_report("Invalid boot device for PC: '%c'",
  267:                          boot_device[i]);
  268:             return(1);
  269:         }
  270:     }
  271:     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
  272:     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
  273:     return(0);
  274: }
  275: 
  276: static int pc_boot_set(void *opaque, const char *boot_device)
  277: {
  278:     return set_boot_dev(opaque, boot_device, 0);
  279: }
  280: 
  281: typedef struct pc_cmos_init_late_arg {
  282:     ISADevice *rtc_state;
  283:     BusState *idebus0, *idebus1;
  284: } pc_cmos_init_late_arg;
  285: 
  286: static void pc_cmos_init_late(void *opaque)
  287: {
  288:     pc_cmos_init_late_arg *arg = opaque;
  289:     ISADevice *s = arg->rtc_state;
  290:     int val;
  291:     BlockDriverState *hd_table[4];
  292:     int i;
  293: 
  294:     ide_get_bs(hd_table, arg->idebus0);
  295:     ide_get_bs(hd_table + 2, arg->idebus1);
  296: 
  297:     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
  298:     if (hd_table[0])
  299:         cmos_init_hd(0x19, 0x1b, hd_table[0], s);
  300:     if (hd_table[1])
  301:         cmos_init_hd(0x1a, 0x24, hd_table[1], s);
  302: 
  303:     val = 0;
  304:     for (i = 0; i < 4; i++) {
  305:         if (hd_table[i]) {
  306:             int cylinders, heads, sectors, translation;
  307:             /* NOTE: bdrv_get_geometry_hint() returns the physical
  308:                 geometry.  It is always such that: 1 <= sects <= 63, 1
  309:                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
  310:                 geometry can be different if a translation is done. */
  311:             translation = bdrv_get_translation_hint(hd_table[i]);
  312:             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
  313:                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
  314:                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
  315:                     /* No translation. */
  316:                     translation = 0;
  317:                 } else {
  318:                     /* LBA translation. */
  319:                     translation = 1;
  320:                 }
  321:             } else {
  322:                 translation--;
  323:             }
  324:             val |= translation << (i * 2);
  325:         }
  326:     }
  327:     rtc_set_memory(s, 0x39, val);
  328: 
  329:     qemu_unregister_reset(pc_cmos_init_late, opaque);
  330: }
  331: 
  332: void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
  333:                   const char *boot_device,
  334:                   BusState *idebus0, BusState *idebus1,
  335:                   FDCtrl *floppy_controller, ISADevice *s)
  336: {
  337:     int val;
  338:     int fd0, fd1, nb;
  339:     static pc_cmos_init_late_arg arg;
  340: 
  341:     /* various important CMOS locations needed by PC/Bochs bios */
  342: 
  343:     /* memory size */
  344:     val = 640; /* base memory in K */
  345:     rtc_set_memory(s, 0x15, val);
  346:     rtc_set_memory(s, 0x16, val >> 8);
  347: 
  348:     val = (ram_size / 1024) - 1024;
  349:     if (val > 65535)
  350:         val = 65535;
  351:     rtc_set_memory(s, 0x17, val);
  352:     rtc_set_memory(s, 0x18, val >> 8);
  353:     rtc_set_memory(s, 0x30, val);
  354:     rtc_set_memory(s, 0x31, val >> 8);
  355: 
  356:     if (above_4g_mem_size) {
  357:         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
  358:         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
  359:         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
  360:     }
  361: 
  362:     if (ram_size > (16 * 1024 * 1024))
  363:         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
  364:     else
  365:         val = 0;
  366:     if (val > 65535)
  367:         val = 65535;
  368:     rtc_set_memory(s, 0x34, val);
  369:     rtc_set_memory(s, 0x35, val >> 8);
  370: 
  371:     /* set the number of CPU */
  372:     rtc_set_memory(s, 0x5f, smp_cpus - 1);
  373: 
  374:     /* set boot devices, and disable floppy signature check if requested */
  375:     if (set_boot_dev(s, boot_device, fd_bootchk)) {
  376:         exit(1);
  377:     }
  378: 
  379:     /* floppy type */
  380: 
  381:     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
  382:     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
  383: 
  384:     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
  385:     rtc_set_memory(s, 0x10, val);
  386: 
  387:     val = 0;
  388:     nb = 0;
  389:     if (fd0 < 3)
  390:         nb++;
  391:     if (fd1 < 3)
  392:         nb++;
  393:     switch (nb) {
  394:     case 0:
  395:         break;
  396:     case 1:
  397:         val |= 0x01; /* 1 drive, ready for boot */
  398:         break;
  399:     case 2:
  400:         val |= 0x41; /* 2 drives, ready for boot */
  401:         break;
  402:     }
  403:     val |= 0x02; /* FPU is there */
  404:     val |= 0x04; /* PS/2 mouse installed */
  405:     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
  406: 
  407:     /* hard drives */
  408:     arg.rtc_state = s;
  409:     arg.idebus0 = idebus0;
  410:     arg.idebus1 = idebus1;
  411:     qemu_register_reset(pc_cmos_init_late, &arg);
  412: }
  413: 
  414: /* port 92 stuff: could be split off */
  415: typedef struct Port92State {
  416:     ISADevice dev;
  417:     uint8_t outport;
  418:     qemu_irq *a20_out;
  419: } Port92State;
  420: 
  421: static void port92_write(void *opaque, uint32_t addr, uint32_t val)
  422: {
  423:     Port92State *s = opaque;
  424: 
  425:     DPRINTF("port92: write 0x%02x\n", val);
  426:     s->outport = val;
  427:     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
  428:     if (val & 1) {
  429:         qemu_system_reset_request();
  430:     }
  431: }
  432: 
  433: static uint32_t port92_read(void *opaque, uint32_t addr)
  434: {
  435:     Port92State *s = opaque;
  436:     uint32_t ret;
  437: 
  438:     ret = s->outport;
  439:     DPRINTF("port92: read 0x%02x\n", ret);
  440:     return ret;
  441: }
  442: 
  443: static void port92_init(ISADevice *dev, qemu_irq *a20_out)
  444: {
  445:     Port92State *s = DO_UPCAST(Port92State, dev, dev);
  446: 
  447:     s->a20_out = a20_out;
  448: }
  449: 
  450: static const VMStateDescription vmstate_port92_isa = {
  451:     .name = "port92",
  452:     .version_id = 1,
  453:     .minimum_version_id = 1,
  454:     .minimum_version_id_old = 1,
  455:     .fields      = (VMStateField []) {
  456:         VMSTATE_UINT8(outport, Port92State),
  457:         VMSTATE_END_OF_LIST()
  458:     }
  459: };
  460: 
  461: static void port92_reset(DeviceState *d)
  462: {
  463:     Port92State *s = container_of(d, Port92State, dev.qdev);
  464: 
  465:     s->outport &= ~1;
  466: }
  467: 
  468: static int port92_initfn(ISADevice *dev)
  469: {
  470:     Port92State *s = DO_UPCAST(Port92State, dev, dev);
  471: 
  472:     register_ioport_read(0x92, 1, 1, port92_read, s);
  473:     register_ioport_write(0x92, 1, 1, port92_write, s);
  474:     isa_init_ioport(dev, 0x92);
  475:     s->outport = 0;
  476:     return 0;
  477: }
  478: 
  479: static ISADeviceInfo port92_info = {
  480:     .qdev.name     = "port92",
  481:     .qdev.size     = sizeof(Port92State),
  482:     .qdev.vmsd     = &vmstate_port92_isa,
  483:     .qdev.no_user  = 1,
  484:     .qdev.reset    = port92_reset,
  485:     .init          = port92_initfn,
  486: };
  487: 
  488: static void port92_register(void)
  489: {
  490:     isa_qdev_register(&port92_info);
  491: }
  492: device_init(port92_register)
  493: 
  494: static void handle_a20_line_change(void *opaque, int irq, int level)
  495: {
  496:     CPUState *cpu = opaque;
  497: 
  498:     /* XXX: send to all CPUs ? */
  499:     /* XXX: add logic to handle multiple A20 line sources */
  500:     cpu_x86_set_a20(cpu, level);
  501: }
  502: 
  503: /***********************************************************/
  504: /* Bochs BIOS debug ports */
  505: 
  506: static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
  507: {
  508:     static const char shutdown_str[8] = "Shutdown";
  509:     static int shutdown_index = 0;
  510: 
  511:     switch(addr) {
  512:         /* Bochs BIOS messages */
  513:     case 0x400:
  514:     case 0x401:
  515:         /* used to be panic, now unused */
  516:         break;
  517:     case 0x402:
  518:     case 0x403:
  519: #ifdef DEBUG_BIOS
  520:         fprintf(stderr, "%c", val);
  521: #endif
  522:         break;
  523:     case 0x8900:
  524:         /* same as Bochs power off */
  525:         if (val == shutdown_str[shutdown_index]) {
  526:             shutdown_index++;
  527:             if (shutdown_index == 8) {
  528:                 shutdown_index = 0;
  529:                 qemu_system_shutdown_request();
  530:             }
  531:         } else {
  532:             shutdown_index = 0;
  533:         }
  534:         break;
  535: 
  536:         /* LGPL'ed VGA BIOS messages */
  537:     case 0x501:
  538:     case 0x502:
  539:         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
  540:         exit(1);
  541:     case 0x500:
  542:     case 0x503:
  543: #ifdef DEBUG_BIOS
  544:         fprintf(stderr, "%c", val);
  545: #endif
  546:         break;
  547:     }
  548: }
  549: 
  550: int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
  551: {
  552:     int index = le32_to_cpu(e820_table.count);
  553:     struct e820_entry *entry;
  554: 
  555:     if (index >= E820_NR_ENTRIES)
  556:         return -EBUSY;
  557:     entry = &e820_table.entry[index++];
  558: 
  559:     entry->address = cpu_to_le64(address);
  560:     entry->length = cpu_to_le64(length);
  561:     entry->type = cpu_to_le32(type);
  562: 
  563:     e820_table.count = cpu_to_le32(index);
  564:     return index;
  565: }
  566: 
  567: static void *bochs_bios_init(void)
  568: {
  569:     void *fw_cfg;
  570:     uint8_t *smbios_table;
  571:     size_t smbios_len;
  572:     uint64_t *numa_fw_cfg;
  573:     int i, j;
  574: 
  575:     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
  576:     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
  577:     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
  578:     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
  579:     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
  580: 
  581:     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
  582:     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
  583:     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
  584:     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
  585: 
  586:     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
  587: 
  588:     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
  589:     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
  590:     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
  591:                      acpi_tables_len);
  592:     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
  593: 
  594:     smbios_table = smbios_get_table(&smbios_len);
  595:     if (smbios_table)
  596:         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
  597:                          smbios_table, smbios_len);
  598:     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
  599:                      sizeof(struct e820_table));
  600: 
  601:     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
  602:                      sizeof(struct hpet_fw_config));
  603:     /* allocate memory for the NUMA channel: one (64bit) word for the number
  604:      * of nodes, one word for each VCPU->node and one word for each node to
  605:      * hold the amount of memory.
  606:      */
  607:     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
  608:     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
  609:     for (i = 0; i < smp_cpus; i++) {
  610:         for (j = 0; j < nb_numa_nodes; j++) {
  611:             if (node_cpumask[j] & (1 << i)) {
  612:                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
  613:                 break;
  614:             }
  615:         }
  616:     }
  617:     for (i = 0; i < nb_numa_nodes; i++) {
  618:         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
  619:     }
  620:     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
  621:                      (1 + smp_cpus + nb_numa_nodes) * 8);
  622: 
  623:     return fw_cfg;
  624: }
  625: 
  626: static long get_file_size(FILE *f)
  627: {
  628:     long where, size;
  629: 
  630:     /* XXX: on Unix systems, using fstat() probably makes more sense */
  631: 
  632:     where = ftell(f);
  633:     fseek(f, 0, SEEK_END);
  634:     size = ftell(f);
  635:     fseek(f, where, SEEK_SET);
  636: 
  637:     return size;
  638: }
  639: 
  640: static void load_linux(void *fw_cfg,
  641:                        const char *kernel_filename,
  642: 		       const char *initrd_filename,
  643: 		       const char *kernel_cmdline,
  644:                        target_phys_addr_t max_ram_size)
  645: {
  646:     uint16_t protocol;
  647:     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
  648:     uint32_t initrd_max;
  649:     uint8_t header[8192], *setup, *kernel, *initrd_data;
  650:     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
  651:     FILE *f;
  652:     char *vmode;
  653: 
  654:     /* Align to 16 bytes as a paranoia measure */
  655:     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
  656: 
  657:     /* load the kernel header */
  658:     f = fopen(kernel_filename, "rb");
  659:     if (!f || !(kernel_size = get_file_size(f)) ||
  660: 	fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
  661: 	MIN(ARRAY_SIZE(header), kernel_size)) {
  662: 	fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
  663: 		kernel_filename, strerror(errno));
  664: 	exit(1);
  665:     }
  666: 
  667:     /* kernel protocol version */
  668: #if 0
  669:     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
  670: #endif
  671:     if (ldl_p(header+0x202) == 0x53726448)
  672: 	protocol = lduw_p(header+0x206);
  673:     else {
  674: 	/* This looks like a multiboot kernel. If it is, let's stop
  675: 	   treating it like a Linux kernel. */
  676:         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
  677:                            kernel_cmdline, kernel_size, header))
  678:             return;
  679: 	protocol = 0;
  680:     }
  681: 
  682:     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
  683: 	/* Low kernel */
  684: 	real_addr    = 0x90000;
  685: 	cmdline_addr = 0x9a000 - cmdline_size;
  686: 	prot_addr    = 0x10000;
  687:     } else if (protocol < 0x202) {
  688: 	/* High but ancient kernel */
  689: 	real_addr    = 0x90000;
  690: 	cmdline_addr = 0x9a000 - cmdline_size;
  691: 	prot_addr    = 0x100000;
  692:     } else {
  693: 	/* High and recent kernel */
  694: 	real_addr    = 0x10000;
  695: 	cmdline_addr = 0x20000;
  696: 	prot_addr    = 0x100000;
  697:     }
  698: 
  699: #if 0
  700:     fprintf(stderr,
  701: 	    "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
  702: 	    "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
  703: 	    "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
  704: 	    real_addr,
  705: 	    cmdline_addr,
  706: 	    prot_addr);
  707: #endif
  708: 
  709:     /* highest address for loading the initrd */
  710:     if (protocol >= 0x203)
  711: 	initrd_max = ldl_p(header+0x22c);
  712:     else
  713: 	initrd_max = 0x37ffffff;
  714: 
  715:     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
  716:     	initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
  717: 
  718:     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
  719:     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
  720:     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
  721:                      (uint8_t*)strdup(kernel_cmdline),
  722:                      strlen(kernel_cmdline)+1);
  723: 
  724:     if (protocol >= 0x202) {
  725: 	stl_p(header+0x228, cmdline_addr);
  726:     } else {
  727: 	stw_p(header+0x20, 0xA33F);
  728: 	stw_p(header+0x22, cmdline_addr-real_addr);
  729:     }
  730: 
  731:     /* handle vga= parameter */
  732:     vmode = strstr(kernel_cmdline, "vga=");
  733:     if (vmode) {
  734:         unsigned int video_mode;
  735:         /* skip "vga=" */
  736:         vmode += 4;
  737:         if (!strncmp(vmode, "normal", 6)) {
  738:             video_mode = 0xffff;
  739:         } else if (!strncmp(vmode, "ext", 3)) {
  740:             video_mode = 0xfffe;
  741:         } else if (!strncmp(vmode, "ask", 3)) {
  742:             video_mode = 0xfffd;
  743:         } else {
  744:             video_mode = strtol(vmode, NULL, 0);
  745:         }
  746:         stw_p(header+0x1fa, video_mode);
  747:     }
  748: 
  749:     /* loader type */
  750:     /* High nybble = B reserved for Qemu; low nybble is revision number.
  751:        If this code is substantially changed, you may want to consider
  752:        incrementing the revision. */
  753:     if (protocol >= 0x200)
  754: 	header[0x210] = 0xB0;
  755: 
  756:     /* heap */
  757:     if (protocol >= 0x201) {
  758: 	header[0x211] |= 0x80;	/* CAN_USE_HEAP */
  759: 	stw_p(header+0x224, cmdline_addr-real_addr-0x200);
  760:     }
  761: 
  762:     /* load initrd */
  763:     if (initrd_filename) {
  764: 	if (protocol < 0x200) {
  765: 	    fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
  766: 	    exit(1);
  767: 	}
  768: 
  769: 	initrd_size = get_image_size(initrd_filename);
  770:         if (initrd_size < 0) {
  771:             fprintf(stderr, "qemu: error reading initrd %s\n",
  772:                     initrd_filename);
  773:             exit(1);
  774:         }
  775: 
  776:         initrd_addr = (initrd_max-initrd_size) & ~4095;
  777: 
  778:         initrd_data = qemu_malloc(initrd_size);
  779:         load_image(initrd_filename, initrd_data);
  780: 
  781:         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
  782:         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
  783:         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
  784: 
  785: 	stl_p(header+0x218, initrd_addr);
  786: 	stl_p(header+0x21c, initrd_size);
  787:     }
  788: 
  789:     /* load kernel and setup */
  790:     setup_size = header[0x1f1];
  791:     if (setup_size == 0)
  792: 	setup_size = 4;
  793:     setup_size = (setup_size+1)*512;
  794:     kernel_size -= setup_size;
  795: 
  796:     setup  = qemu_malloc(setup_size);
  797:     kernel = qemu_malloc(kernel_size);
  798:     fseek(f, 0, SEEK_SET);
  799:     if (fread(setup, 1, setup_size, f) != setup_size) {
  800:         fprintf(stderr, "fread() failed\n");
  801:         exit(1);
  802:     }
  803:     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
  804:         fprintf(stderr, "fread() failed\n");
  805:         exit(1);
  806:     }
  807:     fclose(f);
  808:     memcpy(setup, header, MIN(sizeof(header), setup_size));
  809: 
  810:     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
  811:     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
  812:     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
  813: 
  814:     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
  815:     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
  816:     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
  817: 
  818:     option_rom[nb_option_roms].name = "linuxboot.bin";
  819:     option_rom[nb_option_roms].bootindex = 0;
  820:     nb_option_roms++;
  821: }
  822: 
  823: #define NE2000_NB_MAX 6
  824: 
  825: static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
  826:                                               0x280, 0x380 };
  827: static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  828: 
  829: static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
  830: static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
  831: 
  832: void pc_init_ne2k_isa(NICInfo *nd)
  833: {
  834:     static int nb_ne2k = 0;
  835: 
  836:     if (nb_ne2k == NE2000_NB_MAX)
  837:         return;
  838:     isa_ne2000_init(ne2000_io[nb_ne2k],
  839:                     ne2000_irq[nb_ne2k], nd);
  840:     nb_ne2k++;
  841: }
  842: 
  843: int cpu_is_bsp(CPUState *env)
  844: {
  845:     /* We hard-wire the BSP to the first CPU. */
  846:     return env->cpu_index == 0;
  847: }
  848: 
  849: DeviceState *cpu_get_current_apic(void)
  850: {
  851:     if (cpu_single_env) {
  852:         return cpu_single_env->apic_state;
  853:     } else {
  854:         return NULL;
  855:     }
  856: }
  857: 
  858: static DeviceState *apic_init(void *env, uint8_t apic_id)
  859: {
  860:     DeviceState *dev;
  861:     SysBusDevice *d;
  862:     static int apic_mapped;
  863: 
  864:     dev = qdev_create(NULL, "apic");
  865:     qdev_prop_set_uint8(dev, "id", apic_id);
  866:     qdev_prop_set_ptr(dev, "cpu_env", env);
  867:     qdev_init_nofail(dev);
  868:     d = sysbus_from_qdev(dev);
  869: 
  870:     /* XXX: mapping more APICs at the same memory location */
  871:     if (apic_mapped == 0) {
  872:         /* NOTE: the APIC is directly connected to the CPU - it is not
  873:            on the global memory bus. */
  874:         /* XXX: what if the base changes? */
  875:         sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
  876:         apic_mapped = 1;
  877:     }
  878: 
  879:     msix_supported = 1;
  880: 
  881:     return dev;
  882: }
  883: 
  884: /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
  885:    BIOS will read it and start S3 resume at POST Entry */
  886: void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
  887: {
  888:     ISADevice *s = opaque;
  889: 
  890:     if (level) {
  891:         rtc_set_memory(s, 0xF, 0xFE);
  892:     }
  893: }
  894: 
  895: void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
  896: {
  897:     CPUState *s = opaque;
  898: 
  899:     if (level) {
  900:         cpu_interrupt(s, CPU_INTERRUPT_SMI);
  901:     }
  902: }
  903: 
  904: static void pc_cpu_reset(void *opaque)
  905: {
  906:     CPUState *env = opaque;
  907: 
  908:     cpu_reset(env);
  909:     env->halted = !cpu_is_bsp(env);
  910: }
  911: 
  912: static CPUState *pc_new_cpu(const char *cpu_model)
  913: {
  914:     CPUState *env;
  915: 
  916:     env = cpu_init(cpu_model);
  917:     if (!env) {
  918:         fprintf(stderr, "Unable to find x86 CPU definition\n");
  919:         exit(1);
  920:     }
  921:     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
  922:         env->cpuid_apic_id = env->cpu_index;
  923:         env->apic_state = apic_init(env, env->cpuid_apic_id);
  924:     }
  925:     qemu_register_reset(pc_cpu_reset, env);
  926:     pc_cpu_reset(env);
  927:     return env;
  928: }
  929: 
  930: void pc_cpus_init(const char *cpu_model)
  931: {
  932:     int i;
  933: 
  934:     /* init CPUs */
  935:     if (cpu_model == NULL) {
  936: #ifdef TARGET_X86_64
  937:         cpu_model = "qemu64";
  938: #else
  939:         cpu_model = "qemu32";
  940: #endif
  941:     }
  942: 
  943:     for(i = 0; i < smp_cpus; i++) {
  944:         pc_new_cpu(cpu_model);
  945:     }
  946: }
  947: 
  948: void pc_memory_init(ram_addr_t ram_size,
  949:                     const char *kernel_filename,
  950:                     const char *kernel_cmdline,
  951:                     const char *initrd_filename,
  952:                     ram_addr_t *below_4g_mem_size_p,
  953:                     ram_addr_t *above_4g_mem_size_p)
  954: {
  955:     char *filename;
  956:     int ret, linux_boot, i;
  957:     ram_addr_t ram_addr, bios_offset, option_rom_offset;
  958:     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
  959:     int bios_size, isa_bios_size;
  960:     void *fw_cfg;
  961: 
  962:     if (ram_size >= 0xe0000000 ) {
  963:         above_4g_mem_size = ram_size - 0xe0000000;
  964:         below_4g_mem_size = 0xe0000000;
  965:     } else {
  966:         below_4g_mem_size = ram_size;
  967:     }
  968:     *above_4g_mem_size_p = above_4g_mem_size;
  969:     *below_4g_mem_size_p = below_4g_mem_size;
  970: 
  971: #if TARGET_PHYS_ADDR_BITS == 32
  972:     if (above_4g_mem_size > 0) {
  973:         hw_error("To much RAM for 32-bit physical address");
  974:     }
  975: #endif
  976:     linux_boot = (kernel_filename != NULL);
  977: 
  978:     /* allocate RAM */
  979:     ram_addr = qemu_ram_alloc(NULL, "pc.ram",
  980:                               below_4g_mem_size + above_4g_mem_size);
  981:     cpu_register_physical_memory(0, 0xa0000, ram_addr);
  982:     cpu_register_physical_memory(0x100000,
  983:                  below_4g_mem_size - 0x100000,
  984:                  ram_addr + 0x100000);
  985: #if TARGET_PHYS_ADDR_BITS > 32
  986:     if (above_4g_mem_size > 0) {
  987:         cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size,
  988:                                      ram_addr + below_4g_mem_size);
  989:     }
  990: #endif
  991: 
  992:     /* BIOS load */
  993:     if (bios_name == NULL)
  994:         bios_name = BIOS_FILENAME;
  995:     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
  996:     if (filename) {
  997:         bios_size = get_image_size(filename);
  998:     } else {
  999:         bios_size = -1;
 1000:     }
 1001:     if (bios_size <= 0 ||
 1002:         (bios_size % 65536) != 0) {
 1003:         goto bios_error;
 1004:     }
 1005:     bios_offset = qemu_ram_alloc(NULL, "pc.bios", bios_size);
 1006:     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
 1007:     if (ret != 0) {
 1008:     bios_error:
 1009:         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 1010:         exit(1);
 1011:     }
 1012:     if (filename) {
 1013:         qemu_free(filename);
 1014:     }
 1015:     /* map the last 128KB of the BIOS in ISA space */
 1016:     isa_bios_size = bios_size;
 1017:     if (isa_bios_size > (128 * 1024))
 1018:         isa_bios_size = 128 * 1024;
 1019:     cpu_register_physical_memory(0x100000 - isa_bios_size,
 1020:                                  isa_bios_size,
 1021:                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 1022: 
 1023:     option_rom_offset = qemu_ram_alloc(NULL, "pc.rom", PC_ROM_SIZE);
 1024:     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 1025: 
 1026:     /* map all the bios at the top of memory */
 1027:     cpu_register_physical_memory((uint32_t)(-bios_size),
 1028:                                  bios_size, bios_offset | IO_MEM_ROM);
 1029: 
 1030:     fw_cfg = bochs_bios_init();
 1031:     rom_set_fw(fw_cfg);
 1032: 
 1033:     if (linux_boot) {
 1034:         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 1035:     }
 1036: 
 1037:     for (i = 0; i < nb_option_roms; i++) {
 1038:         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
 1039:     }
 1040: }
 1041: 
 1042: qemu_irq *pc_allocate_cpu_irq(void)
 1043: {
 1044:     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 1045: }
 1046: 
 1047: void pc_vga_init(PCIBus *pci_bus)
 1048: {
 1049:     if (cirrus_vga_enabled) {
 1050:         if (pci_bus) {
 1051:             pci_cirrus_vga_init(pci_bus);
 1052:         } else {
 1053:             isa_cirrus_vga_init();
 1054:         }
 1055:     } else if (vmsvga_enabled) {
 1056:         if (pci_bus)
 1057:             pci_vmsvga_init(pci_bus);
 1058:         else
 1059:             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 1060: #ifdef CONFIG_SPICE
 1061:     } else if (qxl_enabled) {
 1062:         if (pci_bus)
 1063:             pci_create_simple(pci_bus, -1, "qxl-vga");
 1064:         else
 1065:             fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
 1066: #endif
 1067:     } else if (std_vga_enabled) {
 1068:         if (pci_bus) {
 1069:             pci_vga_init(pci_bus);
 1070:         } else {
 1071:             isa_vga_init();
 1072:         }
 1073:     }
 1074: }
 1075: 
 1076: static void cpu_request_exit(void *opaque, int irq, int level)
 1077: {
 1078:     CPUState *env = cpu_single_env;
 1079: 
 1080:     if (env && level) {
 1081:         cpu_exit(env);
 1082:     }
 1083: }
 1084: 
 1085: void pc_basic_device_init(qemu_irq *isa_irq,
 1086:                           FDCtrl **floppy_controller,
 1087:                           ISADevice **rtc_state)
 1088: {
 1089:     int i;
 1090:     DriveInfo *fd[MAX_FD];
 1091:     PITState *pit;
 1092:     qemu_irq rtc_irq = NULL;
 1093:     qemu_irq *a20_line;
 1094:     ISADevice *i8042, *port92;
 1095:     qemu_irq *cpu_exit_irq;
 1096: 
 1097:     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
 1098: 
 1099:     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
 1100: 
 1101:     if (!no_hpet) {
 1102:         DeviceState *hpet = sysbus_create_simple("hpet", HPET_BASE, NULL);
 1103: 
 1104:         for (i = 0; i < 24; i++) {
 1105:             sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]);
 1106:         }
 1107:         rtc_irq = qdev_get_gpio_in(hpet, 0);
 1108:     }
 1109:     *rtc_state = rtc_init(2000, rtc_irq);
 1110: 
 1111:     qemu_register_boot_set(pc_boot_set, *rtc_state);
 1112: 
 1113:     pit = pit_init(0x40, isa_get_irq(0));
 1114:     pcspk_init(pit);
 1115: 
 1116:     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 1117:         if (serial_hds[i]) {
 1118:             serial_isa_init(i, serial_hds[i]);
 1119:         }
 1120:     }
 1121: 
 1122:     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 1123:         if (parallel_hds[i]) {
 1124:             parallel_init(i, parallel_hds[i]);
 1125:         }
 1126:     }
 1127: 
 1128:     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
 1129:     i8042 = isa_create_simple("i8042");
 1130:     i8042_setup_a20_line(i8042, &a20_line[0]);
 1131:     vmmouse_init(i8042);
 1132:     port92 = isa_create_simple("port92");
 1133:     port92_init(port92, &a20_line[1]);
 1134: 
 1135:     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 1136:     DMA_init(0, cpu_exit_irq);
 1137: 
 1138:     for(i = 0; i < MAX_FD; i++) {
 1139:         fd[i] = drive_get(IF_FLOPPY, 0, i);
 1140:     }
 1141:     *floppy_controller = fdctrl_init_isa(fd);
 1142: }
 1143: 
 1144: void pc_pci_device_init(PCIBus *pci_bus)
 1145: {
 1146:     int max_bus;
 1147:     int bus;
 1148: 
 1149:     max_bus = drive_get_max_bus(IF_SCSI);
 1150:     for (bus = 0; bus <= max_bus; bus++) {
 1151:         pci_create_simple(pci_bus, -1, "lsi53c895a");
 1152:     }
 1153: }

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