Annotation of qemu/hw/pci.c, revision 1.1.1.16

1.1       root        1: /*
                      2:  * QEMU PCI bus manager
                      3:  *
                      4:  * Copyright (c) 2004 Fabrice Bellard
1.1.1.6   root        5:  *
1.1       root        6:  * Permission is hereby granted, free of charge, to any person obtaining a copy
                      7:  * of this software and associated documentation files (the "Software"), to deal
                      8:  * in the Software without restriction, including without limitation the rights
                      9:  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
                     10:  * copies of the Software, and to permit persons to whom the Software is
                     11:  * furnished to do so, subject to the following conditions:
                     12:  *
                     13:  * The above copyright notice and this permission notice shall be included in
                     14:  * all copies or substantial portions of the Software.
                     15:  *
                     16:  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
                     17:  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
                     18:  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
                     19:  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
                     20:  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
                     21:  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
                     22:  * THE SOFTWARE.
                     23:  */
1.1.1.6   root       24: #include "hw.h"
                     25: #include "pci.h"
1.1.1.14  root       26: #include "pci_bridge.h"
                     27: #include "pci_internals.h"
1.1.1.9   root       28: #include "monitor.h"
1.1.1.6   root       29: #include "net.h"
1.1.1.7   root       30: #include "sysemu.h"
1.1.1.10  root       31: #include "loader.h"
1.1.1.14  root       32: #include "range.h"
1.1.1.16! root       33: #include "qmp-commands.h"
1.1       root       34: 
                     35: //#define DEBUG_PCI
1.1.1.9   root       36: #ifdef DEBUG_PCI
1.1.1.10  root       37: # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
1.1.1.9   root       38: #else
                     39: # define PCI_DPRINTF(format, ...)       do { } while (0)
                     40: #endif
1.1       root       41: 
1.1.1.9   root       42: static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
1.1.1.13  root       43: static char *pcibus_get_dev_path(DeviceState *dev);
1.1.1.14  root       44: static char *pcibus_get_fw_dev_path(DeviceState *dev);
                     45: static int pcibus_reset(BusState *qbus);
1.1.1.9   root       46: 
1.1.1.14  root       47: struct BusInfo pci_bus_info = {
1.1.1.9   root       48:     .name       = "PCI",
                     49:     .size       = sizeof(PCIBus),
                     50:     .print_dev  = pcibus_dev_print,
1.1.1.13  root       51:     .get_dev_path = pcibus_get_dev_path,
1.1.1.14  root       52:     .get_fw_dev_path = pcibus_get_fw_dev_path,
                     53:     .reset      = pcibus_reset,
1.1.1.9   root       54:     .props      = (Property[]) {
1.1.1.10  root       55:         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
                     56:         DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
1.1.1.11  root       57:         DEFINE_PROP_UINT32("rombar",  PCIDevice, rom_bar, 1),
1.1.1.13  root       58:         DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
                     59:                         QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
1.1.1.14  root       60:         DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
                     61:                         QEMU_PCI_CAP_SERR_BITNR, true),
1.1.1.10  root       62:         DEFINE_PROP_END_OF_LIST()
1.1.1.9   root       63:     }
1.1       root       64: };
                     65: 
1.1.1.5   root       66: static void pci_update_mappings(PCIDevice *d);
1.1.1.6   root       67: static void pci_set_irq(void *opaque, int irq_num, int level);
1.1.1.14  root       68: static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
1.1.1.13  root       69: static void pci_del_option_rom(PCIDevice *pdev);
1.1.1.5   root       70: 
1.1.1.7   root       71: static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
                     72: static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
1.1       root       73: 
1.1.1.10  root       74: struct PCIHostBus {
                     75:     int domain;
                     76:     struct PCIBus *bus;
                     77:     QLIST_ENTRY(PCIHostBus) next;
                     78: };
                     79: static QLIST_HEAD(, PCIHostBus) host_buses;
                     80: 
                     81: static const VMStateDescription vmstate_pcibus = {
                     82:     .name = "PCIBUS",
                     83:     .version_id = 1,
                     84:     .minimum_version_id = 1,
                     85:     .minimum_version_id_old = 1,
                     86:     .fields      = (VMStateField []) {
                     87:         VMSTATE_INT32_EQUAL(nirq, PCIBus),
                     88:         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
                     89:         VMSTATE_END_OF_LIST()
                     90:     }
                     91: };
                     92: 
                     93: static int pci_bar(PCIDevice *d, int reg)
1.1.1.6   root       94: {
1.1.1.10  root       95:     uint8_t type;
                     96: 
                     97:     if (reg != PCI_ROM_SLOT)
                     98:         return PCI_BASE_ADDRESS_0 + reg * 4;
1.1.1.6   root       99: 
1.1.1.10  root      100:     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
                    101:     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
1.1.1.6   root      102: }
                    103: 
1.1.1.10  root      104: static inline int pci_irq_state(PCIDevice *d, int irq_num)
1.1.1.6   root      105: {
1.1.1.10  root      106:        return (d->irq_state >> irq_num) & 0x1;
                    107: }
1.1.1.6   root      108: 
1.1.1.10  root      109: static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
                    110: {
                    111:        d->irq_state &= ~(0x1 << irq_num);
                    112:        d->irq_state |= level << irq_num;
                    113: }
                    114: 
                    115: static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
                    116: {
                    117:     PCIBus *bus;
                    118:     for (;;) {
                    119:         bus = pci_dev->bus;
                    120:         irq_num = bus->map_irq(pci_dev, irq_num);
                    121:         if (bus->set_irq)
                    122:             break;
                    123:         pci_dev = bus->parent_dev;
                    124:     }
                    125:     bus->irq_count[irq_num] += change;
                    126:     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
                    127: }
1.1.1.6   root      128: 
1.1.1.15  root      129: int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
                    130: {
                    131:     assert(irq_num >= 0);
                    132:     assert(irq_num < bus->nirq);
                    133:     return !!bus->irq_count[irq_num];
                    134: }
                    135: 
1.1.1.10  root      136: /* Update interrupt status bit in config space on interrupt
                    137:  * state change. */
                    138: static void pci_update_irq_status(PCIDevice *dev)
                    139: {
                    140:     if (dev->irq_state) {
                    141:         dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
                    142:     } else {
                    143:         dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
1.1.1.6   root      144:     }
1.1.1.10  root      145: }
1.1.1.6   root      146: 
1.1.1.14  root      147: void pci_device_deassert_intx(PCIDevice *dev)
                    148: {
                    149:     int i;
                    150:     for (i = 0; i < PCI_NUM_PINS; ++i) {
                    151:         qemu_set_irq(dev->irq[i], 0);
                    152:     }
                    153: }
                    154: 
                    155: /*
                    156:  * This function is called on #RST and FLR.
                    157:  * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
                    158:  */
                    159: void pci_device_reset(PCIDevice *dev)
1.1.1.10  root      160: {
                    161:     int r;
1.1.1.14  root      162:     /* TODO: call the below unconditionally once all pci devices
                    163:      * are qdevified */
                    164:     if (dev->qdev.info) {
                    165:         qdev_reset_all(&dev->qdev);
                    166:     }
1.1.1.6   root      167: 
1.1.1.10  root      168:     dev->irq_state = 0;
                    169:     pci_update_irq_status(dev);
1.1.1.14  root      170:     pci_device_deassert_intx(dev);
1.1.1.15  root      171:     /* Clear all writable bits */
1.1.1.14  root      172:     pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
                    173:                                  pci_get_word(dev->wmask + PCI_COMMAND) |
                    174:                                  pci_get_word(dev->w1cmask + PCI_COMMAND));
                    175:     pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
                    176:                                  pci_get_word(dev->wmask + PCI_STATUS) |
                    177:                                  pci_get_word(dev->w1cmask + PCI_STATUS));
1.1.1.10  root      178:     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
                    179:     dev->config[PCI_INTERRUPT_LINE] = 0x0;
                    180:     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
1.1.1.13  root      181:         PCIIORegion *region = &dev->io_regions[r];
                    182:         if (!region->size) {
1.1.1.10  root      183:             continue;
                    184:         }
1.1.1.13  root      185: 
                    186:         if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
                    187:             region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
                    188:             pci_set_quad(dev->config + pci_bar(dev, r), region->type);
                    189:         } else {
                    190:             pci_set_long(dev->config + pci_bar(dev, r), region->type);
                    191:         }
1.1.1.10  root      192:     }
                    193:     pci_update_mappings(dev);
1.1.1.6   root      194: }
                    195: 
1.1.1.14  root      196: /*
                    197:  * Trigger pci bus reset under a given bus.
                    198:  * To be called on RST# assert.
                    199:  */
                    200: void pci_bus_reset(PCIBus *bus)
1.1.1.9   root      201: {
                    202:     int i;
                    203: 
                    204:     for (i = 0; i < bus->nirq; i++) {
                    205:         bus->irq_count[i] = 0;
                    206:     }
1.1.1.10  root      207:     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
                    208:         if (bus->devices[i]) {
                    209:             pci_device_reset(bus->devices[i]);
                    210:         }
1.1.1.9   root      211:     }
                    212: }
                    213: 
1.1.1.14  root      214: static int pcibus_reset(BusState *qbus)
                    215: {
                    216:     pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
                    217: 
                    218:     /* topology traverse is done by pci_bus_reset().
                    219:        Tell qbus/qdev walker not to traverse the tree */
                    220:     return 1;
                    221: }
                    222: 
1.1.1.10  root      223: static void pci_host_bus_register(int domain, PCIBus *bus)
                    224: {
                    225:     struct PCIHostBus *host;
1.1.1.16! root      226:     host = g_malloc0(sizeof(*host));
1.1.1.10  root      227:     host->domain = domain;
                    228:     host->bus = bus;
                    229:     QLIST_INSERT_HEAD(&host_buses, host, next);
                    230: }
                    231: 
                    232: PCIBus *pci_find_root_bus(int domain)
                    233: {
                    234:     struct PCIHostBus *host;
                    235: 
                    236:     QLIST_FOREACH(host, &host_buses, next) {
                    237:         if (host->domain == domain) {
                    238:             return host->bus;
                    239:         }
                    240:     }
                    241: 
                    242:     return NULL;
                    243: }
                    244: 
1.1.1.13  root      245: int pci_find_domain(const PCIBus *bus)
                    246: {
                    247:     PCIDevice *d;
                    248:     struct PCIHostBus *host;
                    249: 
                    250:     /* obtain root bus */
                    251:     while ((d = bus->parent_dev) != NULL) {
                    252:         bus = d->bus;
                    253:     }
                    254: 
                    255:     QLIST_FOREACH(host, &host_buses, next) {
                    256:         if (host->bus == bus) {
                    257:             return host->domain;
                    258:         }
                    259:     }
                    260: 
                    261:     abort();    /* should not be reached */
                    262:     return -1;
                    263: }
                    264: 
1.1.1.10  root      265: void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
1.1.1.16! root      266:                          const char *name,
        !           267:                          MemoryRegion *address_space_mem,
        !           268:                          MemoryRegion *address_space_io,
        !           269:                          uint8_t devfn_min)
1.1.1.10  root      270: {
                    271:     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
1.1.1.13  root      272:     assert(PCI_FUNC(devfn_min) == 0);
1.1.1.10  root      273:     bus->devfn_min = devfn_min;
1.1.1.16! root      274:     bus->address_space_mem = address_space_mem;
        !           275:     bus->address_space_io = address_space_io;
1.1.1.10  root      276: 
                    277:     /* host bridge */
                    278:     QLIST_INIT(&bus->child);
                    279:     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
                    280: 
1.1.1.13  root      281:     vmstate_register(NULL, -1, &vmstate_pcibus, bus);
1.1.1.10  root      282: }
                    283: 
1.1.1.16! root      284: PCIBus *pci_bus_new(DeviceState *parent, const char *name,
        !           285:                     MemoryRegion *address_space_mem,
        !           286:                     MemoryRegion *address_space_io,
        !           287:                     uint8_t devfn_min)
1.1       root      288: {
                    289:     PCIBus *bus;
1.1.1.6   root      290: 
1.1.1.16! root      291:     bus = g_malloc0(sizeof(*bus));
1.1.1.10  root      292:     bus->qbus.qdev_allocated = 1;
1.1.1.16! root      293:     pci_bus_new_inplace(bus, parent, name, address_space_mem,
        !           294:                         address_space_io, devfn_min);
1.1.1.10  root      295:     return bus;
                    296: }
                    297: 
                    298: void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
                    299:                   void *irq_opaque, int nirq)
                    300: {
1.1.1.4   root      301:     bus->set_irq = set_irq;
1.1.1.5   root      302:     bus->map_irq = map_irq;
1.1.1.10  root      303:     bus->irq_opaque = irq_opaque;
1.1.1.6   root      304:     bus->nirq = nirq;
1.1.1.16! root      305:     bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
1.1       root      306: }
                    307: 
1.1.1.13  root      308: void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
1.1.1.10  root      309: {
                    310:     bus->qbus.allow_hotplug = 1;
                    311:     bus->hotplug = hotplug;
1.1.1.13  root      312:     bus->hotplug_qdev = qdev;
                    313: }
                    314: 
1.1.1.10  root      315: PCIBus *pci_register_bus(DeviceState *parent, const char *name,
                    316:                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
1.1.1.16! root      317:                          void *irq_opaque,
        !           318:                          MemoryRegion *address_space_mem,
        !           319:                          MemoryRegion *address_space_io,
        !           320:                          uint8_t devfn_min, int nirq)
1.1.1.5   root      321: {
                    322:     PCIBus *bus;
1.1.1.9   root      323: 
1.1.1.16! root      324:     bus = pci_bus_new(parent, name, address_space_mem,
        !           325:                       address_space_io, devfn_min);
1.1.1.10  root      326:     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
                    327:     return bus;
                    328: }
                    329: 
1.1.1.4   root      330: int pci_bus_num(PCIBus *s)
                    331: {
1.1.1.10  root      332:     if (!s->parent_dev)
                    333:         return 0;       /* pci host bridge */
                    334:     return s->parent_dev->config[PCI_SECONDARY_BUS];
1.1.1.4   root      335: }
                    336: 
1.1.1.10  root      337: static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
1.1       root      338: {
1.1.1.10  root      339:     PCIDevice *s = container_of(pv, PCIDevice, config);
                    340:     uint8_t *config;
1.1.1.6   root      341:     int i;
                    342: 
1.1.1.10  root      343:     assert(size == pci_config_size(s));
1.1.1.16! root      344:     config = g_malloc(size);
1.1.1.10  root      345: 
                    346:     qemu_get_buffer(f, config, size);
                    347:     for (i = 0; i < size; ++i) {
1.1.1.14  root      348:         if ((config[i] ^ s->config[i]) &
                    349:             s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
1.1.1.16! root      350:             g_free(config);
1.1.1.10  root      351:             return -EINVAL;
                    352:         }
                    353:     }
                    354:     memcpy(s->config, config, size);
                    355: 
                    356:     pci_update_mappings(s);
                    357: 
1.1.1.16! root      358:     g_free(config);
1.1.1.10  root      359:     return 0;
1.1       root      360: }
                    361: 
1.1.1.10  root      362: /* just put buffer */
                    363: static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
1.1       root      364: {
1.1.1.10  root      365:     const uint8_t **v = pv;
                    366:     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
                    367:     qemu_put_buffer(f, *v, size);
                    368: }
1.1.1.6   root      369: 
1.1.1.10  root      370: static VMStateInfo vmstate_info_pci_config = {
                    371:     .name = "pci config",
                    372:     .get  = get_pci_config_device,
                    373:     .put  = put_pci_config_device,
                    374: };
                    375: 
                    376: static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
                    377: {
1.1.1.12  root      378:     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
1.1.1.10  root      379:     uint32_t irq_state[PCI_NUM_PINS];
                    380:     int i;
                    381:     for (i = 0; i < PCI_NUM_PINS; ++i) {
                    382:         irq_state[i] = qemu_get_be32(f);
                    383:         if (irq_state[i] != 0x1 && irq_state[i] != 0) {
                    384:             fprintf(stderr, "irq state %d: must be 0 or 1.\n",
                    385:                     irq_state[i]);
1.1.1.9   root      386:             return -EINVAL;
1.1.1.10  root      387:         }
                    388:     }
1.1.1.9   root      389: 
1.1.1.10  root      390:     for (i = 0; i < PCI_NUM_PINS; ++i) {
                    391:         pci_set_irq_state(s, i, irq_state[i]);
                    392:     }
1.1.1.6   root      393: 
1.1       root      394:     return 0;
                    395: }
                    396: 
1.1.1.10  root      397: static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
                    398: {
                    399:     int i;
1.1.1.12  root      400:     PCIDevice *s = container_of(pv, PCIDevice, irq_state);
1.1.1.10  root      401: 
                    402:     for (i = 0; i < PCI_NUM_PINS; ++i) {
                    403:         qemu_put_be32(f, pci_irq_state(s, i));
                    404:     }
                    405: }
                    406: 
                    407: static VMStateInfo vmstate_info_pci_irq_state = {
                    408:     .name = "pci irq state",
                    409:     .get  = get_pci_irq_state,
                    410:     .put  = put_pci_irq_state,
                    411: };
                    412: 
                    413: const VMStateDescription vmstate_pci_device = {
                    414:     .name = "PCIDevice",
                    415:     .version_id = 2,
                    416:     .minimum_version_id = 1,
                    417:     .minimum_version_id_old = 1,
                    418:     .fields      = (VMStateField []) {
                    419:         VMSTATE_INT32_LE(version_id, PCIDevice),
                    420:         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
                    421:                                    vmstate_info_pci_config,
                    422:                                    PCI_CONFIG_SPACE_SIZE),
                    423:         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
                    424:                                   vmstate_info_pci_irq_state,
                    425:                                   PCI_NUM_PINS * sizeof(int32_t)),
                    426:         VMSTATE_END_OF_LIST()
                    427:     }
                    428: };
                    429: 
                    430: const VMStateDescription vmstate_pcie_device = {
                    431:     .name = "PCIDevice",
                    432:     .version_id = 2,
                    433:     .minimum_version_id = 1,
                    434:     .minimum_version_id_old = 1,
                    435:     .fields      = (VMStateField []) {
                    436:         VMSTATE_INT32_LE(version_id, PCIDevice),
                    437:         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
                    438:                                    vmstate_info_pci_config,
                    439:                                    PCIE_CONFIG_SPACE_SIZE),
                    440:         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
                    441:                                   vmstate_info_pci_irq_state,
                    442:                                   PCI_NUM_PINS * sizeof(int32_t)),
                    443:         VMSTATE_END_OF_LIST()
                    444:     }
                    445: };
                    446: 
                    447: static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
                    448: {
                    449:     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
                    450: }
                    451: 
                    452: void pci_device_save(PCIDevice *s, QEMUFile *f)
                    453: {
                    454:     /* Clear interrupt status bit: it is implicit
                    455:      * in irq_state which we are saving.
                    456:      * This makes us compatible with old devices
                    457:      * which never set or clear this bit. */
                    458:     s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
                    459:     vmstate_save_state(f, pci_get_vmstate(s), s);
                    460:     /* Restore the interrupt status bit. */
                    461:     pci_update_irq_status(s);
                    462: }
                    463: 
                    464: int pci_device_load(PCIDevice *s, QEMUFile *f)
                    465: {
                    466:     int ret;
                    467:     ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
                    468:     /* Restore the interrupt status bit. */
                    469:     pci_update_irq_status(s);
                    470:     return ret;
                    471: }
                    472: 
1.1.1.13  root      473: static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
1.1.1.7   root      474: {
1.1.1.13  root      475:     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
                    476:                  pci_default_sub_vendor_id);
                    477:     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
                    478:                  pci_default_sub_device_id);
1.1.1.7   root      479: }
                    480: 
                    481: /*
1.1.1.14  root      482:  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
                    483:  *       [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
1.1.1.7   root      484:  */
1.1.1.14  root      485: int pci_parse_devaddr(const char *addr, int *domp, int *busp,
                    486:                       unsigned int *slotp, unsigned int *funcp)
1.1.1.7   root      487: {
                    488:     const char *p;
                    489:     char *e;
                    490:     unsigned long val;
                    491:     unsigned long dom = 0, bus = 0;
1.1.1.14  root      492:     unsigned int slot = 0;
                    493:     unsigned int func = 0;
1.1.1.7   root      494: 
                    495:     p = addr;
                    496:     val = strtoul(p, &e, 16);
                    497:     if (e == p)
                    498:        return -1;
                    499:     if (*e == ':') {
                    500:        bus = val;
                    501:        p = e + 1;
                    502:        val = strtoul(p, &e, 16);
                    503:        if (e == p)
                    504:            return -1;
                    505:        if (*e == ':') {
                    506:            dom = bus;
                    507:            bus = val;
                    508:            p = e + 1;
                    509:            val = strtoul(p, &e, 16);
                    510:            if (e == p)
                    511:                return -1;
                    512:        }
                    513:     }
                    514: 
                    515:     slot = val;
                    516: 
1.1.1.14  root      517:     if (funcp != NULL) {
                    518:         if (*e != '.')
                    519:             return -1;
                    520: 
                    521:         p = e + 1;
                    522:         val = strtoul(p, &e, 16);
                    523:         if (e == p)
                    524:             return -1;
                    525: 
                    526:         func = val;
                    527:     }
                    528: 
                    529:     /* if funcp == NULL func is 0 */
                    530:     if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
                    531:        return -1;
                    532: 
1.1.1.7   root      533:     if (*e)
                    534:        return -1;
                    535: 
                    536:     /* Note: QEMU doesn't implement domains other than 0 */
1.1.1.10  root      537:     if (!pci_find_bus(pci_find_root_bus(dom), bus))
1.1.1.7   root      538:        return -1;
                    539: 
                    540:     *domp = dom;
                    541:     *busp = bus;
                    542:     *slotp = slot;
1.1.1.14  root      543:     if (funcp != NULL)
                    544:         *funcp = func;
1.1.1.7   root      545:     return 0;
                    546: }
                    547: 
1.1.1.9   root      548: int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
                    549:                      unsigned *slotp)
1.1.1.7   root      550: {
1.1.1.9   root      551:     /* strip legacy tag */
                    552:     if (!strncmp(addr, "pci_addr=", 9)) {
                    553:         addr += 9;
                    554:     }
1.1.1.14  root      555:     if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
1.1.1.9   root      556:         monitor_printf(mon, "Invalid pci address\n");
1.1.1.7   root      557:         return -1;
1.1.1.9   root      558:     }
                    559:     return 0;
1.1.1.7   root      560: }
                    561: 
1.1.1.10  root      562: PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
1.1.1.7   root      563: {
1.1.1.9   root      564:     int dom, bus;
                    565:     unsigned slot;
1.1.1.7   root      566: 
1.1.1.9   root      567:     if (!devaddr) {
                    568:         *devfnp = -1;
1.1.1.10  root      569:         return pci_find_bus(pci_find_root_bus(0), 0);
1.1.1.9   root      570:     }
1.1.1.7   root      571: 
1.1.1.14  root      572:     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
1.1.1.9   root      573:         return NULL;
1.1.1.7   root      574:     }
                    575: 
1.1.1.15  root      576:     *devfnp = PCI_DEVFN(slot, 0);
1.1.1.13  root      577:     return pci_find_bus(pci_find_root_bus(dom), bus);
1.1.1.7   root      578: }
                    579: 
1.1.1.9   root      580: static void pci_init_cmask(PCIDevice *dev)
1.1       root      581: {
1.1.1.9   root      582:     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
                    583:     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
                    584:     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
                    585:     dev->cmask[PCI_REVISION_ID] = 0xff;
                    586:     dev->cmask[PCI_CLASS_PROG] = 0xff;
                    587:     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
                    588:     dev->cmask[PCI_HEADER_TYPE] = 0xff;
                    589:     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
                    590: }
1.1       root      591: 
1.1.1.9   root      592: static void pci_init_wmask(PCIDevice *dev)
                    593: {
1.1.1.10  root      594:     int config_size = pci_config_size(dev);
                    595: 
1.1.1.9   root      596:     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
                    597:     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
1.1.1.10  root      598:     pci_set_word(dev->wmask + PCI_COMMAND,
1.1.1.13  root      599:                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
                    600:                  PCI_COMMAND_INTX_DISABLE);
1.1.1.14  root      601:     if (dev->cap_present & QEMU_PCI_CAP_SERR) {
                    602:         pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
                    603:     }
1.1.1.10  root      604: 
                    605:     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
                    606:            config_size - PCI_CONFIG_HEADER_SIZE);
                    607: }
                    608: 
1.1.1.14  root      609: static void pci_init_w1cmask(PCIDevice *dev)
                    610: {
                    611:     /*
                    612:      * Note: It's okay to set w1cmask even for readonly bits as
                    613:      * long as their value is hardwired to 0.
                    614:      */
                    615:     pci_set_word(dev->w1cmask + PCI_STATUS,
                    616:                  PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
                    617:                  PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
                    618:                  PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
                    619: }
                    620: 
1.1.1.10  root      621: static void pci_init_wmask_bridge(PCIDevice *d)
                    622: {
                    623:     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
                    624:        PCI_SEC_LETENCY_TIMER */
                    625:     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
                    626: 
                    627:     /* base and limit */
                    628:     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
                    629:     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
                    630:     pci_set_word(d->wmask + PCI_MEMORY_BASE,
                    631:                  PCI_MEMORY_RANGE_MASK & 0xffff);
                    632:     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
                    633:                  PCI_MEMORY_RANGE_MASK & 0xffff);
                    634:     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
                    635:                  PCI_PREF_RANGE_MASK & 0xffff);
                    636:     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
                    637:                  PCI_PREF_RANGE_MASK & 0xffff);
                    638: 
                    639:     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
                    640:     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
                    641: 
1.1.1.14  root      642: /* TODO: add this define to pci_regs.h in linux and then in qemu. */
                    643: #define  PCI_BRIDGE_CTL_VGA_16BIT      0x10    /* VGA 16-bit decode */
                    644: #define  PCI_BRIDGE_CTL_DISCARD                0x100   /* Primary discard timer */
                    645: #define  PCI_BRIDGE_CTL_SEC_DISCARD    0x200   /* Secondary discard timer */
                    646: #define  PCI_BRIDGE_CTL_DISCARD_STATUS 0x400   /* Discard timer status */
                    647: #define  PCI_BRIDGE_CTL_DISCARD_SERR   0x800   /* Discard timer SERR# enable */
                    648:     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
                    649:                  PCI_BRIDGE_CTL_PARITY |
                    650:                  PCI_BRIDGE_CTL_SERR |
                    651:                  PCI_BRIDGE_CTL_ISA |
                    652:                  PCI_BRIDGE_CTL_VGA |
                    653:                  PCI_BRIDGE_CTL_VGA_16BIT |
                    654:                  PCI_BRIDGE_CTL_MASTER_ABORT |
                    655:                  PCI_BRIDGE_CTL_BUS_RESET |
                    656:                  PCI_BRIDGE_CTL_FAST_BACK |
                    657:                  PCI_BRIDGE_CTL_DISCARD |
                    658:                  PCI_BRIDGE_CTL_SEC_DISCARD |
                    659:                  PCI_BRIDGE_CTL_DISCARD_SERR);
                    660:     /* Below does not do anything as we never set this bit, put here for
                    661:      * completeness. */
                    662:     pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
                    663:                  PCI_BRIDGE_CTL_DISCARD_STATUS);
1.1.1.10  root      664: }
                    665: 
1.1.1.13  root      666: static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
                    667: {
                    668:     uint8_t slot = PCI_SLOT(dev->devfn);
                    669:     uint8_t func;
                    670: 
                    671:     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
                    672:         dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
                    673:     }
                    674: 
                    675:     /*
1.1.1.14  root      676:      * multifunction bit is interpreted in two ways as follows.
1.1.1.13  root      677:      *   - all functions must set the bit to 1.
                    678:      *     Example: Intel X53
                    679:      *   - function 0 must set the bit, but the rest function (> 0)
                    680:      *     is allowed to leave the bit to 0.
                    681:      *     Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
                    682:      *
                    683:      * So OS (at least Linux) checks the bit of only function 0,
                    684:      * and doesn't see the bit of function > 0.
                    685:      *
                    686:      * The below check allows both interpretation.
                    687:      */
                    688:     if (PCI_FUNC(dev->devfn)) {
                    689:         PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
                    690:         if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
                    691:             /* function 0 should set multifunction bit */
                    692:             error_report("PCI: single function device can't be populated "
                    693:                          "in function %x.%x", slot, PCI_FUNC(dev->devfn));
                    694:             return -1;
                    695:         }
                    696:         return 0;
                    697:     }
                    698: 
                    699:     if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
                    700:         return 0;
                    701:     }
                    702:     /* function 0 indicates single function, so function > 0 must be NULL */
                    703:     for (func = 1; func < PCI_FUNC_MAX; ++func) {
                    704:         if (bus->devices[PCI_DEVFN(slot, func)]) {
                    705:             error_report("PCI: %x.0 indicates single function, "
                    706:                          "but %x.%x is already populated.",
                    707:                          slot, slot, func);
                    708:             return -1;
                    709:         }
                    710:     }
                    711:     return 0;
                    712: }
                    713: 
1.1.1.10  root      714: static void pci_config_alloc(PCIDevice *pci_dev)
                    715: {
                    716:     int config_size = pci_config_size(pci_dev);
                    717: 
1.1.1.16! root      718:     pci_dev->config = g_malloc0(config_size);
        !           719:     pci_dev->cmask = g_malloc0(config_size);
        !           720:     pci_dev->wmask = g_malloc0(config_size);
        !           721:     pci_dev->w1cmask = g_malloc0(config_size);
        !           722:     pci_dev->used = g_malloc0(config_size);
1.1.1.10  root      723: }
                    724: 
                    725: static void pci_config_free(PCIDevice *pci_dev)
                    726: {
1.1.1.16! root      727:     g_free(pci_dev->config);
        !           728:     g_free(pci_dev->cmask);
        !           729:     g_free(pci_dev->wmask);
        !           730:     g_free(pci_dev->w1cmask);
        !           731:     g_free(pci_dev->used);
1.1.1.9   root      732: }
1.1.1.6   root      733: 
1.1.1.9   root      734: /* -1 for devfn means auto assign */
                    735: static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
                    736:                                          const char *name, int devfn,
1.1.1.15  root      737:                                          const PCIDeviceInfo *info)
1.1.1.9   root      738: {
1.1.1.15  root      739:     PCIConfigReadFunc *config_read = info->config_read;
                    740:     PCIConfigWriteFunc *config_write = info->config_write;
                    741: 
1.1       root      742:     if (devfn < 0) {
1.1.1.10  root      743:         for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
1.1.1.13  root      744:             devfn += PCI_FUNC_MAX) {
1.1       root      745:             if (!bus->devices[devfn])
                    746:                 goto found;
                    747:         }
1.1.1.13  root      748:         error_report("PCI: no slot/function available for %s, all in use", name);
1.1       root      749:         return NULL;
                    750:     found: ;
1.1.1.9   root      751:     } else if (bus->devices[devfn]) {
1.1.1.13  root      752:         error_report("PCI: slot %d function %d not available for %s, in use by %s",
                    753:                      PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
1.1.1.9   root      754:         return NULL;
1.1       root      755:     }
                    756:     pci_dev->bus = bus;
                    757:     pci_dev->devfn = devfn;
                    758:     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
1.1.1.10  root      759:     pci_dev->irq_state = 0;
                    760:     pci_config_alloc(pci_dev);
                    761: 
1.1.1.15  root      762:     pci_config_set_vendor_id(pci_dev->config, info->vendor_id);
                    763:     pci_config_set_device_id(pci_dev->config, info->device_id);
                    764:     pci_config_set_revision(pci_dev->config, info->revision);
                    765:     pci_config_set_class(pci_dev->config, info->class_id);
                    766: 
                    767:     if (!info->is_bridge) {
                    768:         if (info->subsystem_vendor_id || info->subsystem_id) {
                    769:             pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
                    770:                          info->subsystem_vendor_id);
                    771:             pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
                    772:                          info->subsystem_id);
                    773:         } else {
                    774:             pci_set_default_subsystem_id(pci_dev);
                    775:         }
                    776:     } else {
                    777:         /* subsystem_vendor_id/subsystem_id are only for header type 0 */
                    778:         assert(!info->subsystem_vendor_id);
                    779:         assert(!info->subsystem_id);
1.1.1.10  root      780:     }
1.1.1.9   root      781:     pci_init_cmask(pci_dev);
                    782:     pci_init_wmask(pci_dev);
1.1.1.14  root      783:     pci_init_w1cmask(pci_dev);
1.1.1.15  root      784:     if (info->is_bridge) {
1.1.1.10  root      785:         pci_init_wmask_bridge(pci_dev);
                    786:     }
1.1.1.13  root      787:     if (pci_init_multifunction(bus, pci_dev)) {
                    788:         pci_config_free(pci_dev);
                    789:         return NULL;
                    790:     }
1.1       root      791: 
                    792:     if (!config_read)
                    793:         config_read = pci_default_read_config;
                    794:     if (!config_write)
                    795:         config_write = pci_default_write_config;
                    796:     pci_dev->config_read = config_read;
                    797:     pci_dev->config_write = config_write;
                    798:     bus->devices[devfn] = pci_dev;
1.1.1.10  root      799:     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
                    800:     pci_dev->version_id = 2; /* Current pci device vmstate version */
1.1       root      801:     return pci_dev;
                    802: }
                    803: 
1.1.1.13  root      804: static void do_pci_unregister_device(PCIDevice *pci_dev)
                    805: {
                    806:     qemu_free_irqs(pci_dev->irq);
                    807:     pci_dev->bus->devices[pci_dev->devfn] = NULL;
                    808:     pci_config_free(pci_dev);
                    809: }
                    810: 
1.1.1.15  root      811: /* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
1.1.1.9   root      812: PCIDevice *pci_register_device(PCIBus *bus, const char *name,
                    813:                                int instance_size, int devfn,
                    814:                                PCIConfigReadFunc *config_read,
                    815:                                PCIConfigWriteFunc *config_write)
                    816: {
                    817:     PCIDevice *pci_dev;
1.1.1.15  root      818:     PCIDeviceInfo info = {
                    819:         .config_read = config_read,
                    820:         .config_write = config_write,
                    821:     };
1.1.1.9   root      822: 
1.1.1.16! root      823:     pci_dev = g_malloc0(instance_size);
1.1.1.15  root      824:     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, &info);
1.1.1.10  root      825:     if (pci_dev == NULL) {
                    826:         hw_error("PCI: can't register device\n");
                    827:     }
1.1.1.9   root      828:     return pci_dev;
                    829: }
1.1.1.13  root      830: 
1.1.1.7   root      831: static void pci_unregister_io_regions(PCIDevice *pci_dev)
                    832: {
                    833:     PCIIORegion *r;
                    834:     int i;
                    835: 
                    836:     for(i = 0; i < PCI_NUM_REGIONS; i++) {
                    837:         r = &pci_dev->io_regions[i];
1.1.1.10  root      838:         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
1.1.1.7   root      839:             continue;
1.1.1.16! root      840:         memory_region_del_subregion(r->address_space, r->memory);
1.1.1.7   root      841:     }
                    842: }
                    843: 
1.1.1.10  root      844: static int pci_unregister_device(DeviceState *dev)
1.1.1.7   root      845: {
1.1.1.10  root      846:     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
                    847:     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
1.1.1.7   root      848:     int ret = 0;
                    849: 
1.1.1.10  root      850:     if (info->exit)
                    851:         ret = info->exit(pci_dev);
1.1.1.7   root      852:     if (ret)
                    853:         return ret;
                    854: 
                    855:     pci_unregister_io_regions(pci_dev);
1.1.1.13  root      856:     pci_del_option_rom(pci_dev);
1.1.1.16! root      857:     g_free(pci_dev->romfile);
1.1.1.13  root      858:     do_pci_unregister_device(pci_dev);
1.1.1.7   root      859:     return 0;
                    860: }
                    861: 
1.1.1.9   root      862: void pci_register_bar(PCIDevice *pci_dev, int region_num,
1.1.1.16! root      863:                       uint8_t type, MemoryRegion *memory)
1.1       root      864: {
                    865:     PCIIORegion *r;
1.1.1.3   root      866:     uint32_t addr;
1.1.1.14  root      867:     uint64_t wmask;
1.1.1.16! root      868:     pcibus_t size = memory_region_size(memory);
1.1.1.7   root      869: 
1.1.1.14  root      870:     assert(region_num >= 0);
                    871:     assert(region_num < PCI_NUM_REGIONS);
1.1.1.7   root      872:     if (size & (size-1)) {
                    873:         fprintf(stderr, "ERROR: PCI region size must be pow2 "
1.1.1.10  root      874:                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
1.1.1.7   root      875:         exit(1);
                    876:     }
                    877: 
1.1       root      878:     r = &pci_dev->io_regions[region_num];
1.1.1.10  root      879:     r->addr = PCI_BAR_UNMAPPED;
1.1       root      880:     r->size = size;
                    881:     r->type = type;
1.1.1.16! root      882:     r->memory = NULL;
1.1.1.9   root      883: 
                    884:     wmask = ~(size - 1);
1.1.1.10  root      885:     addr = pci_bar(pci_dev, region_num);
1.1.1.3   root      886:     if (region_num == PCI_ROM_SLOT) {
1.1.1.15  root      887:         /* ROM enable bit is writable */
1.1.1.10  root      888:         wmask |= PCI_ROM_ADDRESS_ENABLE;
                    889:     }
                    890:     pci_set_long(pci_dev->config + addr, type);
                    891:     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
                    892:         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
                    893:         pci_set_quad(pci_dev->wmask + addr, wmask);
                    894:         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1.1.1.3   root      895:     } else {
1.1.1.10  root      896:         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
                    897:         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1.1.1.3   root      898:     }
1.1.1.16! root      899:     pci_dev->io_regions[region_num].memory = memory;
        !           900:     pci_dev->io_regions[region_num].address_space
        !           901:         = type & PCI_BASE_ADDRESS_SPACE_IO
        !           902:         ? pci_dev->bus->address_space_io
        !           903:         : pci_dev->bus->address_space_mem;
1.1       root      904: }
                    905: 
1.1.1.16! root      906: pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1.1.1.15  root      907: {
1.1.1.16! root      908:     return pci_dev->io_regions[region_num].addr;
1.1       root      909: }
                    910: 
1.1.1.10  root      911: static pcibus_t pci_bar_address(PCIDevice *d,
                    912:                                int reg, uint8_t type, pcibus_t size)
1.1       root      913: {
1.1.1.10  root      914:     pcibus_t new_addr, last_addr;
                    915:     int bar = pci_bar(d, reg);
                    916:     uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1.1.1.5   root      917: 
1.1.1.10  root      918:     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
                    919:         if (!(cmd & PCI_COMMAND_IO)) {
                    920:             return PCI_BAR_UNMAPPED;
                    921:         }
                    922:         new_addr = pci_get_long(d->config + bar) & ~(size - 1);
                    923:         last_addr = new_addr + size - 1;
                    924:         /* NOTE: we have only 64K ioports on PC */
                    925:         if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
                    926:             return PCI_BAR_UNMAPPED;
                    927:         }
                    928:         return new_addr;
1.1       root      929:     }
1.1.1.10  root      930: 
                    931:     if (!(cmd & PCI_COMMAND_MEMORY)) {
                    932:         return PCI_BAR_UNMAPPED;
                    933:     }
                    934:     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
                    935:         new_addr = pci_get_quad(d->config + bar);
                    936:     } else {
                    937:         new_addr = pci_get_long(d->config + bar);
                    938:     }
                    939:     /* the ROM slot has a specific enable bit */
                    940:     if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
                    941:         return PCI_BAR_UNMAPPED;
                    942:     }
                    943:     new_addr &= ~(size - 1);
                    944:     last_addr = new_addr + size - 1;
                    945:     /* NOTE: we do not support wrapping */
                    946:     /* XXX: as we cannot support really dynamic
                    947:        mappings, we handle specific values as invalid
                    948:        mappings. */
                    949:     if (last_addr <= new_addr || new_addr == 0 ||
                    950:         last_addr == PCI_BAR_UNMAPPED) {
                    951:         return PCI_BAR_UNMAPPED;
                    952:     }
                    953: 
                    954:     /* Now pcibus_t is 64bit.
                    955:      * Check if 32 bit BAR wraps around explicitly.
                    956:      * Without this, PC ide doesn't work well.
                    957:      * TODO: remove this work around.
                    958:      */
                    959:     if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
                    960:         return PCI_BAR_UNMAPPED;
                    961:     }
                    962: 
                    963:     /*
                    964:      * OS is allowed to set BAR beyond its addressable
                    965:      * bits. For example, 32 bit OS can set 64bit bar
                    966:      * to >4G. Check it. TODO: we might need to support
                    967:      * it in the future for e.g. PAE.
                    968:      */
                    969:     if (last_addr >= TARGET_PHYS_ADDR_MAX) {
                    970:         return PCI_BAR_UNMAPPED;
                    971:     }
                    972: 
                    973:     return new_addr;
1.1       root      974: }
                    975: 
1.1.1.10  root      976: static void pci_update_mappings(PCIDevice *d)
1.1       root      977: {
1.1.1.10  root      978:     PCIIORegion *r;
1.1.1.9   root      979:     int i;
1.1.1.16! root      980:     pcibus_t new_addr;
1.1       root      981: 
1.1.1.10  root      982:     for(i = 0; i < PCI_NUM_REGIONS; i++) {
                    983:         r = &d->io_regions[i];
                    984: 
                    985:         /* this region isn't registered */
                    986:         if (!r->size)
                    987:             continue;
                    988: 
                    989:         new_addr = pci_bar_address(d, i, r->type, r->size);
                    990: 
                    991:         /* This bar isn't changed */
1.1.1.16! root      992:         if (new_addr == r->addr)
1.1.1.10  root      993:             continue;
                    994: 
                    995:         /* now do the real mapping */
                    996:         if (r->addr != PCI_BAR_UNMAPPED) {
1.1.1.16! root      997:             memory_region_del_subregion(r->address_space, r->memory);
1.1.1.10  root      998:         }
                    999:         r->addr = new_addr;
                   1000:         if (r->addr != PCI_BAR_UNMAPPED) {
1.1.1.16! root     1001:             memory_region_add_subregion_overlap(r->address_space,
        !          1002:                                                 r->addr, r->memory, 1);
1.1.1.10  root     1003:         }
                   1004:     }
1.1       root     1005: }
                   1006: 
1.1.1.13  root     1007: static inline int pci_irq_disabled(PCIDevice *d)
                   1008: {
                   1009:     return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
                   1010: }
                   1011: 
                   1012: /* Called after interrupt disabled field update in config space,
                   1013:  * assert/deassert interrupts if necessary.
                   1014:  * Gets original interrupt disable bit value (before update). */
                   1015: static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
                   1016: {
                   1017:     int i, disabled = pci_irq_disabled(d);
                   1018:     if (disabled == was_irq_disabled)
                   1019:         return;
                   1020:     for (i = 0; i < PCI_NUM_PINS; ++i) {
                   1021:         int state = pci_irq_state(d, i);
                   1022:         pci_change_irq_level(d, i, disabled ? -state : state);
                   1023:     }
                   1024: }
                   1025: 
1.1.1.10  root     1026: uint32_t pci_default_read_config(PCIDevice *d,
                   1027:                                  uint32_t address, int len)
1.1       root     1028: {
1.1.1.10  root     1029:     uint32_t val = 0;
1.1.1.16! root     1030: 
1.1.1.10  root     1031:     memcpy(&val, d->config + address, len);
                   1032:     return le32_to_cpu(val);
1.1       root     1033: }
                   1034: 
1.1.1.10  root     1035: void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1.1       root     1036: {
1.1.1.13  root     1037:     int i, was_irq_disabled = pci_irq_disabled(d);
1.1       root     1038: 
1.1.1.16! root     1039:     for (i = 0; i < l; val >>= 8, ++i) {
1.1.1.10  root     1040:         uint8_t wmask = d->wmask[addr + i];
1.1.1.14  root     1041:         uint8_t w1cmask = d->w1cmask[addr + i];
                   1042:         assert(!(wmask & w1cmask));
1.1.1.10  root     1043:         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1.1.1.14  root     1044:         d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1.1.1.10  root     1045:     }
                   1046:     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
                   1047:         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
                   1048:         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
                   1049:         range_covers_byte(addr, l, PCI_COMMAND))
                   1050:         pci_update_mappings(d);
1.1.1.13  root     1051: 
                   1052:     if (range_covers_byte(addr, l, PCI_COMMAND))
                   1053:         pci_update_irq_disabled(d, was_irq_disabled);
1.1       root     1054: }
                   1055: 
1.1.1.4   root     1056: /***********************************************************/
                   1057: /* generic PCI irq support */
1.1       root     1058: 
1.1.1.4   root     1059: /* 0 <= irq_num <= 3. level must be 0 or 1 */
1.1.1.6   root     1060: static void pci_set_irq(void *opaque, int irq_num, int level)
1.1       root     1061: {
1.1.1.10  root     1062:     PCIDevice *pci_dev = opaque;
1.1.1.5   root     1063:     int change;
1.1.1.6   root     1064: 
1.1.1.10  root     1065:     change = level - pci_irq_state(pci_dev, irq_num);
1.1.1.5   root     1066:     if (!change)
                   1067:         return;
                   1068: 
1.1.1.10  root     1069:     pci_set_irq_state(pci_dev, irq_num, level);
                   1070:     pci_update_irq_status(pci_dev);
1.1.1.13  root     1071:     if (pci_irq_disabled(pci_dev))
                   1072:         return;
1.1.1.10  root     1073:     pci_change_irq_level(pci_dev, irq_num, change);
1.1       root     1074: }
                   1075: 
1.1.1.4   root     1076: /***********************************************************/
                   1077: /* monitor info on PCI */
1.1       root     1078: 
1.1.1.4   root     1079: typedef struct {
                   1080:     uint16_t class;
                   1081:     const char *desc;
1.1.1.14  root     1082:     const char *fw_name;
                   1083:     uint16_t fw_ign_bits;
1.1.1.4   root     1084: } pci_class_desc;
                   1085: 
1.1.1.7   root     1086: static const pci_class_desc pci_class_descriptions[] =
1.1.1.4   root     1087: {
1.1.1.14  root     1088:     { 0x0001, "VGA controller", "display"},
                   1089:     { 0x0100, "SCSI controller", "scsi"},
                   1090:     { 0x0101, "IDE controller", "ide"},
                   1091:     { 0x0102, "Floppy controller", "fdc"},
                   1092:     { 0x0103, "IPI controller", "ipi"},
                   1093:     { 0x0104, "RAID controller", "raid"},
1.1.1.6   root     1094:     { 0x0106, "SATA controller"},
                   1095:     { 0x0107, "SAS controller"},
                   1096:     { 0x0180, "Storage controller"},
1.1.1.14  root     1097:     { 0x0200, "Ethernet controller", "ethernet"},
                   1098:     { 0x0201, "Token Ring controller", "token-ring"},
                   1099:     { 0x0202, "FDDI controller", "fddi"},
                   1100:     { 0x0203, "ATM controller", "atm"},
1.1.1.6   root     1101:     { 0x0280, "Network controller"},
1.1.1.14  root     1102:     { 0x0300, "VGA controller", "display", 0x00ff},
1.1.1.6   root     1103:     { 0x0301, "XGA controller"},
                   1104:     { 0x0302, "3D controller"},
                   1105:     { 0x0380, "Display controller"},
1.1.1.14  root     1106:     { 0x0400, "Video controller", "video"},
                   1107:     { 0x0401, "Audio controller", "sound"},
1.1.1.6   root     1108:     { 0x0402, "Phone"},
1.1.1.15  root     1109:     { 0x0403, "Audio controller", "sound"},
1.1.1.6   root     1110:     { 0x0480, "Multimedia controller"},
1.1.1.14  root     1111:     { 0x0500, "RAM controller", "memory"},
                   1112:     { 0x0501, "Flash controller", "flash"},
1.1.1.6   root     1113:     { 0x0580, "Memory controller"},
1.1.1.14  root     1114:     { 0x0600, "Host bridge", "host"},
                   1115:     { 0x0601, "ISA bridge", "isa"},
                   1116:     { 0x0602, "EISA bridge", "eisa"},
                   1117:     { 0x0603, "MC bridge", "mca"},
                   1118:     { 0x0604, "PCI bridge", "pci"},
                   1119:     { 0x0605, "PCMCIA bridge", "pcmcia"},
                   1120:     { 0x0606, "NUBUS bridge", "nubus"},
                   1121:     { 0x0607, "CARDBUS bridge", "cardbus"},
1.1.1.6   root     1122:     { 0x0608, "RACEWAY bridge"},
                   1123:     { 0x0680, "Bridge"},
1.1.1.14  root     1124:     { 0x0700, "Serial port", "serial"},
                   1125:     { 0x0701, "Parallel port", "parallel"},
                   1126:     { 0x0800, "Interrupt controller", "interrupt-controller"},
                   1127:     { 0x0801, "DMA controller", "dma-controller"},
                   1128:     { 0x0802, "Timer", "timer"},
                   1129:     { 0x0803, "RTC", "rtc"},
                   1130:     { 0x0900, "Keyboard", "keyboard"},
                   1131:     { 0x0901, "Pen", "pen"},
                   1132:     { 0x0902, "Mouse", "mouse"},
                   1133:     { 0x0A00, "Dock station", "dock", 0x00ff},
                   1134:     { 0x0B00, "i386 cpu", "cpu", 0x00ff},
                   1135:     { 0x0c00, "Fireware contorller", "fireware"},
                   1136:     { 0x0c01, "Access bus controller", "access-bus"},
                   1137:     { 0x0c02, "SSA controller", "ssa"},
                   1138:     { 0x0c03, "USB controller", "usb"},
                   1139:     { 0x0c04, "Fibre channel controller", "fibre-channel"},
1.1.1.4   root     1140:     { 0, NULL}
                   1141: };
1.1       root     1142: 
1.1.1.13  root     1143: static void pci_for_each_device_under_bus(PCIBus *bus,
                   1144:                                           void (*fn)(PCIBus *b, PCIDevice *d))
1.1       root     1145: {
1.1.1.13  root     1146:     PCIDevice *d;
                   1147:     int devfn;
1.1       root     1148: 
1.1.1.13  root     1149:     for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
                   1150:         d = bus->devices[devfn];
                   1151:         if (d) {
                   1152:             fn(bus, d);
                   1153:         }
                   1154:     }
                   1155: }
                   1156: 
                   1157: void pci_for_each_device(PCIBus *bus, int bus_num,
                   1158:                          void (*fn)(PCIBus *b, PCIDevice *d))
                   1159: {
                   1160:     bus = pci_find_bus(bus, bus_num);
                   1161: 
                   1162:     if (bus) {
                   1163:         pci_for_each_device_under_bus(bus, fn);
                   1164:     }
                   1165: }
                   1166: 
1.1.1.16! root     1167: static const pci_class_desc *get_class_desc(int class)
1.1.1.13  root     1168: {
1.1.1.16! root     1169:     const pci_class_desc *desc;
1.1.1.13  root     1170: 
1.1.1.16! root     1171:     desc = pci_class_descriptions;
        !          1172:     while (desc->desc && class != desc->class) {
        !          1173:         desc++;
1.1.1.13  root     1174:     }
                   1175: 
1.1.1.16! root     1176:     return desc;
        !          1177: }
1.1.1.13  root     1178: 
1.1.1.16! root     1179: static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1.1.1.10  root     1180: 
1.1.1.16! root     1181: static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
        !          1182: {
        !          1183:     PciMemoryRegionList *head = NULL, *cur_item = NULL;
        !          1184:     int i;
1.1.1.10  root     1185: 
1.1.1.16! root     1186:     for (i = 0; i < PCI_NUM_REGIONS; i++) {
        !          1187:         const PCIIORegion *r = &dev->io_regions[i];
        !          1188:         PciMemoryRegionList *region;
1.1.1.13  root     1189: 
1.1.1.16! root     1190:         if (!r->size) {
        !          1191:             continue;
        !          1192:         }
1.1.1.13  root     1193: 
1.1.1.16! root     1194:         region = g_malloc0(sizeof(*region));
        !          1195:         region->value = g_malloc0(sizeof(*region->value));
1.1.1.13  root     1196: 
1.1.1.16! root     1197:         if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
        !          1198:             region->value->type = g_strdup("io");
1.1.1.13  root     1199:         } else {
1.1.1.16! root     1200:             region->value->type = g_strdup("memory");
        !          1201:             region->value->has_prefetch = true;
        !          1202:             region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
        !          1203:             region->value->has_mem_type_64 = true;
        !          1204:             region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1.1.1.13  root     1205:         }
1.1.1.10  root     1206: 
1.1.1.16! root     1207:         region->value->bar = i;
        !          1208:         region->value->address = r->addr;
        !          1209:         region->value->size = r->size;
        !          1210: 
        !          1211:         /* XXX: waiting for the qapi to support GSList */
        !          1212:         if (!cur_item) {
        !          1213:             head = cur_item = region;
        !          1214:         } else {
        !          1215:             cur_item->next = region;
        !          1216:             cur_item = region;
1.1.1.4   root     1217:         }
1.1       root     1218:     }
1.1.1.13  root     1219: 
1.1.1.16! root     1220:     return head;
1.1       root     1221: }
                   1222: 
1.1.1.16! root     1223: static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
        !          1224:                                            int bus_num)
1.1.1.13  root     1225: {
1.1.1.16! root     1226:     PciBridgeInfo *info;
1.1.1.13  root     1227: 
1.1.1.16! root     1228:     info = g_malloc0(sizeof(*info));
1.1.1.13  root     1229: 
1.1.1.16! root     1230:     info->bus.number = dev->config[PCI_PRIMARY_BUS];
        !          1231:     info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
        !          1232:     info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
1.1.1.13  root     1233: 
1.1.1.16! root     1234:     info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
        !          1235:     info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
        !          1236:     info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1.1.1.13  root     1237: 
1.1.1.16! root     1238:     info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
        !          1239:     info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
        !          1240:     info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1.1.1.13  root     1241: 
1.1.1.16! root     1242:     info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
        !          1243:     info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
        !          1244:     info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1.1.1.13  root     1245: 
1.1.1.16! root     1246:     if (dev->config[PCI_SECONDARY_BUS] != 0) {
        !          1247:         PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
        !          1248:         if (child_bus) {
        !          1249:             info->has_devices = true;
        !          1250:             info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1.1.1.13  root     1251:         }
                   1252:     }
                   1253: 
1.1.1.16! root     1254:     return info;
1.1.1.13  root     1255: }
                   1256: 
1.1.1.16! root     1257: static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
        !          1258:                                            int bus_num)
1.1.1.13  root     1259: {
1.1.1.16! root     1260:     const pci_class_desc *desc;
        !          1261:     PciDeviceInfo *info;
1.1.1.13  root     1262:     uint8_t type;
1.1.1.16! root     1263:     int class;
1.1.1.13  root     1264: 
1.1.1.16! root     1265:     info = g_malloc0(sizeof(*info));
        !          1266:     info->bus = bus_num;
        !          1267:     info->slot = PCI_SLOT(dev->devfn);
        !          1268:     info->function = PCI_FUNC(dev->devfn);
        !          1269: 
        !          1270:     class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
        !          1271:     info->class_info.class = class;
        !          1272:     desc = get_class_desc(class);
        !          1273:     if (desc->desc) {
        !          1274:         info->class_info.has_desc = true;
        !          1275:         info->class_info.desc = g_strdup(desc->desc);
        !          1276:     }
        !          1277: 
        !          1278:     info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
        !          1279:     info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
        !          1280:     info->regions = qmp_query_pci_regions(dev);
        !          1281:     info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1.1.1.13  root     1282: 
                   1283:     if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1.1.1.16! root     1284:         info->has_irq = true;
        !          1285:         info->irq = dev->config[PCI_INTERRUPT_LINE];
1.1.1.13  root     1286:     }
                   1287: 
                   1288:     type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
                   1289:     if (type == PCI_HEADER_TYPE_BRIDGE) {
1.1.1.16! root     1290:         info->has_pci_bridge = true;
        !          1291:         info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1.1.1.13  root     1292:     }
                   1293: 
1.1.1.16! root     1294:     return info;
1.1.1.13  root     1295: }
                   1296: 
1.1.1.16! root     1297: static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1.1       root     1298: {
1.1.1.16! root     1299:     PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1.1.1.13  root     1300:     PCIDevice *dev;
1.1.1.16! root     1301:     int devfn;
1.1.1.13  root     1302: 
                   1303:     for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
                   1304:         dev = bus->devices[devfn];
                   1305:         if (dev) {
1.1.1.16! root     1306:             info = g_malloc0(sizeof(*info));
        !          1307:             info->value = qmp_query_pci_device(dev, bus, bus_num);
        !          1308: 
        !          1309:             /* XXX: waiting for the qapi to support GSList */
        !          1310:             if (!cur_item) {
        !          1311:                 head = cur_item = info;
        !          1312:             } else {
        !          1313:                 cur_item->next = info;
        !          1314:                 cur_item = info;
        !          1315:             }
1.1.1.13  root     1316:         }
1.1       root     1317:     }
1.1.1.13  root     1318: 
1.1.1.16! root     1319:     return head;
1.1       root     1320: }
                   1321: 
1.1.1.16! root     1322: static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1.1       root     1323: {
1.1.1.16! root     1324:     PciInfo *info = NULL;
        !          1325: 
1.1.1.10  root     1326:     bus = pci_find_bus(bus, bus_num);
                   1327:     if (bus) {
1.1.1.16! root     1328:         info = g_malloc0(sizeof(*info));
        !          1329:         info->bus = bus_num;
        !          1330:         info->devices = qmp_query_pci_devices(bus, bus_num);
1.1.1.10  root     1331:     }
1.1.1.13  root     1332: 
1.1.1.16! root     1333:     return info;
1.1       root     1334: }
1.1.1.3   root     1335: 
1.1.1.16! root     1336: PciInfoList *qmp_query_pci(Error **errp)
1.1.1.9   root     1337: {
1.1.1.16! root     1338:     PciInfoList *info, *head = NULL, *cur_item = NULL;
1.1.1.10  root     1339:     struct PCIHostBus *host;
1.1.1.13  root     1340: 
1.1.1.10  root     1341:     QLIST_FOREACH(host, &host_buses, next) {
1.1.1.16! root     1342:         info = g_malloc0(sizeof(*info));
        !          1343:         info->value = qmp_query_pci_bus(host->bus, 0);
        !          1344: 
        !          1345:         /* XXX: waiting for the qapi to support GSList */
        !          1346:         if (!cur_item) {
        !          1347:             head = cur_item = info;
        !          1348:         } else {
        !          1349:             cur_item->next = info;
        !          1350:             cur_item = info;
1.1.1.13  root     1351:         }
1.1.1.9   root     1352:     }
1.1.1.13  root     1353: 
1.1.1.16! root     1354:     return head;
1.1.1.9   root     1355: }
                   1356: 
1.1.1.7   root     1357: static const char * const pci_nic_models[] = {
                   1358:     "ne2k_pci",
                   1359:     "i82551",
                   1360:     "i82557b",
                   1361:     "i82559er",
                   1362:     "rtl8139",
                   1363:     "e1000",
                   1364:     "pcnet",
                   1365:     "virtio",
                   1366:     NULL
                   1367: };
                   1368: 
1.1.1.9   root     1369: static const char * const pci_nic_names[] = {
                   1370:     "ne2k_pci",
                   1371:     "i82551",
                   1372:     "i82557b",
                   1373:     "i82559er",
                   1374:     "rtl8139",
                   1375:     "e1000",
                   1376:     "pcnet",
                   1377:     "virtio-net-pci",
1.1.1.7   root     1378:     NULL
                   1379: };
                   1380: 
1.1.1.3   root     1381: /* Initialize a PCI NIC.  */
1.1.1.10  root     1382: /* FIXME callers should check for failure, but don't */
1.1.1.9   root     1383: PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
                   1384:                         const char *default_devaddr)
1.1.1.3   root     1385: {
1.1.1.9   root     1386:     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1.1.1.10  root     1387:     PCIBus *bus;
                   1388:     int devfn;
1.1.1.7   root     1389:     PCIDevice *pci_dev;
1.1.1.9   root     1390:     DeviceState *dev;
1.1.1.7   root     1391:     int i;
                   1392: 
1.1.1.10  root     1393:     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
                   1394:     if (i < 0)
                   1395:         return NULL;
1.1.1.7   root     1396: 
1.1.1.10  root     1397:     bus = pci_get_bus_devfn(&devfn, devaddr);
                   1398:     if (!bus) {
1.1.1.13  root     1399:         error_report("Invalid PCI device address %s for device %s",
                   1400:                      devaddr, pci_nic_names[i]);
1.1.1.10  root     1401:         return NULL;
1.1.1.9   root     1402:     }
1.1.1.7   root     1403: 
1.1.1.10  root     1404:     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
                   1405:     dev = &pci_dev->qdev;
                   1406:     qdev_set_nic_properties(dev, nd);
                   1407:     if (qdev_init(dev) < 0)
                   1408:         return NULL;
                   1409:     return pci_dev;
                   1410: }
                   1411: 
                   1412: PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
                   1413:                                const char *default_devaddr)
                   1414: {
                   1415:     PCIDevice *res;
                   1416: 
                   1417:     if (qemu_show_nic_models(nd->model, pci_nic_models))
                   1418:         exit(0);
                   1419: 
                   1420:     res = pci_nic_init(nd, default_model, default_devaddr);
                   1421:     if (!res)
                   1422:         exit(1);
                   1423:     return res;
1.1.1.3   root     1424: }
                   1425: 
1.1.1.14  root     1426: /* Whether a given bus number is in range of the secondary
                   1427:  * bus of the given bridge device. */
                   1428: static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
                   1429: {
                   1430:     return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
                   1431:              PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
                   1432:         dev->config[PCI_SECONDARY_BUS] < bus_num &&
                   1433:         bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1.1.1.5   root     1434: }
                   1435: 
1.1.1.10  root     1436: PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1.1.1.7   root     1437: {
1.1.1.10  root     1438:     PCIBus *sec;
                   1439: 
1.1.1.13  root     1440:     if (!bus) {
1.1.1.10  root     1441:         return NULL;
1.1.1.13  root     1442:     }
1.1.1.7   root     1443: 
1.1.1.10  root     1444:     if (pci_bus_num(bus) == bus_num) {
                   1445:         return bus;
                   1446:     }
1.1.1.7   root     1447: 
1.1.1.14  root     1448:     /* Consider all bus numbers in range for the host pci bridge. */
                   1449:     if (bus->parent_dev &&
                   1450:         !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
                   1451:         return NULL;
                   1452:     }
                   1453: 
1.1.1.10  root     1454:     /* try child bus */
1.1.1.14  root     1455:     for (; bus; bus = sec) {
                   1456:         QLIST_FOREACH(sec, &bus->child, sibling) {
                   1457:             assert(sec->parent_dev);
                   1458:             if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
                   1459:                 return sec;
                   1460:             }
                   1461:             if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
                   1462:                 break;
1.1.1.13  root     1463:             }
1.1.1.10  root     1464:         }
                   1465:     }
                   1466: 
                   1467:     return NULL;
1.1.1.7   root     1468: }
                   1469: 
1.1.1.15  root     1470: PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1.1.1.7   root     1471: {
1.1.1.10  root     1472:     bus = pci_find_bus(bus, bus_num);
1.1.1.7   root     1473: 
                   1474:     if (!bus)
                   1475:         return NULL;
                   1476: 
1.1.1.15  root     1477:     return bus->devices[devfn];
1.1.1.7   root     1478: }
                   1479: 
1.1.1.10  root     1480: static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1.1.1.9   root     1481: {
                   1482:     PCIDevice *pci_dev = (PCIDevice *)qdev;
                   1483:     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
                   1484:     PCIBus *bus;
1.1.1.15  root     1485:     int rc;
1.1.1.14  root     1486:     bool is_default_rom;
1.1.1.10  root     1487: 
                   1488:     /* initialize cap_present for pci_is_express() and pci_config_size() */
                   1489:     if (info->is_express) {
                   1490:         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
                   1491:     }
1.1.1.9   root     1492: 
                   1493:     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1.1.1.15  root     1494:     pci_dev = do_pci_register_device(pci_dev, bus, base->name,
                   1495:                                      pci_dev->devfn, info);
1.1.1.10  root     1496:     if (pci_dev == NULL)
                   1497:         return -1;
1.1.1.14  root     1498:     if (qdev->hotplugged && info->no_hotplug) {
                   1499:         qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
                   1500:         do_pci_unregister_device(pci_dev);
                   1501:         return -1;
                   1502:     }
1.1.1.15  root     1503:     if (info->init) {
                   1504:         rc = info->init(pci_dev);
                   1505:         if (rc != 0) {
                   1506:             do_pci_unregister_device(pci_dev);
                   1507:             return rc;
                   1508:         }
1.1.1.13  root     1509:     }
1.1.1.10  root     1510: 
                   1511:     /* rom loading */
1.1.1.14  root     1512:     is_default_rom = false;
                   1513:     if (pci_dev->romfile == NULL && info->romfile != NULL) {
1.1.1.16! root     1514:         pci_dev->romfile = g_strdup(info->romfile);
1.1.1.14  root     1515:         is_default_rom = true;
                   1516:     }
                   1517:     pci_add_option_rom(pci_dev, is_default_rom);
1.1.1.10  root     1518: 
1.1.1.14  root     1519:     if (bus->hotplug) {
                   1520:         /* Let buses differentiate between hotplug and when device is
                   1521:          * enabled during qemu machine creation. */
                   1522:         rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
                   1523:                           qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
                   1524:                           PCI_COLDPLUG_ENABLED);
1.1.1.13  root     1525:         if (rc != 0) {
                   1526:             int r = pci_unregister_device(&pci_dev->qdev);
                   1527:             assert(!r);
                   1528:             return rc;
                   1529:         }
                   1530:     }
1.1.1.10  root     1531:     return 0;
                   1532: }
                   1533: 
                   1534: static int pci_unplug_device(DeviceState *qdev)
                   1535: {
                   1536:     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1.1.1.14  root     1537:     PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
1.1.1.10  root     1538: 
1.1.1.14  root     1539:     if (info->no_hotplug) {
                   1540:         qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
                   1541:         return -1;
                   1542:     }
                   1543:     return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
                   1544:                              PCI_HOTPLUG_DISABLED);
1.1.1.9   root     1545: }
                   1546: 
                   1547: void pci_qdev_register(PCIDeviceInfo *info)
                   1548: {
                   1549:     info->qdev.init = pci_qdev_init;
1.1.1.10  root     1550:     info->qdev.unplug = pci_unplug_device;
                   1551:     info->qdev.exit = pci_unregister_device;
1.1.1.9   root     1552:     info->qdev.bus_info = &pci_bus_info;
                   1553:     qdev_register(&info->qdev);
                   1554: }
                   1555: 
                   1556: void pci_qdev_register_many(PCIDeviceInfo *info)
                   1557: {
                   1558:     while (info->qdev.name) {
                   1559:         pci_qdev_register(info);
                   1560:         info++;
                   1561:     }
                   1562: }
                   1563: 
1.1.1.13  root     1564: PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
                   1565:                                     const char *name)
1.1.1.9   root     1566: {
                   1567:     DeviceState *dev;
                   1568: 
                   1569:     dev = qdev_create(&bus->qbus, name);
1.1.1.10  root     1570:     qdev_prop_set_uint32(dev, "addr", devfn);
1.1.1.13  root     1571:     qdev_prop_set_bit(dev, "multifunction", multifunction);
1.1.1.10  root     1572:     return DO_UPCAST(PCIDevice, qdev, dev);
                   1573: }
1.1.1.9   root     1574: 
1.1.1.15  root     1575: PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
                   1576:                                         bool multifunction,
                   1577:                                         const char *name)
                   1578: {
                   1579:     DeviceState *dev;
                   1580: 
                   1581:     dev = qdev_try_create(&bus->qbus, name);
                   1582:     if (!dev) {
                   1583:         return NULL;
                   1584:     }
                   1585:     qdev_prop_set_uint32(dev, "addr", devfn);
                   1586:     qdev_prop_set_bit(dev, "multifunction", multifunction);
                   1587:     return DO_UPCAST(PCIDevice, qdev, dev);
                   1588: }
                   1589: 
1.1.1.13  root     1590: PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
                   1591:                                            bool multifunction,
                   1592:                                            const char *name)
1.1.1.10  root     1593: {
1.1.1.13  root     1594:     PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1.1.1.10  root     1595:     qdev_init_nofail(&dev->qdev);
                   1596:     return dev;
1.1.1.9   root     1597: }
                   1598: 
1.1.1.13  root     1599: PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
                   1600: {
                   1601:     return pci_create_multifunction(bus, devfn, false, name);
                   1602: }
                   1603: 
                   1604: PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
                   1605: {
                   1606:     return pci_create_simple_multifunction(bus, devfn, false, name);
                   1607: }
                   1608: 
1.1.1.15  root     1609: PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name)
                   1610: {
                   1611:     return pci_try_create_multifunction(bus, devfn, false, name);
                   1612: }
                   1613: 
1.1.1.9   root     1614: static int pci_find_space(PCIDevice *pdev, uint8_t size)
                   1615: {
1.1.1.10  root     1616:     int config_size = pci_config_size(pdev);
1.1.1.9   root     1617:     int offset = PCI_CONFIG_HEADER_SIZE;
                   1618:     int i;
1.1.1.10  root     1619:     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1.1.1.9   root     1620:         if (pdev->used[i])
                   1621:             offset = i + 1;
                   1622:         else if (i - offset + 1 == size)
                   1623:             return offset;
                   1624:     return 0;
                   1625: }
                   1626: 
                   1627: static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
                   1628:                                         uint8_t *prev_p)
                   1629: {
                   1630:     uint8_t next, prev;
                   1631: 
                   1632:     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
                   1633:         return 0;
                   1634: 
                   1635:     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
                   1636:          prev = next + PCI_CAP_LIST_NEXT)
                   1637:         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
                   1638:             break;
                   1639: 
                   1640:     if (prev_p)
                   1641:         *prev_p = prev;
                   1642:     return next;
                   1643: }
                   1644: 
1.1.1.16! root     1645: static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1.1.1.10  root     1646: {
1.1.1.16! root     1647:     uint8_t next, prev, found = 0;
        !          1648: 
        !          1649:     if (!(pdev->used[offset])) {
        !          1650:         return 0;
        !          1651:     }
        !          1652: 
        !          1653:     assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
        !          1654: 
        !          1655:     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
        !          1656:          prev = next + PCI_CAP_LIST_NEXT) {
        !          1657:         if (next <= offset && next > found) {
        !          1658:             found = next;
        !          1659:         }
        !          1660:     }
        !          1661:     return found;
1.1.1.10  root     1662: }
                   1663: 
1.1.1.14  root     1664: /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
                   1665:    This is needed for an option rom which is used for more than one device. */
                   1666: static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
                   1667: {
                   1668:     uint16_t vendor_id;
                   1669:     uint16_t device_id;
                   1670:     uint16_t rom_vendor_id;
                   1671:     uint16_t rom_device_id;
                   1672:     uint16_t rom_magic;
                   1673:     uint16_t pcir_offset;
                   1674:     uint8_t checksum;
                   1675: 
                   1676:     /* Words in rom data are little endian (like in PCI configuration),
                   1677:        so they can be read / written with pci_get_word / pci_set_word. */
                   1678: 
                   1679:     /* Only a valid rom will be patched. */
                   1680:     rom_magic = pci_get_word(ptr);
                   1681:     if (rom_magic != 0xaa55) {
                   1682:         PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
                   1683:         return;
                   1684:     }
                   1685:     pcir_offset = pci_get_word(ptr + 0x18);
                   1686:     if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
                   1687:         PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
                   1688:         return;
                   1689:     }
                   1690: 
                   1691:     vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
                   1692:     device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
                   1693:     rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
                   1694:     rom_device_id = pci_get_word(ptr + pcir_offset + 6);
                   1695: 
                   1696:     PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
                   1697:                 vendor_id, device_id, rom_vendor_id, rom_device_id);
                   1698: 
                   1699:     checksum = ptr[6];
                   1700: 
                   1701:     if (vendor_id != rom_vendor_id) {
                   1702:         /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
                   1703:         checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
                   1704:         checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
                   1705:         PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
                   1706:         ptr[6] = checksum;
                   1707:         pci_set_word(ptr + pcir_offset + 4, vendor_id);
                   1708:     }
                   1709: 
                   1710:     if (device_id != rom_device_id) {
                   1711:         /* Patch device id and checksum (at offset 6 for etherboot roms). */
                   1712:         checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
                   1713:         checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
                   1714:         PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
                   1715:         ptr[6] = checksum;
                   1716:         pci_set_word(ptr + pcir_offset + 6, device_id);
                   1717:     }
                   1718: }
                   1719: 
1.1.1.10  root     1720: /* Add an option rom for the device */
1.1.1.14  root     1721: static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1.1.1.10  root     1722: {
                   1723:     int size;
                   1724:     char *path;
                   1725:     void *ptr;
1.1.1.13  root     1726:     char name[32];
1.1.1.10  root     1727: 
                   1728:     if (!pdev->romfile)
                   1729:         return 0;
                   1730:     if (strlen(pdev->romfile) == 0)
                   1731:         return 0;
                   1732: 
1.1.1.11  root     1733:     if (!pdev->rom_bar) {
                   1734:         /*
                   1735:          * Load rom via fw_cfg instead of creating a rom bar,
                   1736:          * for 0.11 compatibility.
                   1737:          */
                   1738:         int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
                   1739:         if (class == 0x0300) {
                   1740:             rom_add_vga(pdev->romfile);
                   1741:         } else {
1.1.1.14  root     1742:             rom_add_option(pdev->romfile, -1);
1.1.1.11  root     1743:         }
                   1744:         return 0;
                   1745:     }
                   1746: 
1.1.1.10  root     1747:     path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
                   1748:     if (path == NULL) {
1.1.1.16! root     1749:         path = g_strdup(pdev->romfile);
1.1.1.10  root     1750:     }
                   1751: 
                   1752:     size = get_image_size(path);
                   1753:     if (size < 0) {
1.1.1.13  root     1754:         error_report("%s: failed to find romfile \"%s\"",
                   1755:                      __FUNCTION__, pdev->romfile);
1.1.1.16! root     1756:         g_free(path);
1.1.1.10  root     1757:         return -1;
                   1758:     }
                   1759:     if (size & (size - 1)) {
                   1760:         size = 1 << qemu_fls(size);
                   1761:     }
                   1762: 
1.1.1.13  root     1763:     if (pdev->qdev.info->vmsd)
                   1764:         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
                   1765:     else
                   1766:         snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1.1.1.16! root     1767:     pdev->has_rom = true;
        !          1768:     memory_region_init_ram(&pdev->rom, &pdev->qdev, name, size);
        !          1769:     ptr = memory_region_get_ram_ptr(&pdev->rom);
1.1.1.10  root     1770:     load_image(path, ptr);
1.1.1.16! root     1771:     g_free(path);
1.1.1.10  root     1772: 
1.1.1.14  root     1773:     if (is_default_rom) {
                   1774:         /* Only the default rom images will be patched (if needed). */
                   1775:         pci_patch_ids(pdev, ptr, size);
                   1776:     }
                   1777: 
1.1.1.15  root     1778:     qemu_put_ram_ptr(ptr);
                   1779: 
1.1.1.16! root     1780:     pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1.1.1.10  root     1781: 
                   1782:     return 0;
                   1783: }
                   1784: 
1.1.1.13  root     1785: static void pci_del_option_rom(PCIDevice *pdev)
                   1786: {
1.1.1.16! root     1787:     if (!pdev->has_rom)
1.1.1.13  root     1788:         return;
                   1789: 
1.1.1.16! root     1790:     memory_region_destroy(&pdev->rom);
        !          1791:     pdev->has_rom = false;
1.1.1.13  root     1792: }
                   1793: 
1.1.1.14  root     1794: /*
                   1795:  * if !offset
                   1796:  * Reserve space and add capability to the linked list in pci config space
                   1797:  *
                   1798:  * if offset = 0,
                   1799:  * Find and reserve space and add capability to the linked list
                   1800:  * in pci config space */
                   1801: int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
                   1802:                        uint8_t offset, uint8_t size)
1.1.1.9   root     1803: {
1.1.1.14  root     1804:     uint8_t *config;
1.1.1.16! root     1805:     int i, overlapping_cap;
        !          1806: 
1.1.1.14  root     1807:     if (!offset) {
                   1808:         offset = pci_find_space(pdev, size);
                   1809:         if (!offset) {
                   1810:             return -ENOSPC;
                   1811:         }
1.1.1.16! root     1812:     } else {
        !          1813:         /* Verify that capabilities don't overlap.  Note: device assignment
        !          1814:          * depends on this check to verify that the device is not broken.
        !          1815:          * Should never trigger for emulated devices, but it's helpful
        !          1816:          * for debugging these. */
        !          1817:         for (i = offset; i < offset + size; i++) {
        !          1818:             overlapping_cap = pci_find_capability_at_offset(pdev, i);
        !          1819:             if (overlapping_cap) {
        !          1820:                 fprintf(stderr, "ERROR: %04x:%02x:%02x.%x "
        !          1821:                         "Attempt to add PCI capability %x at offset "
        !          1822:                         "%x overlaps existing capability %x at offset %x\n",
        !          1823:                         pci_find_domain(pdev->bus), pci_bus_num(pdev->bus),
        !          1824:                         PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
        !          1825:                         cap_id, offset, overlapping_cap, i);
        !          1826:                 return -EINVAL;
        !          1827:             }
        !          1828:         }
1.1.1.14  root     1829:     }
                   1830: 
                   1831:     config = pdev->config + offset;
1.1.1.9   root     1832:     config[PCI_CAP_LIST_ID] = cap_id;
                   1833:     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
                   1834:     pdev->config[PCI_CAPABILITY_LIST] = offset;
                   1835:     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
                   1836:     memset(pdev->used + offset, 0xFF, size);
                   1837:     /* Make capability read-only by default */
                   1838:     memset(pdev->wmask + offset, 0, size);
                   1839:     /* Check capability by default */
                   1840:     memset(pdev->cmask + offset, 0xFF, size);
                   1841:     return offset;
                   1842: }
                   1843: 
                   1844: /* Unlink capability from the pci config space. */
                   1845: void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
                   1846: {
                   1847:     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
                   1848:     if (!offset)
                   1849:         return;
                   1850:     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1.1.1.15  root     1851:     /* Make capability writable again */
1.1.1.9   root     1852:     memset(pdev->wmask + offset, 0xff, size);
1.1.1.14  root     1853:     memset(pdev->w1cmask + offset, 0, size);
1.1.1.9   root     1854:     /* Clear cmask as device-specific registers can't be checked */
                   1855:     memset(pdev->cmask + offset, 0, size);
                   1856:     memset(pdev->used + offset, 0, size);
                   1857: 
                   1858:     if (!pdev->config[PCI_CAPABILITY_LIST])
                   1859:         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
                   1860: }
                   1861: 
                   1862: uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
                   1863: {
                   1864:     return pci_find_capability_list(pdev, cap_id, NULL);
                   1865: }
                   1866: 
                   1867: static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
                   1868: {
                   1869:     PCIDevice *d = (PCIDevice *)dev;
                   1870:     const pci_class_desc *desc;
                   1871:     char ctxt[64];
                   1872:     PCIIORegion *r;
                   1873:     int i, class;
                   1874: 
1.1.1.10  root     1875:     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1.1.1.9   root     1876:     desc = pci_class_descriptions;
                   1877:     while (desc->desc && class != desc->class)
                   1878:         desc++;
                   1879:     if (desc->desc) {
                   1880:         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
                   1881:     } else {
                   1882:         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
                   1883:     }
                   1884: 
                   1885:     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
                   1886:                    "pci id %04x:%04x (sub %04x:%04x)\n",
1.1.1.14  root     1887:                    indent, "", ctxt, pci_bus_num(d->bus),
1.1.1.10  root     1888:                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
                   1889:                    pci_get_word(d->config + PCI_VENDOR_ID),
                   1890:                    pci_get_word(d->config + PCI_DEVICE_ID),
                   1891:                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
                   1892:                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1.1.1.9   root     1893:     for (i = 0; i < PCI_NUM_REGIONS; i++) {
                   1894:         r = &d->io_regions[i];
                   1895:         if (!r->size)
                   1896:             continue;
1.1.1.10  root     1897:         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
                   1898:                        " [0x%"FMT_PCIBUS"]\n",
                   1899:                        indent, "",
                   1900:                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1.1.1.9   root     1901:                        r->addr, r->addr + r->size - 1);
                   1902:     }
                   1903: }
1.1.1.10  root     1904: 
1.1.1.14  root     1905: static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
1.1.1.13  root     1906: {
                   1907:     PCIDevice *d = (PCIDevice *)dev;
1.1.1.14  root     1908:     const char *name = NULL;
                   1909:     const pci_class_desc *desc =  pci_class_descriptions;
                   1910:     int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
                   1911: 
                   1912:     while (desc->desc &&
                   1913:           (class & ~desc->fw_ign_bits) !=
                   1914:           (desc->class & ~desc->fw_ign_bits)) {
                   1915:         desc++;
                   1916:     }
                   1917: 
                   1918:     if (desc->desc) {
                   1919:         name = desc->fw_name;
                   1920:     }
                   1921: 
                   1922:     if (name) {
                   1923:         pstrcpy(buf, len, name);
                   1924:     } else {
                   1925:         snprintf(buf, len, "pci%04x,%04x",
                   1926:                  pci_get_word(d->config + PCI_VENDOR_ID),
                   1927:                  pci_get_word(d->config + PCI_DEVICE_ID));
                   1928:     }
1.1.1.13  root     1929: 
1.1.1.14  root     1930:     return buf;
                   1931: }
                   1932: 
                   1933: static char *pcibus_get_fw_dev_path(DeviceState *dev)
                   1934: {
                   1935:     PCIDevice *d = (PCIDevice *)dev;
                   1936:     char path[50], name[33];
                   1937:     int off;
1.1.1.13  root     1938: 
1.1.1.14  root     1939:     off = snprintf(path, sizeof(path), "%s@%x",
                   1940:                    pci_dev_fw_name(dev, name, sizeof name),
                   1941:                    PCI_SLOT(d->devfn));
                   1942:     if (PCI_FUNC(d->devfn))
                   1943:         snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
1.1.1.13  root     1944:     return strdup(path);
                   1945: }
                   1946: 
1.1.1.14  root     1947: static char *pcibus_get_dev_path(DeviceState *dev)
                   1948: {
                   1949:     PCIDevice *d = container_of(dev, PCIDevice, qdev);
                   1950:     PCIDevice *t;
                   1951:     int slot_depth;
                   1952:     /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
                   1953:      * 00 is added here to make this format compatible with
                   1954:      * domain:Bus:Slot.Func for systems without nested PCI bridges.
                   1955:      * Slot.Function list specifies the slot and function numbers for all
                   1956:      * devices on the path from root to the specific device. */
                   1957:     char domain[] = "DDDD:00";
                   1958:     char slot[] = ":SS.F";
                   1959:     int domain_len = sizeof domain - 1 /* For '\0' */;
                   1960:     int slot_len = sizeof slot - 1 /* For '\0' */;
                   1961:     int path_len;
                   1962:     char *path, *p;
                   1963:     int s;
                   1964: 
                   1965:     /* Calculate # of slots on path between device and root. */;
                   1966:     slot_depth = 0;
                   1967:     for (t = d; t; t = t->bus->parent_dev) {
                   1968:         ++slot_depth;
                   1969:     }
                   1970: 
                   1971:     path_len = domain_len + slot_len * slot_depth;
                   1972: 
                   1973:     /* Allocate memory, fill in the terminating null byte. */
1.1.1.16! root     1974:     path = g_malloc(path_len + 1 /* For '\0' */);
1.1.1.14  root     1975:     path[path_len] = '\0';
                   1976: 
                   1977:     /* First field is the domain. */
                   1978:     s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
                   1979:     assert(s == domain_len);
                   1980:     memcpy(path, domain, domain_len);
                   1981: 
                   1982:     /* Fill in slot numbers. We walk up from device to root, so need to print
                   1983:      * them in the reverse order, last to first. */
                   1984:     p = path + path_len;
                   1985:     for (t = d; t; t = t->bus->parent_dev) {
                   1986:         p -= slot_len;
                   1987:         s = snprintf(slot, sizeof slot, ":%02x.%x",
                   1988:                      PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
                   1989:         assert(s == slot_len);
                   1990:         memcpy(p, slot, slot_len);
                   1991:     }
                   1992: 
                   1993:     return path;
                   1994: }
                   1995: 
                   1996: static int pci_qdev_find_recursive(PCIBus *bus,
                   1997:                                    const char *id, PCIDevice **pdev)
                   1998: {
                   1999:     DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
                   2000:     if (!qdev) {
                   2001:         return -ENODEV;
                   2002:     }
                   2003: 
                   2004:     /* roughly check if given qdev is pci device */
                   2005:     if (qdev->info->init == &pci_qdev_init &&
                   2006:         qdev->parent_bus->info == &pci_bus_info) {
                   2007:         *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
                   2008:         return 0;
1.1.1.10  root     2009:     }
1.1.1.14  root     2010:     return -EINVAL;
                   2011: }
1.1.1.10  root     2012: 
1.1.1.14  root     2013: int pci_qdev_find_device(const char *id, PCIDevice **pdev)
1.1.1.10  root     2014: {
1.1.1.14  root     2015:     struct PCIHostBus *host;
                   2016:     int rc = -ENODEV;
                   2017: 
                   2018:     QLIST_FOREACH(host, &host_buses, next) {
                   2019:         int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
                   2020:         if (!tmp) {
                   2021:             rc = 0;
                   2022:             break;
                   2023:         }
                   2024:         if (tmp != -ENODEV) {
                   2025:             rc = tmp;
                   2026:         }
                   2027:     }
1.1.1.10  root     2028: 
1.1.1.14  root     2029:     return rc;
                   2030: }
1.1.1.16! root     2031: 
        !          2032: MemoryRegion *pci_address_space(PCIDevice *dev)
        !          2033: {
        !          2034:     return dev->bus->address_space_mem;
        !          2035: }
        !          2036: 
        !          2037: MemoryRegion *pci_address_space_io(PCIDevice *dev)
        !          2038: {
        !          2039:     return dev->bus->address_space_io;
        !          2040: }

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