Diff for /qemu/hw/pci_host.h between versions 1.1 and 1.1.1.6

version 1.1, 2018/04/24 16:43:36 version 1.1.1.6, 2018/04/24 18:29:25
Line 2 Line 2
  * QEMU Common PCI Host bridge configuration data space access routines.   * QEMU Common PCI Host bridge configuration data space access routines.
  *   *
  * Copyright (c) 2006 Fabrice Bellard   * Copyright (c) 2006 Fabrice Bellard
  *    *
  * Permission is hereby granted, free of charge, to any person obtaining a copy   * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal   * of this software and associated documentation files (the "Software"), to deal
  * in the Software without restriction, including without limitation the rights   * in the Software without restriction, including without limitation the rights
Line 25 Line 25
 /* Worker routines for a PCI host controller that uses an {address,data}  /* Worker routines for a PCI host controller that uses an {address,data}
    register pair to access PCI configuration space.  */     register pair to access PCI configuration space.  */
   
 typedef struct {  #ifndef PCI_HOST_H
   #define PCI_HOST_H
   
   #include "sysbus.h"
   #include "rwhandler.h"
   
   struct PCIHostState {
       SysBusDevice busdev;
       ReadWriteHandler conf_noswap_handler;
       ReadWriteHandler conf_handler;
       ReadWriteHandler data_noswap_handler;
       ReadWriteHandler data_handler;
     uint32_t config_reg;      uint32_t config_reg;
     PCIBus *bus;      PCIBus *bus;
 } PCIHostState;  };
   
   void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len);
   uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);
   
   /* for mmio */
   int pci_host_conf_register_mmio(PCIHostState *s, int swap);
   int pci_host_data_register_mmio(PCIHostState *s, int swap);
   
 static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val)  /* for ioio */
 {  void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s);
     PCIHostState *s = opaque;  void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s);
     if (s->config_reg & (1u << 31))  
         pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1);  
 }  
   
 static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val)  
 {  
     PCIHostState *s = opaque;  
 #ifdef TARGET_WORDS_BIGENDIAN  
     val = bswap16(val);  
 #endif  
     if (s->config_reg & (1u << 31))  
         pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2);  
 }  
   
 static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val)  
 {  
     PCIHostState *s = opaque;  
 #ifdef TARGET_WORDS_BIGENDIAN  
     val = bswap32(val);  
 #endif  
     if (s->config_reg & (1u << 31))  
         pci_data_write(s->bus, s->config_reg, val, 4);  
 }  
   
 static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr)  
 {  
     PCIHostState *s = opaque;  
     if (!(s->config_reg & (1 << 31)))  
         return 0xff;  
     return pci_data_read(s->bus, s->config_reg | (addr & 3), 1);  
 }  
   
 static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr)  
 {  
     PCIHostState *s = opaque;  
     uint32_t val;  
     if (!(s->config_reg & (1 << 31)))  
         return 0xffff;  
     val = pci_data_read(s->bus, s->config_reg | (addr & 3), 2);  
 #ifdef TARGET_WORDS_BIGENDIAN  
     val = bswap16(val);  
 #endif  
     return val;  
 }  
   
 static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr)  
 {  
     PCIHostState *s = opaque;  
     uint32_t val;  
     if (!(s->config_reg & (1 << 31)))  
         return 0xffffffff;  
     val = pci_data_read(s->bus, s->config_reg | (addr & 3), 4);  
 #ifdef TARGET_WORDS_BIGENDIAN  
     val = bswap32(val);  
 #endif  
     return val;  
 }  
   
   #endif /* PCI_HOST_H */

Removed from v.1.1  
changed lines
  Added in v.1.1.1.6


unix.superglobalmegacorp.com