File:  [Qemu by Fabrice Bellard] / qemu / hw / pci_host.h
Revision 1.1.1.3 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 16:53:17 2018 UTC (2 years, 4 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu0105, qemu0104, qemu0103, qemu0102, qemu0101, qemu0100, HEAD
qemu 0.10.0

    1: /*
    2:  * QEMU Common PCI Host bridge configuration data space access routines.
    3:  *
    4:  * Copyright (c) 2006 Fabrice Bellard
    5:  *
    6:  * Permission is hereby granted, free of charge, to any person obtaining a copy
    7:  * of this software and associated documentation files (the "Software"), to deal
    8:  * in the Software without restriction, including without limitation the rights
    9:  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   10:  * copies of the Software, and to permit persons to whom the Software is
   11:  * furnished to do so, subject to the following conditions:
   12:  *
   13:  * The above copyright notice and this permission notice shall be included in
   14:  * all copies or substantial portions of the Software.
   15:  *
   16:  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   17:  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   18:  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
   19:  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   20:  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   21:  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   22:  * THE SOFTWARE.
   23:  */
   24: 
   25: /* Worker routines for a PCI host controller that uses an {address,data}
   26:    register pair to access PCI configuration space.  */
   27: 
   28: /* debug PCI */
   29: //#define DEBUG_PCI
   30: 
   31: #ifdef DEBUG_PCI
   32: #define PCI_DPRINTF(fmt, args...) \
   33: do { printf("pci_host_data: " fmt , ##args); } while (0)
   34: #else
   35: #define PCI_DPRINTF(fmt, args...)
   36: #endif
   37: 
   38: typedef struct {
   39:     uint32_t config_reg;
   40:     PCIBus *bus;
   41: } PCIHostState;
   42: 
   43: static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val)
   44: {
   45:     PCIHostState *s = opaque;
   46: 
   47:     PCI_DPRINTF("writeb addr " TARGET_FMT_plx " val %x\n",
   48:                 (target_phys_addr_t)addr, val);
   49:     if (s->config_reg & (1u << 31))
   50:         pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1);
   51: }
   52: 
   53: static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val)
   54: {
   55:     PCIHostState *s = opaque;
   56: #ifdef TARGET_WORDS_BIGENDIAN
   57:     val = bswap16(val);
   58: #endif
   59:     PCI_DPRINTF("writew addr " TARGET_FMT_plx " val %x\n",
   60:                 (target_phys_addr_t)addr, val);
   61:     if (s->config_reg & (1u << 31))
   62:         pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2);
   63: }
   64: 
   65: static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val)
   66: {
   67:     PCIHostState *s = opaque;
   68: #ifdef TARGET_WORDS_BIGENDIAN
   69:     val = bswap32(val);
   70: #endif
   71:     PCI_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n",
   72:                 (target_phys_addr_t)addr, val);
   73:     if (s->config_reg & (1u << 31))
   74:         pci_data_write(s->bus, s->config_reg, val, 4);
   75: }
   76: 
   77: static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr)
   78: {
   79:     PCIHostState *s = opaque;
   80:     uint32_t val;
   81: 
   82:     if (!(s->config_reg & (1 << 31)))
   83:         return 0xff;
   84:     val = pci_data_read(s->bus, s->config_reg | (addr & 3), 1);
   85:     PCI_DPRINTF("readb addr " TARGET_FMT_plx " val %x\n",
   86:                 (target_phys_addr_t)addr, val);
   87:     return val;
   88: }
   89: 
   90: static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr)
   91: {
   92:     PCIHostState *s = opaque;
   93:     uint32_t val;
   94:     if (!(s->config_reg & (1 << 31)))
   95:         return 0xffff;
   96:     val = pci_data_read(s->bus, s->config_reg | (addr & 3), 2);
   97:     PCI_DPRINTF("readw addr " TARGET_FMT_plx " val %x\n",
   98:                 (target_phys_addr_t)addr, val);
   99: #ifdef TARGET_WORDS_BIGENDIAN
  100:     val = bswap16(val);
  101: #endif
  102:     return val;
  103: }
  104: 
  105: static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr)
  106: {
  107:     PCIHostState *s = opaque;
  108:     uint32_t val;
  109:     if (!(s->config_reg & (1 << 31)))
  110:         return 0xffffffff;
  111:     val = pci_data_read(s->bus, s->config_reg | (addr & 3), 4);
  112:     PCI_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n",
  113:                 (target_phys_addr_t)addr, val);
  114: #ifdef TARGET_WORDS_BIGENDIAN
  115:     val = bswap32(val);
  116: #endif
  117:     return val;
  118: }

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