File:  [Qemu by Fabrice Bellard] / qemu / hw / pci_host.h
Revision 1.1.1.5 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 17:38:47 2018 UTC (2 years, 6 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu0125, qemu0124, qemu0123, qemu0122, qemu0121, qemu0120, HEAD
qemu 0.12.0

    1: /*
    2:  * QEMU Common PCI Host bridge configuration data space access routines.
    3:  *
    4:  * Copyright (c) 2006 Fabrice Bellard
    5:  *
    6:  * Permission is hereby granted, free of charge, to any person obtaining a copy
    7:  * of this software and associated documentation files (the "Software"), to deal
    8:  * in the Software without restriction, including without limitation the rights
    9:  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   10:  * copies of the Software, and to permit persons to whom the Software is
   11:  * furnished to do so, subject to the following conditions:
   12:  *
   13:  * The above copyright notice and this permission notice shall be included in
   14:  * all copies or substantial portions of the Software.
   15:  *
   16:  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
   17:  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   18:  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
   19:  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   20:  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   21:  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   22:  * THE SOFTWARE.
   23:  */
   24: 
   25: /* Worker routines for a PCI host controller that uses an {address,data}
   26:    register pair to access PCI configuration space.  */
   27: 
   28: #ifndef PCI_HOST_H
   29: #define PCI_HOST_H
   30: 
   31: #include "sysbus.h"
   32: 
   33: struct PCIHostState {
   34:     SysBusDevice busdev;
   35:     uint32_t config_reg;
   36:     PCIBus *bus;
   37: };
   38: 
   39: void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len);
   40: uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);
   41: 
   42: /* for mmio */
   43: int pci_host_conf_register_mmio(PCIHostState *s);
   44: int pci_host_conf_register_mmio_noswap(PCIHostState *s);
   45: int pci_host_data_register_mmio(PCIHostState *s);
   46: 
   47: /* for ioio */
   48: void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s);
   49: void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s);
   50: 
   51: #endif /* PCI_HOST_H */

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