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1.1 root 1: /*
2: * pcie_host.c
3: * utility functions for pci express host bridge.
4: *
5: * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
6: * VA Linux Systems Japan K.K.
7: *
8: * This program is free software; you can redistribute it and/or modify
9: * it under the terms of the GNU General Public License as published by
10: * the Free Software Foundation; either version 2 of the License, or
11: * (at your option) any later version.
12:
13: * This program is distributed in the hope that it will be useful,
14: * but WITHOUT ANY WARRANTY; without even the implied warranty of
15: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: * GNU General Public License for more details.
17:
18: * You should have received a copy of the GNU General Public License along
1.1.1.2 root 19: * with this program; if not, see <http://www.gnu.org/licenses/>.
1.1 root 20: */
21:
22: #include "hw.h"
23: #include "pci.h"
24: #include "pcie_host.h"
25:
26: /*
27: * PCI express mmcfig address
28: * bit 20 - 28: bus number
29: * bit 15 - 19: device number
30: * bit 12 - 14: function number
31: * bit 0 - 11: offset in configuration space of a given device
32: */
33: #define PCIE_MMCFG_SIZE_MAX (1ULL << 28)
34: #define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
35: #define PCIE_MMCFG_BUS_BIT 20
36: #define PCIE_MMCFG_BUS_MASK 0x1ff
37: #define PCIE_MMCFG_DEVFN_BIT 12
38: #define PCIE_MMCFG_DEVFN_MASK 0xff
39: #define PCIE_MMCFG_CONFOFFSET_MASK 0xfff
40: #define PCIE_MMCFG_BUS(addr) (((addr) >> PCIE_MMCFG_BUS_BIT) & \
41: PCIE_MMCFG_BUS_MASK)
42: #define PCIE_MMCFG_DEVFN(addr) (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \
43: PCIE_MMCFG_DEVFN_MASK)
44: #define PCIE_MMCFG_CONFOFFSET(addr) ((addr) & PCIE_MMCFG_CONFOFFSET_MASK)
45:
46:
47: /* a helper function to get a PCIDevice for a given mmconfig address */
48: static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
49: uint32_t mmcfg_addr)
50: {
51: return pci_find_device(s, PCIE_MMCFG_BUS(mmcfg_addr),
1.1.1.4 ! root 52: PCIE_MMCFG_DEVFN(mmcfg_addr));
1.1 root 53: }
54:
55: static void pcie_mmcfg_data_write(PCIBus *s,
56: uint32_t mmcfg_addr, uint32_t val, int len)
57: {
58: PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
59:
60: if (!pci_dev)
61: return;
62:
63: pci_dev->config_write(pci_dev,
64: PCIE_MMCFG_CONFOFFSET(mmcfg_addr), val, len);
65: }
66:
67: static uint32_t pcie_mmcfg_data_read(PCIBus *s, uint32_t addr, int len)
68: {
69: PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, addr);
70:
71: assert(len == 1 || len == 2 || len == 4);
72: if (!pci_dev) {
73: return ~0x0;
74: }
75: return pci_dev->config_read(pci_dev, PCIE_MMCFG_CONFOFFSET(addr), len);
76: }
77:
78: static void pcie_mmcfg_data_writeb(void *opaque,
79: target_phys_addr_t addr, uint32_t value)
80: {
81: PCIExpressHost *e = opaque;
82: pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 1);
83: }
84:
85: static void pcie_mmcfg_data_writew(void *opaque,
86: target_phys_addr_t addr, uint32_t value)
87: {
88: PCIExpressHost *e = opaque;
89: pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 2);
90: }
91:
92: static void pcie_mmcfg_data_writel(void *opaque,
93: target_phys_addr_t addr, uint32_t value)
94: {
95: PCIExpressHost *e = opaque;
96: pcie_mmcfg_data_write(e->pci.bus, addr - e->base_addr, value, 4);
97: }
98:
99: static uint32_t pcie_mmcfg_data_readb(void *opaque, target_phys_addr_t addr)
100: {
101: PCIExpressHost *e = opaque;
102: return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 1);
103: }
104:
105: static uint32_t pcie_mmcfg_data_readw(void *opaque, target_phys_addr_t addr)
106: {
107: PCIExpressHost *e = opaque;
108: return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 2);
109: }
110:
111: static uint32_t pcie_mmcfg_data_readl(void *opaque, target_phys_addr_t addr)
112: {
113: PCIExpressHost *e = opaque;
114: return pcie_mmcfg_data_read(e->pci.bus, addr - e->base_addr, 4);
115: }
116:
117:
118: static CPUWriteMemoryFunc * const pcie_mmcfg_write[] =
119: {
120: pcie_mmcfg_data_writeb,
121: pcie_mmcfg_data_writew,
122: pcie_mmcfg_data_writel,
123: };
124:
125: static CPUReadMemoryFunc * const pcie_mmcfg_read[] =
126: {
127: pcie_mmcfg_data_readb,
128: pcie_mmcfg_data_readw,
129: pcie_mmcfg_data_readl,
130: };
131:
132: /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
133: #define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
134:
135: int pcie_host_init(PCIExpressHost *e)
136: {
137: e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
138: e->mmio_index =
1.1.1.3 root 139: cpu_register_io_memory(pcie_mmcfg_read, pcie_mmcfg_write, e,
140: DEVICE_NATIVE_ENDIAN);
1.1 root 141: if (e->mmio_index < 0) {
142: return -1;
143: }
144:
145: return 0;
146: }
147:
148: void pcie_host_mmcfg_unmap(PCIExpressHost *e)
149: {
150: if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
151: cpu_register_physical_memory(e->base_addr, e->size, IO_MEM_UNASSIGNED);
152: e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
153: }
154: }
155:
156: void pcie_host_mmcfg_map(PCIExpressHost *e,
157: target_phys_addr_t addr, uint32_t size)
158: {
159: assert(!(size & (size - 1))); /* power of 2 */
160: assert(size >= PCIE_MMCFG_SIZE_MIN);
161: assert(size <= PCIE_MMCFG_SIZE_MAX);
162:
163: e->base_addr = addr;
164: e->size = size;
165: cpu_register_physical_memory(e->base_addr, e->size, e->mmio_index);
166: }
167:
168: void pcie_host_mmcfg_update(PCIExpressHost *e,
169: int enable,
170: target_phys_addr_t addr, uint32_t size)
171: {
172: pcie_host_mmcfg_unmap(e);
173: if (enable) {
174: pcie_host_mmcfg_map(e, addr, size);
175: }
176: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.