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1.1 root 1: /*
2: * QEMU AMD PC-Net II (Am79C970A) emulation
1.1.1.3 root 3: *
1.1 root 4: * Copyright (c) 2004 Antony T Curtis
1.1.1.3 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.3 root 24:
1.1 root 25: /* This software was written to be compatible with the specification:
26: * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
27: * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
28: */
1.1.1.3 root 29:
1.1.1.2 root 30: /*
31: * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
32: * produced as NCR89C100. See
33: * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
34: * and
35: * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
36: */
37:
1.1.1.6 root 38: #include "sysbus.h"
1.1.1.3 root 39: #include "pci.h"
40: #include "net.h"
41: #include "qemu-timer.h"
1.1.1.4 root 42: #include "qemu_socket.h"
1.1 root 43:
44: //#define PCNET_DEBUG
45: //#define PCNET_DEBUG_IO
46: //#define PCNET_DEBUG_BCR
47: //#define PCNET_DEBUG_CSR
48: //#define PCNET_DEBUG_RMD
49: //#define PCNET_DEBUG_TMD
50: //#define PCNET_DEBUG_MATCH
51:
52:
53: #define PCNET_IOPORT_SIZE 0x20
54: #define PCNET_PNPMMIO_SIZE 0x20
55:
1.1.1.4 root 56: #define PCNET_LOOPTEST_CRC 1
57: #define PCNET_LOOPTEST_NOCRC 2
58:
1.1 root 59:
60: typedef struct PCNetState_st PCNetState;
61:
62: struct PCNetState_st {
1.1.1.2 root 63: PCIDevice *pci_dev;
1.1 root 64: VLANClientState *vc;
1.1.1.6 root 65: uint8_t macaddr[6];
1.1 root 66: QEMUTimer *poll_timer;
1.1.1.6 root 67: int rap, isr, lnkst;
1.1.1.2 root 68: uint32_t rdra, tdra;
1.1 root 69: uint8_t prom[16];
70: uint16_t csr[128];
71: uint16_t bcr[32];
72: uint64_t timer;
1.1.1.6 root 73: int mmio_index, xmit_pos, recv_pos;
1.1 root 74: uint8_t buffer[4096];
75: int tx_busy;
1.1.1.3 root 76: qemu_irq irq;
1.1.1.2 root 77: void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr,
78: uint8_t *buf, int len, int do_bswap);
79: void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
80: uint8_t *buf, int len, int do_bswap);
81: void *dma_opaque;
1.1.1.4 root 82: int looptest;
1.1 root 83: };
84:
1.1.1.6 root 85: typedef struct {
86: PCIDevice pci_dev;
87: PCNetState state;
88: } PCIPCNetState;
89:
90: typedef struct {
91: SysBusDevice busdev;
92: PCNetState state;
93: } SysBusPCNetState;
94:
1.1 root 95: struct qemu_ether_header {
96: uint8_t ether_dhost[6];
97: uint8_t ether_shost[6];
98: uint16_t ether_type;
99: };
100:
101: /* BUS CONFIGURATION REGISTERS */
102: #define BCR_MSRDA 0
103: #define BCR_MSWRA 1
104: #define BCR_MC 2
105: #define BCR_LNKST 4
106: #define BCR_LED1 5
107: #define BCR_LED2 6
108: #define BCR_LED3 7
109: #define BCR_FDC 9
110: #define BCR_BSBC 18
111: #define BCR_EECAS 19
112: #define BCR_SWS 20
113: #define BCR_PLAT 22
114:
115: #define BCR_DWIO(S) !!((S)->bcr[BCR_BSBC] & 0x0080)
116: #define BCR_SSIZE32(S) !!((S)->bcr[BCR_SWS ] & 0x0100)
117: #define BCR_SWSTYLE(S) ((S)->bcr[BCR_SWS ] & 0x00FF)
118:
119: #define CSR_INIT(S) !!(((S)->csr[0])&0x0001)
120: #define CSR_STRT(S) !!(((S)->csr[0])&0x0002)
121: #define CSR_STOP(S) !!(((S)->csr[0])&0x0004)
122: #define CSR_TDMD(S) !!(((S)->csr[0])&0x0008)
123: #define CSR_TXON(S) !!(((S)->csr[0])&0x0010)
124: #define CSR_RXON(S) !!(((S)->csr[0])&0x0020)
125: #define CSR_INEA(S) !!(((S)->csr[0])&0x0040)
1.1.1.2 root 126: #define CSR_BSWP(S) !!(((S)->csr[3])&0x0004)
1.1 root 127: #define CSR_LAPPEN(S) !!(((S)->csr[3])&0x0020)
128: #define CSR_DXSUFLO(S) !!(((S)->csr[3])&0x0040)
129: #define CSR_ASTRP_RCV(S) !!(((S)->csr[4])&0x0800)
130: #define CSR_DPOLL(S) !!(((S)->csr[4])&0x1000)
131: #define CSR_SPND(S) !!(((S)->csr[5])&0x0001)
132: #define CSR_LTINTEN(S) !!(((S)->csr[5])&0x4000)
133: #define CSR_TOKINTD(S) !!(((S)->csr[5])&0x8000)
134: #define CSR_DRX(S) !!(((S)->csr[15])&0x0001)
135: #define CSR_DTX(S) !!(((S)->csr[15])&0x0002)
136: #define CSR_LOOP(S) !!(((S)->csr[15])&0x0004)
1.1.1.4 root 137: #define CSR_DXMTFCS(S) !!(((S)->csr[15])&0x0008)
1.1 root 138: #define CSR_DRCVPA(S) !!(((S)->csr[15])&0x2000)
139: #define CSR_DRCVBC(S) !!(((S)->csr[15])&0x4000)
140: #define CSR_PROM(S) !!(((S)->csr[15])&0x8000)
141:
142: #define CSR_CRBC(S) ((S)->csr[40])
143: #define CSR_CRST(S) ((S)->csr[41])
144: #define CSR_CXBC(S) ((S)->csr[42])
145: #define CSR_CXST(S) ((S)->csr[43])
146: #define CSR_NRBC(S) ((S)->csr[44])
147: #define CSR_NRST(S) ((S)->csr[45])
148: #define CSR_POLL(S) ((S)->csr[46])
149: #define CSR_PINT(S) ((S)->csr[47])
150: #define CSR_RCVRC(S) ((S)->csr[72])
151: #define CSR_XMTRC(S) ((S)->csr[74])
152: #define CSR_RCVRL(S) ((S)->csr[76])
153: #define CSR_XMTRL(S) ((S)->csr[78])
154: #define CSR_MISSC(S) ((S)->csr[112])
155:
156: #define CSR_IADR(S) ((S)->csr[ 1] | ((S)->csr[ 2] << 16))
157: #define CSR_CRBA(S) ((S)->csr[18] | ((S)->csr[19] << 16))
158: #define CSR_CXBA(S) ((S)->csr[20] | ((S)->csr[21] << 16))
159: #define CSR_NRBA(S) ((S)->csr[22] | ((S)->csr[23] << 16))
160: #define CSR_BADR(S) ((S)->csr[24] | ((S)->csr[25] << 16))
161: #define CSR_NRDA(S) ((S)->csr[26] | ((S)->csr[27] << 16))
162: #define CSR_CRDA(S) ((S)->csr[28] | ((S)->csr[29] << 16))
163: #define CSR_BADX(S) ((S)->csr[30] | ((S)->csr[31] << 16))
164: #define CSR_NXDA(S) ((S)->csr[32] | ((S)->csr[33] << 16))
165: #define CSR_CXDA(S) ((S)->csr[34] | ((S)->csr[35] << 16))
166: #define CSR_NNRD(S) ((S)->csr[36] | ((S)->csr[37] << 16))
167: #define CSR_NNXD(S) ((S)->csr[38] | ((S)->csr[39] << 16))
168: #define CSR_PXDA(S) ((S)->csr[60] | ((S)->csr[61] << 16))
169: #define CSR_NXBA(S) ((S)->csr[64] | ((S)->csr[65] << 16))
170:
171: #define PHYSADDR(S,A) \
172: (BCR_SSIZE32(S) ? (A) : (A) | ((0xff00 & (uint32_t)(s)->csr[2])<<16))
173:
174: struct pcnet_initblk16 {
175: uint16_t mode;
1.1.1.2 root 176: uint16_t padr[3];
177: uint16_t ladrf[4];
178: uint32_t rdra;
179: uint32_t tdra;
1.1 root 180: };
181:
182: struct pcnet_initblk32 {
183: uint16_t mode;
1.1.1.2 root 184: uint8_t rlen;
185: uint8_t tlen;
186: uint16_t padr[3];
1.1 root 187: uint16_t _res;
1.1.1.2 root 188: uint16_t ladrf[4];
1.1 root 189: uint32_t rdra;
190: uint32_t tdra;
191: };
192:
193: struct pcnet_TMD {
1.1.1.3 root 194: uint32_t tbadr;
195: int16_t length;
196: int16_t status;
197: uint32_t misc;
198: uint32_t res;
1.1 root 199: };
200:
1.1.1.3 root 201: #define TMDL_BCNT_MASK 0x0fff
202: #define TMDL_BCNT_SH 0
203: #define TMDL_ONES_MASK 0xf000
204: #define TMDL_ONES_SH 12
205:
206: #define TMDS_BPE_MASK 0x0080
207: #define TMDS_BPE_SH 7
208: #define TMDS_ENP_MASK 0x0100
209: #define TMDS_ENP_SH 8
210: #define TMDS_STP_MASK 0x0200
211: #define TMDS_STP_SH 9
212: #define TMDS_DEF_MASK 0x0400
213: #define TMDS_DEF_SH 10
214: #define TMDS_ONE_MASK 0x0800
215: #define TMDS_ONE_SH 11
216: #define TMDS_LTINT_MASK 0x1000
217: #define TMDS_LTINT_SH 12
218: #define TMDS_NOFCS_MASK 0x2000
219: #define TMDS_NOFCS_SH 13
1.1.1.4 root 220: #define TMDS_ADDFCS_MASK TMDS_NOFCS_MASK
221: #define TMDS_ADDFCS_SH TMDS_NOFCS_SH
1.1.1.3 root 222: #define TMDS_ERR_MASK 0x4000
223: #define TMDS_ERR_SH 14
224: #define TMDS_OWN_MASK 0x8000
225: #define TMDS_OWN_SH 15
226:
227: #define TMDM_TRC_MASK 0x0000000f
228: #define TMDM_TRC_SH 0
229: #define TMDM_TDR_MASK 0x03ff0000
230: #define TMDM_TDR_SH 16
231: #define TMDM_RTRY_MASK 0x04000000
232: #define TMDM_RTRY_SH 26
233: #define TMDM_LCAR_MASK 0x08000000
234: #define TMDM_LCAR_SH 27
235: #define TMDM_LCOL_MASK 0x10000000
236: #define TMDM_LCOL_SH 28
237: #define TMDM_EXDEF_MASK 0x20000000
238: #define TMDM_EXDEF_SH 29
239: #define TMDM_UFLO_MASK 0x40000000
240: #define TMDM_UFLO_SH 30
241: #define TMDM_BUFF_MASK 0x80000000
242: #define TMDM_BUFF_SH 31
243:
1.1 root 244: struct pcnet_RMD {
1.1.1.3 root 245: uint32_t rbadr;
246: int16_t buf_length;
247: int16_t status;
248: uint32_t msg_length;
249: uint32_t res;
1.1 root 250: };
251:
1.1.1.3 root 252: #define RMDL_BCNT_MASK 0x0fff
253: #define RMDL_BCNT_SH 0
254: #define RMDL_ONES_MASK 0xf000
255: #define RMDL_ONES_SH 12
256:
257: #define RMDS_BAM_MASK 0x0010
258: #define RMDS_BAM_SH 4
259: #define RMDS_LFAM_MASK 0x0020
260: #define RMDS_LFAM_SH 5
261: #define RMDS_PAM_MASK 0x0040
262: #define RMDS_PAM_SH 6
263: #define RMDS_BPE_MASK 0x0080
264: #define RMDS_BPE_SH 7
265: #define RMDS_ENP_MASK 0x0100
266: #define RMDS_ENP_SH 8
267: #define RMDS_STP_MASK 0x0200
268: #define RMDS_STP_SH 9
269: #define RMDS_BUFF_MASK 0x0400
270: #define RMDS_BUFF_SH 10
271: #define RMDS_CRC_MASK 0x0800
272: #define RMDS_CRC_SH 11
273: #define RMDS_OFLO_MASK 0x1000
274: #define RMDS_OFLO_SH 12
275: #define RMDS_FRAM_MASK 0x2000
276: #define RMDS_FRAM_SH 13
277: #define RMDS_ERR_MASK 0x4000
278: #define RMDS_ERR_SH 14
279: #define RMDS_OWN_MASK 0x8000
280: #define RMDS_OWN_SH 15
281:
282: #define RMDM_MCNT_MASK 0x00000fff
283: #define RMDM_MCNT_SH 0
284: #define RMDM_ZEROS_MASK 0x0000f000
285: #define RMDM_ZEROS_SH 12
286: #define RMDM_RPC_MASK 0x00ff0000
287: #define RMDM_RPC_SH 16
288: #define RMDM_RCC_MASK 0xff000000
289: #define RMDM_RCC_SH 24
290:
291: #define SET_FIELD(regp, name, field, value) \
292: (*(regp) = (*(regp) & ~(name ## _ ## field ## _MASK)) \
293: | ((value) << name ## _ ## field ## _SH))
294:
295: #define GET_FIELD(reg, name, field) \
296: (((reg) & name ## _ ## field ## _MASK) >> name ## _ ## field ## _SH)
1.1 root 297:
1.1.1.3 root 298: #define PRINT_TMD(T) printf( \
299: "TMD0 : TBADR=0x%08x\n" \
1.1 root 300: "TMD1 : OWN=%d, ERR=%d, FCS=%d, LTI=%d, " \
301: "ONE=%d, DEF=%d, STP=%d, ENP=%d,\n" \
302: " BPE=%d, BCNT=%d\n" \
303: "TMD2 : BUF=%d, UFL=%d, EXD=%d, LCO=%d, " \
304: "LCA=%d, RTR=%d,\n" \
305: " TDR=%d, TRC=%d\n", \
1.1.1.3 root 306: (T)->tbadr, \
307: GET_FIELD((T)->status, TMDS, OWN), \
308: GET_FIELD((T)->status, TMDS, ERR), \
309: GET_FIELD((T)->status, TMDS, NOFCS), \
310: GET_FIELD((T)->status, TMDS, LTINT), \
311: GET_FIELD((T)->status, TMDS, ONE), \
312: GET_FIELD((T)->status, TMDS, DEF), \
313: GET_FIELD((T)->status, TMDS, STP), \
314: GET_FIELD((T)->status, TMDS, ENP), \
315: GET_FIELD((T)->status, TMDS, BPE), \
316: 4096-GET_FIELD((T)->length, TMDL, BCNT), \
317: GET_FIELD((T)->misc, TMDM, BUFF), \
318: GET_FIELD((T)->misc, TMDM, UFLO), \
319: GET_FIELD((T)->misc, TMDM, EXDEF), \
320: GET_FIELD((T)->misc, TMDM, LCOL), \
321: GET_FIELD((T)->misc, TMDM, LCAR), \
322: GET_FIELD((T)->misc, TMDM, RTRY), \
323: GET_FIELD((T)->misc, TMDM, TDR), \
324: GET_FIELD((T)->misc, TMDM, TRC))
1.1 root 325:
1.1.1.3 root 326: #define PRINT_RMD(R) printf( \
327: "RMD0 : RBADR=0x%08x\n" \
1.1 root 328: "RMD1 : OWN=%d, ERR=%d, FRAM=%d, OFLO=%d, " \
329: "CRC=%d, BUFF=%d, STP=%d, ENP=%d,\n " \
1.1.1.3 root 330: "BPE=%d, PAM=%d, LAFM=%d, BAM=%d, ONES=%d, BCNT=%d\n" \
1.1 root 331: "RMD2 : RCC=%d, RPC=%d, MCNT=%d, ZEROS=%d\n", \
1.1.1.3 root 332: (R)->rbadr, \
333: GET_FIELD((R)->status, RMDS, OWN), \
334: GET_FIELD((R)->status, RMDS, ERR), \
335: GET_FIELD((R)->status, RMDS, FRAM), \
336: GET_FIELD((R)->status, RMDS, OFLO), \
337: GET_FIELD((R)->status, RMDS, CRC), \
338: GET_FIELD((R)->status, RMDS, BUFF), \
339: GET_FIELD((R)->status, RMDS, STP), \
340: GET_FIELD((R)->status, RMDS, ENP), \
341: GET_FIELD((R)->status, RMDS, BPE), \
342: GET_FIELD((R)->status, RMDS, PAM), \
343: GET_FIELD((R)->status, RMDS, LFAM), \
344: GET_FIELD((R)->status, RMDS, BAM), \
345: GET_FIELD((R)->buf_length, RMDL, ONES), \
346: 4096-GET_FIELD((R)->buf_length, RMDL, BCNT), \
347: GET_FIELD((R)->msg_length, RMDM, RCC), \
348: GET_FIELD((R)->msg_length, RMDM, RPC), \
349: GET_FIELD((R)->msg_length, RMDM, MCNT), \
350: GET_FIELD((R)->msg_length, RMDM, ZEROS))
1.1 root 351:
1.1.1.3 root 352: static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
1.1.1.2 root 353: target_phys_addr_t addr)
1.1 root 354: {
1.1.1.3 root 355: if (!BCR_SSIZE32(s)) {
356: struct {
357: uint32_t tbadr;
358: int16_t length;
359: int16_t status;
360: } xda;
361: s->phys_mem_read(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
362: tmd->tbadr = le32_to_cpu(xda.tbadr) & 0xffffff;
363: tmd->length = le16_to_cpu(xda.length);
364: tmd->status = (le32_to_cpu(xda.tbadr) >> 16) & 0xff00;
365: tmd->misc = le16_to_cpu(xda.status) << 16;
366: tmd->res = 0;
1.1.1.2 root 367: } else {
1.1.1.3 root 368: s->phys_mem_read(s->dma_opaque, addr, (void *)tmd, sizeof(*tmd), 0);
369: le32_to_cpus(&tmd->tbadr);
370: le16_to_cpus((uint16_t *)&tmd->length);
371: le16_to_cpus((uint16_t *)&tmd->status);
372: le32_to_cpus(&tmd->misc);
373: le32_to_cpus(&tmd->res);
374: if (BCR_SWSTYLE(s) == 3) {
375: uint32_t tmp = tmd->tbadr;
376: tmd->tbadr = tmd->misc;
377: tmd->misc = tmp;
1.1.1.2 root 378: }
1.1 root 379: }
380: }
381:
1.1.1.3 root 382: static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
1.1.1.2 root 383: target_phys_addr_t addr)
1.1 root 384: {
1.1.1.3 root 385: if (!BCR_SSIZE32(s)) {
386: struct {
387: uint32_t tbadr;
388: int16_t length;
389: int16_t status;
390: } xda;
391: xda.tbadr = cpu_to_le32((tmd->tbadr & 0xffffff) |
392: ((tmd->status & 0xff00) << 16));
393: xda.length = cpu_to_le16(tmd->length);
394: xda.status = cpu_to_le16(tmd->misc >> 16);
395: s->phys_mem_write(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
1.1.1.2 root 396: } else {
1.1.1.3 root 397: struct {
398: uint32_t tbadr;
399: int16_t length;
400: int16_t status;
401: uint32_t misc;
402: uint32_t res;
403: } xda;
404: xda.tbadr = cpu_to_le32(tmd->tbadr);
405: xda.length = cpu_to_le16(tmd->length);
406: xda.status = cpu_to_le16(tmd->status);
407: xda.misc = cpu_to_le32(tmd->misc);
408: xda.res = cpu_to_le32(tmd->res);
409: if (BCR_SWSTYLE(s) == 3) {
410: uint32_t tmp = xda.tbadr;
411: xda.tbadr = xda.misc;
412: xda.misc = tmp;
1.1 root 413: }
1.1.1.3 root 414: s->phys_mem_write(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
1.1 root 415: }
416: }
417:
1.1.1.3 root 418: static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
1.1.1.2 root 419: target_phys_addr_t addr)
1.1 root 420: {
1.1.1.3 root 421: if (!BCR_SSIZE32(s)) {
422: struct {
423: uint32_t rbadr;
424: int16_t buf_length;
425: int16_t msg_length;
426: } rda;
427: s->phys_mem_read(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
428: rmd->rbadr = le32_to_cpu(rda.rbadr) & 0xffffff;
429: rmd->buf_length = le16_to_cpu(rda.buf_length);
430: rmd->status = (le32_to_cpu(rda.rbadr) >> 16) & 0xff00;
431: rmd->msg_length = le16_to_cpu(rda.msg_length);
432: rmd->res = 0;
1.1.1.2 root 433: } else {
1.1.1.3 root 434: s->phys_mem_read(s->dma_opaque, addr, (void *)rmd, sizeof(*rmd), 0);
435: le32_to_cpus(&rmd->rbadr);
436: le16_to_cpus((uint16_t *)&rmd->buf_length);
437: le16_to_cpus((uint16_t *)&rmd->status);
438: le32_to_cpus(&rmd->msg_length);
439: le32_to_cpus(&rmd->res);
440: if (BCR_SWSTYLE(s) == 3) {
441: uint32_t tmp = rmd->rbadr;
442: rmd->rbadr = rmd->msg_length;
443: rmd->msg_length = tmp;
1.1.1.2 root 444: }
1.1 root 445: }
446: }
447:
1.1.1.3 root 448: static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd,
1.1.1.2 root 449: target_phys_addr_t addr)
1.1 root 450: {
1.1.1.3 root 451: if (!BCR_SSIZE32(s)) {
452: struct {
453: uint32_t rbadr;
454: int16_t buf_length;
455: int16_t msg_length;
456: } rda;
457: rda.rbadr = cpu_to_le32((rmd->rbadr & 0xffffff) |
458: ((rmd->status & 0xff00) << 16));
459: rda.buf_length = cpu_to_le16(rmd->buf_length);
460: rda.msg_length = cpu_to_le16(rmd->msg_length);
461: s->phys_mem_write(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
1.1.1.2 root 462: } else {
1.1.1.3 root 463: struct {
464: uint32_t rbadr;
465: int16_t buf_length;
466: int16_t status;
467: uint32_t msg_length;
468: uint32_t res;
469: } rda;
470: rda.rbadr = cpu_to_le32(rmd->rbadr);
471: rda.buf_length = cpu_to_le16(rmd->buf_length);
472: rda.status = cpu_to_le16(rmd->status);
473: rda.msg_length = cpu_to_le32(rmd->msg_length);
474: rda.res = cpu_to_le32(rmd->res);
475: if (BCR_SWSTYLE(s) == 3) {
476: uint32_t tmp = rda.rbadr;
477: rda.rbadr = rda.msg_length;
478: rda.msg_length = tmp;
1.1 root 479: }
1.1.1.3 root 480: s->phys_mem_write(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
1.1 root 481: }
482: }
483:
484:
485: #define TMDLOAD(TMD,ADDR) pcnet_tmd_load(s,TMD,ADDR)
486:
487: #define TMDSTORE(TMD,ADDR) pcnet_tmd_store(s,TMD,ADDR)
488:
489: #define RMDLOAD(RMD,ADDR) pcnet_rmd_load(s,RMD,ADDR)
490:
491: #define RMDSTORE(RMD,ADDR) pcnet_rmd_store(s,RMD,ADDR)
492:
493: #if 1
494:
495: #define CHECK_RMD(ADDR,RES) do { \
496: struct pcnet_RMD rmd; \
497: RMDLOAD(&rmd,(ADDR)); \
1.1.1.3 root 498: (RES) |= (GET_FIELD(rmd.buf_length, RMDL, ONES) != 15) \
499: || (GET_FIELD(rmd.msg_length, RMDM, ZEROS) != 0); \
1.1 root 500: } while (0)
501:
502: #define CHECK_TMD(ADDR,RES) do { \
503: struct pcnet_TMD tmd; \
504: TMDLOAD(&tmd,(ADDR)); \
1.1.1.3 root 505: (RES) |= (GET_FIELD(tmd.length, TMDL, ONES) != 15); \
1.1 root 506: } while (0)
507:
508: #else
509:
510: #define CHECK_RMD(ADDR,RES) do { \
511: switch (BCR_SWSTYLE(s)) { \
512: case 0x00: \
513: do { \
514: uint16_t rda[4]; \
1.1.1.3 root 515: s->phys_mem_read(s->dma_opaque, (ADDR), \
516: (void *)&rda[0], sizeof(rda), 0); \
1.1 root 517: (RES) |= (rda[2] & 0xf000)!=0xf000; \
518: (RES) |= (rda[3] & 0xf000)!=0x0000; \
519: } while (0); \
520: break; \
521: case 0x01: \
522: case 0x02: \
523: do { \
524: uint32_t rda[4]; \
1.1.1.3 root 525: s->phys_mem_read(s->dma_opaque, (ADDR), \
1.1.1.2 root 526: (void *)&rda[0], sizeof(rda), 0); \
1.1 root 527: (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
528: (RES) |= (rda[2] & 0x0000f000L)!=0x00000000L; \
529: } while (0); \
530: break; \
531: case 0x03: \
532: do { \
533: uint32_t rda[4]; \
1.1.1.3 root 534: s->phys_mem_read(s->dma_opaque, (ADDR), \
1.1.1.2 root 535: (void *)&rda[0], sizeof(rda), 0); \
1.1 root 536: (RES) |= (rda[0] & 0x0000f000L)!=0x00000000L; \
537: (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
538: } while (0); \
539: break; \
540: } \
541: } while (0)
542:
543: #define CHECK_TMD(ADDR,RES) do { \
544: switch (BCR_SWSTYLE(s)) { \
545: case 0x00: \
546: do { \
547: uint16_t xda[4]; \
1.1.1.3 root 548: s->phys_mem_read(s->dma_opaque, (ADDR), \
549: (void *)&xda[0], sizeof(xda), 0); \
550: (RES) |= (xda[2] & 0xf000)!=0xf000; \
1.1 root 551: } while (0); \
552: break; \
553: case 0x01: \
554: case 0x02: \
555: case 0x03: \
556: do { \
557: uint32_t xda[4]; \
1.1.1.3 root 558: s->phys_mem_read(s->dma_opaque, (ADDR), \
559: (void *)&xda[0], sizeof(xda), 0); \
1.1 root 560: (RES) |= (xda[1] & 0x0000f000L)!=0x0000f000L; \
561: } while (0); \
562: break; \
563: } \
564: } while (0)
565:
566: #endif
567:
568: #define PRINT_PKTHDR(BUF) do { \
1.1.1.3 root 569: struct qemu_ether_header *hdr = (void *)(BUF); \
570: printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, " \
571: "shost=%02x:%02x:%02x:%02x:%02x:%02x, " \
572: "type=0x%04x\n", \
1.1 root 573: hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], \
574: hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], \
575: hdr->ether_shost[0],hdr->ether_shost[1],hdr->ether_shost[2], \
576: hdr->ether_shost[3],hdr->ether_shost[4],hdr->ether_shost[5], \
1.1.1.3 root 577: be16_to_cpu(hdr->ether_type)); \
1.1 root 578: } while (0)
579:
580: #define MULTICAST_FILTER_LEN 8
581:
582: static inline uint32_t lnc_mchash(const uint8_t *ether_addr)
583: {
584: #define LNC_POLYNOMIAL 0xEDB88320UL
585: uint32_t crc = 0xFFFFFFFF;
586: int idx, bit;
587: uint8_t data;
588:
589: for (idx = 0; idx < 6; idx++) {
590: for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++) {
591: crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0);
592: data >>= 1;
593: }
594: }
595: return crc;
596: #undef LNC_POLYNOMIAL
597: }
598:
599: #define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
600:
601: /* generated using the AUTODIN II polynomial
602: * x^32 + x^26 + x^23 + x^22 + x^16 +
603: * x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
604: */
605: static const uint32_t crctab[256] = {
606: 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
607: 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
608: 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
609: 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
610: 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
611: 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
612: 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
613: 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
614: 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
615: 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
616: 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
617: 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
618: 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
619: 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
620: 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
621: 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
622: 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
623: 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
624: 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
625: 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
626: 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
627: 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
628: 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
629: 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
630: 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
631: 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
632: 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
633: 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
634: 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
635: 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
636: 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
637: 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
638: 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
639: 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
640: 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
641: 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
642: 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
643: 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
644: 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
645: 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
646: 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
647: 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
648: 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
649: 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
650: 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
651: 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
652: 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
653: 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
654: 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
655: 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
656: 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
657: 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
658: 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
659: 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
660: 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
661: 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
662: 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
663: 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
664: 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
665: 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
666: 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
667: 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
668: 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
669: 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
670: };
671:
672: static inline int padr_match(PCNetState *s, const uint8_t *buf, int size)
673: {
674: struct qemu_ether_header *hdr = (void *)buf;
1.1.1.3 root 675: uint8_t padr[6] = {
1.1 root 676: s->csr[12] & 0xff, s->csr[12] >> 8,
677: s->csr[13] & 0xff, s->csr[13] >> 8,
1.1.1.3 root 678: s->csr[14] & 0xff, s->csr[14] >> 8
1.1 root 679: };
680: int result = (!CSR_DRCVPA(s)) && !memcmp(hdr->ether_dhost, padr, 6);
681: #ifdef PCNET_DEBUG_MATCH
682: printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, "
683: "padr=%02x:%02x:%02x:%02x:%02x:%02x\n",
684: hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2],
685: hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5],
686: padr[0],padr[1],padr[2],padr[3],padr[4],padr[5]);
687: printf("padr_match result=%d\n", result);
688: #endif
689: return result;
690: }
691:
692: static inline int padr_bcast(PCNetState *s, const uint8_t *buf, int size)
693: {
1.1.1.2 root 694: static const uint8_t BCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1.1 root 695: struct qemu_ether_header *hdr = (void *)buf;
696: int result = !CSR_DRCVBC(s) && !memcmp(hdr->ether_dhost, BCAST, 6);
697: #ifdef PCNET_DEBUG_MATCH
698: printf("padr_bcast result=%d\n", result);
699: #endif
700: return result;
701: }
702:
703: static inline int ladr_match(PCNetState *s, const uint8_t *buf, int size)
704: {
705: struct qemu_ether_header *hdr = (void *)buf;
1.1.1.3 root 706: if ((*(hdr->ether_dhost)&0x01) &&
1.1 root 707: ((uint64_t *)&s->csr[8])[0] != 0LL) {
1.1.1.3 root 708: uint8_t ladr[8] = {
1.1 root 709: s->csr[8] & 0xff, s->csr[8] >> 8,
710: s->csr[9] & 0xff, s->csr[9] >> 8,
1.1.1.3 root 711: s->csr[10] & 0xff, s->csr[10] >> 8,
712: s->csr[11] & 0xff, s->csr[11] >> 8
1.1 root 713: };
714: int index = lnc_mchash(hdr->ether_dhost) >> 26;
715: return !!(ladr[index >> 3] & (1 << (index & 7)));
716: }
717: return 0;
718: }
719:
1.1.1.3 root 720: static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx)
1.1 root 721: {
722: while (idx < 1) idx += CSR_RCVRL(s);
723: return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
724: }
725:
726: static inline int64_t pcnet_get_next_poll_time(PCNetState *s, int64_t current_time)
727: {
1.1.1.3 root 728: int64_t next_time = current_time +
729: muldiv64(65536 - (CSR_SPND(s) ? 0 : CSR_POLL(s)),
1.1 root 730: ticks_per_sec, 33000000L);
731: if (next_time <= current_time)
732: next_time = current_time + 1;
733: return next_time;
734: }
735:
736: static void pcnet_poll(PCNetState *s);
737: static void pcnet_poll_timer(void *opaque);
738:
739: static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap);
740: static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value);
741: static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val);
742: static uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap);
743:
744: static void pcnet_s_reset(PCNetState *s)
745: {
746: #ifdef PCNET_DEBUG
747: printf("pcnet_s_reset\n");
748: #endif
749:
750: s->lnkst = 0x40;
751: s->rdra = 0;
752: s->tdra = 0;
753: s->rap = 0;
1.1.1.3 root 754:
1.1 root 755: s->bcr[BCR_BSBC] &= ~0x0080;
756:
757: s->csr[0] = 0x0004;
758: s->csr[3] = 0x0000;
759: s->csr[4] = 0x0115;
760: s->csr[5] = 0x0000;
761: s->csr[6] = 0x0000;
762: s->csr[8] = 0;
763: s->csr[9] = 0;
764: s->csr[10] = 0;
765: s->csr[11] = 0;
766: s->csr[12] = le16_to_cpu(((uint16_t *)&s->prom[0])[0]);
767: s->csr[13] = le16_to_cpu(((uint16_t *)&s->prom[0])[1]);
768: s->csr[14] = le16_to_cpu(((uint16_t *)&s->prom[0])[2]);
769: s->csr[15] &= 0x21c4;
770: s->csr[72] = 1;
771: s->csr[74] = 1;
772: s->csr[76] = 1;
773: s->csr[78] = 1;
774: s->csr[80] = 0x1410;
775: s->csr[88] = 0x1003;
776: s->csr[89] = 0x0262;
777: s->csr[94] = 0x0000;
778: s->csr[100] = 0x0200;
779: s->csr[103] = 0x0105;
780: s->csr[103] = 0x0105;
781: s->csr[112] = 0x0000;
782: s->csr[114] = 0x0000;
783: s->csr[122] = 0x0000;
784: s->csr[124] = 0x0000;
785:
786: s->tx_busy = 0;
787: }
788:
789: static void pcnet_update_irq(PCNetState *s)
790: {
791: int isr = 0;
792: s->csr[0] &= ~0x0080;
1.1.1.3 root 793:
1.1 root 794: #if 1
795: if (((s->csr[0] & ~s->csr[3]) & 0x5f00) ||
796: (((s->csr[4]>>1) & ~s->csr[4]) & 0x0115) ||
797: (((s->csr[5]>>1) & s->csr[5]) & 0x0048))
798: #else
799: if ((!(s->csr[3] & 0x4000) && !!(s->csr[0] & 0x4000)) /* BABL */ ||
800: (!(s->csr[3] & 0x1000) && !!(s->csr[0] & 0x1000)) /* MISS */ ||
801: (!(s->csr[3] & 0x0100) && !!(s->csr[0] & 0x0100)) /* IDON */ ||
802: (!(s->csr[3] & 0x0200) && !!(s->csr[0] & 0x0200)) /* TINT */ ||
803: (!(s->csr[3] & 0x0400) && !!(s->csr[0] & 0x0400)) /* RINT */ ||
804: (!(s->csr[3] & 0x0800) && !!(s->csr[0] & 0x0800)) /* MERR */ ||
805: (!(s->csr[4] & 0x0001) && !!(s->csr[4] & 0x0002)) /* JAB */ ||
806: (!(s->csr[4] & 0x0004) && !!(s->csr[4] & 0x0008)) /* TXSTRT */ ||
807: (!(s->csr[4] & 0x0010) && !!(s->csr[4] & 0x0020)) /* RCVO */ ||
808: (!(s->csr[4] & 0x0100) && !!(s->csr[4] & 0x0200)) /* MFCO */ ||
809: (!!(s->csr[5] & 0x0040) && !!(s->csr[5] & 0x0080)) /* EXDINT */ ||
810: (!!(s->csr[5] & 0x0008) && !!(s->csr[5] & 0x0010)) /* MPINT */)
811: #endif
812: {
1.1.1.3 root 813:
1.1 root 814: isr = CSR_INEA(s);
815: s->csr[0] |= 0x0080;
816: }
1.1.1.3 root 817:
1.1 root 818: if (!!(s->csr[4] & 0x0080) && CSR_INEA(s)) { /* UINT */
819: s->csr[4] &= ~0x0080;
820: s->csr[4] |= 0x0040;
821: s->csr[0] |= 0x0080;
822: isr = 1;
823: #ifdef PCNET_DEBUG
824: printf("pcnet user int\n");
825: #endif
826: }
827:
828: #if 1
1.1.1.3 root 829: if (((s->csr[5]>>1) & s->csr[5]) & 0x0500)
1.1 root 830: #else
831: if ((!!(s->csr[5] & 0x0400) && !!(s->csr[5] & 0x0800)) /* SINT */ ||
832: (!!(s->csr[5] & 0x0100) && !!(s->csr[5] & 0x0200)) /* SLPINT */ )
833: #endif
834: {
835: isr = 1;
836: s->csr[0] |= 0x0080;
837: }
838:
839: if (isr != s->isr) {
840: #ifdef PCNET_DEBUG
841: printf("pcnet: INTA=%d\n", isr);
842: #endif
843: }
1.1.1.3 root 844: qemu_set_irq(s->irq, isr);
1.1.1.2 root 845: s->isr = isr;
1.1 root 846: }
847:
848: static void pcnet_init(PCNetState *s)
849: {
1.1.1.2 root 850: int rlen, tlen;
1.1.1.3 root 851: uint16_t padr[3], ladrf[4], mode;
1.1.1.2 root 852: uint32_t rdra, tdra;
853:
1.1 root 854: #ifdef PCNET_DEBUG
855: printf("pcnet_init init_addr=0x%08x\n", PHYSADDR(s,CSR_IADR(s)));
856: #endif
1.1.1.3 root 857:
1.1 root 858: if (BCR_SSIZE32(s)) {
859: struct pcnet_initblk32 initblk;
1.1.1.2 root 860: s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
861: (uint8_t *)&initblk, sizeof(initblk), 0);
1.1.1.3 root 862: mode = le16_to_cpu(initblk.mode);
1.1.1.2 root 863: rlen = initblk.rlen >> 4;
864: tlen = initblk.tlen >> 4;
1.1.1.3 root 865: ladrf[0] = le16_to_cpu(initblk.ladrf[0]);
866: ladrf[1] = le16_to_cpu(initblk.ladrf[1]);
867: ladrf[2] = le16_to_cpu(initblk.ladrf[2]);
868: ladrf[3] = le16_to_cpu(initblk.ladrf[3]);
869: padr[0] = le16_to_cpu(initblk.padr[0]);
870: padr[1] = le16_to_cpu(initblk.padr[1]);
871: padr[2] = le16_to_cpu(initblk.padr[2]);
1.1.1.2 root 872: rdra = le32_to_cpu(initblk.rdra);
873: tdra = le32_to_cpu(initblk.tdra);
1.1 root 874: } else {
875: struct pcnet_initblk16 initblk;
1.1.1.2 root 876: s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
877: (uint8_t *)&initblk, sizeof(initblk), 0);
1.1.1.3 root 878: mode = le16_to_cpu(initblk.mode);
879: ladrf[0] = le16_to_cpu(initblk.ladrf[0]);
880: ladrf[1] = le16_to_cpu(initblk.ladrf[1]);
881: ladrf[2] = le16_to_cpu(initblk.ladrf[2]);
882: ladrf[3] = le16_to_cpu(initblk.ladrf[3]);
883: padr[0] = le16_to_cpu(initblk.padr[0]);
884: padr[1] = le16_to_cpu(initblk.padr[1]);
885: padr[2] = le16_to_cpu(initblk.padr[2]);
1.1.1.2 root 886: rdra = le32_to_cpu(initblk.rdra);
887: tdra = le32_to_cpu(initblk.tdra);
888: rlen = rdra >> 29;
889: tlen = tdra >> 29;
890: rdra &= 0x00ffffff;
891: tdra &= 0x00ffffff;
1.1 root 892: }
1.1.1.3 root 893:
1.1.1.2 root 894: #if defined(PCNET_DEBUG)
1.1.1.3 root 895: printf("rlen=%d tlen=%d\n", rlen, tlen);
1.1.1.2 root 896: #endif
1.1.1.3 root 897:
1.1.1.2 root 898: CSR_RCVRL(s) = (rlen < 9) ? (1 << rlen) : 512;
899: CSR_XMTRL(s) = (tlen < 9) ? (1 << tlen) : 512;
900: s->csr[ 6] = (tlen << 12) | (rlen << 8);
1.1.1.3 root 901: s->csr[15] = mode;
902: s->csr[ 8] = ladrf[0];
903: s->csr[ 9] = ladrf[1];
904: s->csr[10] = ladrf[2];
905: s->csr[11] = ladrf[3];
906: s->csr[12] = padr[0];
907: s->csr[13] = padr[1];
908: s->csr[14] = padr[2];
1.1.1.2 root 909: s->rdra = PHYSADDR(s, rdra);
910: s->tdra = PHYSADDR(s, tdra);
1.1 root 911:
912: CSR_RCVRC(s) = CSR_RCVRL(s);
913: CSR_XMTRC(s) = CSR_XMTRL(s);
914:
915: #ifdef PCNET_DEBUG
1.1.1.3 root 916: printf("pcnet ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]\n",
1.1 root 917: BCR_SSIZE32(s),
918: s->rdra, CSR_RCVRL(s), s->tdra, CSR_XMTRL(s));
919: #endif
920:
1.1.1.3 root 921: s->csr[0] |= 0x0101;
1.1 root 922: s->csr[0] &= ~0x0004; /* clear STOP bit */
923: }
924:
925: static void pcnet_start(PCNetState *s)
926: {
927: #ifdef PCNET_DEBUG
928: printf("pcnet_start\n");
929: #endif
930:
931: if (!CSR_DTX(s))
932: s->csr[0] |= 0x0010; /* set TXON */
1.1.1.3 root 933:
1.1 root 934: if (!CSR_DRX(s))
935: s->csr[0] |= 0x0020; /* set RXON */
936:
937: s->csr[0] &= ~0x0004; /* clear STOP bit */
938: s->csr[0] |= 0x0002;
1.1.1.7 ! root 939: pcnet_poll_timer(s);
1.1 root 940: }
941:
942: static void pcnet_stop(PCNetState *s)
943: {
944: #ifdef PCNET_DEBUG
945: printf("pcnet_stop\n");
946: #endif
947: s->csr[0] &= ~0x7feb;
948: s->csr[0] |= 0x0014;
949: s->csr[4] &= ~0x02c2;
950: s->csr[5] &= ~0x0011;
951: pcnet_poll_timer(s);
952: }
953:
954: static void pcnet_rdte_poll(PCNetState *s)
955: {
956: s->csr[28] = s->csr[29] = 0;
957: if (s->rdra) {
958: int bad = 0;
959: #if 1
960: target_phys_addr_t crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
961: target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
962: target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
963: #else
1.1.1.3 root 964: target_phys_addr_t crda = s->rdra +
1.1 root 965: (CSR_RCVRL(s) - CSR_RCVRC(s)) *
966: (BCR_SWSTYLE(s) ? 16 : 8 );
967: int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
1.1.1.3 root 968: target_phys_addr_t nrda = s->rdra +
1.1 root 969: (CSR_RCVRL(s) - nrdc) *
970: (BCR_SWSTYLE(s) ? 16 : 8 );
971: int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
1.1.1.3 root 972: target_phys_addr_t nnrd = s->rdra +
1.1 root 973: (CSR_RCVRL(s) - nnrc) *
974: (BCR_SWSTYLE(s) ? 16 : 8 );
975: #endif
976:
1.1.1.6 root 977: CHECK_RMD(crda, bad);
1.1 root 978: if (!bad) {
1.1.1.6 root 979: CHECK_RMD(nrda, bad);
1.1 root 980: if (bad || (nrda == crda)) nrda = 0;
1.1.1.6 root 981: CHECK_RMD(nnrd, bad);
1.1 root 982: if (bad || (nnrd == crda)) nnrd = 0;
983:
984: s->csr[28] = crda & 0xffff;
985: s->csr[29] = crda >> 16;
986: s->csr[26] = nrda & 0xffff;
987: s->csr[27] = nrda >> 16;
988: s->csr[36] = nnrd & 0xffff;
989: s->csr[37] = nnrd >> 16;
990: #ifdef PCNET_DEBUG
991: if (bad) {
1.1.1.4 root 992: printf("pcnet: BAD RMD RECORDS AFTER 0x" TARGET_FMT_plx "\n",
1.1.1.6 root 993: crda);
1.1 root 994: }
995: } else {
1.1.1.4 root 996: printf("pcnet: BAD RMD RDA=0x" TARGET_FMT_plx "\n",
1.1.1.6 root 997: crda);
1.1 root 998: #endif
999: }
1000: }
1.1.1.3 root 1001:
1.1 root 1002: if (CSR_CRDA(s)) {
1003: struct pcnet_RMD rmd;
1004: RMDLOAD(&rmd, PHYSADDR(s,CSR_CRDA(s)));
1.1.1.3 root 1005: CSR_CRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
1006: CSR_CRST(s) = rmd.status;
1.1 root 1007: #ifdef PCNET_DEBUG_RMD_X
1.1.1.3 root 1008: printf("CRDA=0x%08x CRST=0x%04x RCVRC=%d RMDL=0x%04x RMDS=0x%04x RMDM=0x%08x\n",
1.1 root 1009: PHYSADDR(s,CSR_CRDA(s)), CSR_CRST(s), CSR_RCVRC(s),
1.1.1.3 root 1010: rmd.buf_length, rmd.status, rmd.msg_length);
1.1 root 1011: PRINT_RMD(&rmd);
1012: #endif
1013: } else {
1014: CSR_CRBC(s) = CSR_CRST(s) = 0;
1015: }
1.1.1.3 root 1016:
1.1 root 1017: if (CSR_NRDA(s)) {
1018: struct pcnet_RMD rmd;
1019: RMDLOAD(&rmd, PHYSADDR(s,CSR_NRDA(s)));
1.1.1.3 root 1020: CSR_NRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
1021: CSR_NRST(s) = rmd.status;
1.1 root 1022: } else {
1023: CSR_NRBC(s) = CSR_NRST(s) = 0;
1024: }
1025:
1026: }
1027:
1028: static int pcnet_tdte_poll(PCNetState *s)
1029: {
1030: s->csr[34] = s->csr[35] = 0;
1031: if (s->tdra) {
1.1.1.3 root 1032: target_phys_addr_t cxda = s->tdra +
1.1 root 1033: (CSR_XMTRL(s) - CSR_XMTRC(s)) *
1.1.1.3 root 1034: (BCR_SWSTYLE(s) ? 16 : 8);
1.1 root 1035: int bad = 0;
1.1.1.6 root 1036: CHECK_TMD(cxda, bad);
1.1 root 1037: if (!bad) {
1038: if (CSR_CXDA(s) != cxda) {
1039: s->csr[60] = s->csr[34];
1040: s->csr[61] = s->csr[35];
1041: s->csr[62] = CSR_CXBC(s);
1042: s->csr[63] = CSR_CXST(s);
1043: }
1044: s->csr[34] = cxda & 0xffff;
1045: s->csr[35] = cxda >> 16;
1.1.1.3 root 1046: #ifdef PCNET_DEBUG_X
1.1.1.6 root 1047: printf("pcnet: BAD TMD XDA=0x%08x\n", cxda);
1.1 root 1048: #endif
1049: }
1050: }
1051:
1052: if (CSR_CXDA(s)) {
1053: struct pcnet_TMD tmd;
1054:
1.1.1.3 root 1055: TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
1.1 root 1056:
1.1.1.3 root 1057: CSR_CXBC(s) = GET_FIELD(tmd.length, TMDL, BCNT);
1058: CSR_CXST(s) = tmd.status;
1.1 root 1059: } else {
1060: CSR_CXBC(s) = CSR_CXST(s) = 0;
1061: }
1.1.1.3 root 1062:
1.1 root 1063: return !!(CSR_CXST(s) & 0x8000);
1064: }
1065:
1.1.1.6 root 1066: static int pcnet_can_receive(VLANClientState *vc)
1.1 root 1067: {
1.1.1.6 root 1068: PCNetState *s = vc->opaque;
1.1 root 1069: if (CSR_STOP(s) || CSR_SPND(s))
1070: return 0;
1.1.1.3 root 1071:
1.1 root 1072: if (s->recv_pos > 0)
1073: return 0;
1074:
1075: return sizeof(s->buffer)-16;
1076: }
1077:
1078: #define MIN_BUF_SIZE 60
1079:
1.1.1.6 root 1080: static ssize_t pcnet_receive(VLANClientState *vc, const uint8_t *buf, size_t size_)
1.1 root 1081: {
1.1.1.6 root 1082: PCNetState *s = vc->opaque;
1.1 root 1083: int is_padr = 0, is_bcast = 0, is_ladr = 0;
1084: uint8_t buf1[60];
1.1.1.4 root 1085: int remaining;
1086: int crc_err = 0;
1.1.1.6 root 1087: int size = size_;
1.1 root 1088:
1089: if (CSR_DRX(s) || CSR_STOP(s) || CSR_SPND(s) || !size)
1.1.1.6 root 1090: return -1;
1.1 root 1091:
1092: #ifdef PCNET_DEBUG
1093: printf("pcnet_receive size=%d\n", size);
1094: #endif
1095:
1096: /* if too small buffer, then expand it */
1097: if (size < MIN_BUF_SIZE) {
1098: memcpy(buf1, buf, size);
1099: memset(buf1 + size, 0, MIN_BUF_SIZE - size);
1100: buf = buf1;
1101: size = MIN_BUF_SIZE;
1102: }
1103:
1.1.1.3 root 1104: if (CSR_PROM(s)
1105: || (is_padr=padr_match(s, buf, size))
1.1 root 1106: || (is_bcast=padr_bcast(s, buf, size))
1107: || (is_ladr=ladr_match(s, buf, size))) {
1108:
1109: pcnet_rdte_poll(s);
1110:
1111: if (!(CSR_CRST(s) & 0x8000) && s->rdra) {
1112: struct pcnet_RMD rmd;
1113: int rcvrc = CSR_RCVRC(s)-1,i;
1114: target_phys_addr_t nrda;
1115: for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) {
1116: if (rcvrc <= 1)
1117: rcvrc = CSR_RCVRL(s);
1118: nrda = s->rdra +
1119: (CSR_RCVRL(s) - rcvrc) *
1120: (BCR_SWSTYLE(s) ? 16 : 8 );
1.1.1.6 root 1121: RMDLOAD(&rmd, nrda);
1.1.1.3 root 1122: if (GET_FIELD(rmd.status, RMDS, OWN)) {
1.1 root 1123: #ifdef PCNET_DEBUG_RMD
1.1.1.3 root 1124: printf("pcnet - scan buffer: RCVRC=%d PREV_RCVRC=%d\n",
1.1 root 1125: rcvrc, CSR_RCVRC(s));
1126: #endif
1127: CSR_RCVRC(s) = rcvrc;
1128: pcnet_rdte_poll(s);
1129: break;
1130: }
1131: }
1132: }
1133:
1134: if (!(CSR_CRST(s) & 0x8000)) {
1135: #ifdef PCNET_DEBUG_RMD
1136: printf("pcnet - no buffer: RCVRC=%d\n", CSR_RCVRC(s));
1137: #endif
1138: s->csr[0] |= 0x1000; /* Set MISS flag */
1139: CSR_MISSC(s)++;
1140: } else {
1.1.1.4 root 1141: uint8_t *src = s->buffer;
1.1 root 1142: target_phys_addr_t crda = CSR_CRDA(s);
1143: struct pcnet_RMD rmd;
1144: int pktcount = 0;
1145:
1.1.1.4 root 1146: if (!s->looptest) {
1147: memcpy(src, buf, size);
1148: /* no need to compute the CRC */
1149: src[size] = 0;
1150: src[size + 1] = 0;
1151: src[size + 2] = 0;
1152: src[size + 3] = 0;
1153: size += 4;
1154: } else if (s->looptest == PCNET_LOOPTEST_CRC ||
1155: !CSR_DXMTFCS(s) || size < MIN_BUF_SIZE+4) {
1.1 root 1156: uint32_t fcs = ~0;
1157: uint8_t *p = src;
1158:
1.1.1.4 root 1159: while (p != &src[size])
1160: CRC(fcs, *p++);
1161: *(uint32_t *)p = htonl(fcs);
1162: size += 4;
1163: } else {
1164: uint32_t fcs = ~0;
1165: uint8_t *p = src;
1.1.1.3 root 1166:
1.1.1.4 root 1167: while (p != &src[size-4])
1.1 root 1168: CRC(fcs, *p++);
1.1.1.4 root 1169: crc_err = (*(uint32_t *)p != htonl(fcs));
1170: }
1.1 root 1171:
1172: #ifdef PCNET_DEBUG_MATCH
1173: PRINT_PKTHDR(buf);
1174: #endif
1175:
1176: RMDLOAD(&rmd, PHYSADDR(s,crda));
1177: /*if (!CSR_LAPPEN(s))*/
1.1.1.3 root 1178: SET_FIELD(&rmd.status, RMDS, STP, 1);
1.1 root 1179:
1180: #define PCNET_RECV_STORE() do { \
1.1.1.4 root 1181: int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
1.1.1.3 root 1182: target_phys_addr_t rbadr = PHYSADDR(s, rmd.rbadr); \
1183: s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
1.1.1.4 root 1184: src += count; remaining -= count; \
1.1.1.3 root 1185: SET_FIELD(&rmd.status, RMDS, OWN, 0); \
1.1 root 1186: RMDSTORE(&rmd, PHYSADDR(s,crda)); \
1187: pktcount++; \
1188: } while (0)
1189:
1.1.1.4 root 1190: remaining = size;
1.1 root 1191: PCNET_RECV_STORE();
1.1.1.4 root 1192: if ((remaining > 0) && CSR_NRDA(s)) {
1.1 root 1193: target_phys_addr_t nrda = CSR_NRDA(s);
1.1.1.4 root 1194: #ifdef PCNET_DEBUG_RMD
1195: PRINT_RMD(&rmd);
1196: #endif
1.1 root 1197: RMDLOAD(&rmd, PHYSADDR(s,nrda));
1.1.1.3 root 1198: if (GET_FIELD(rmd.status, RMDS, OWN)) {
1.1 root 1199: crda = nrda;
1200: PCNET_RECV_STORE();
1.1.1.4 root 1201: #ifdef PCNET_DEBUG_RMD
1202: PRINT_RMD(&rmd);
1203: #endif
1204: if ((remaining > 0) && (nrda=CSR_NNRD(s))) {
1.1 root 1205: RMDLOAD(&rmd, PHYSADDR(s,nrda));
1.1.1.3 root 1206: if (GET_FIELD(rmd.status, RMDS, OWN)) {
1.1 root 1207: crda = nrda;
1208: PCNET_RECV_STORE();
1209: }
1210: }
1.1.1.3 root 1211: }
1.1 root 1212: }
1213:
1214: #undef PCNET_RECV_STORE
1215:
1216: RMDLOAD(&rmd, PHYSADDR(s,crda));
1.1.1.4 root 1217: if (remaining == 0) {
1218: SET_FIELD(&rmd.msg_length, RMDM, MCNT, size);
1.1.1.3 root 1219: SET_FIELD(&rmd.status, RMDS, ENP, 1);
1220: SET_FIELD(&rmd.status, RMDS, PAM, !CSR_PROM(s) && is_padr);
1221: SET_FIELD(&rmd.status, RMDS, LFAM, !CSR_PROM(s) && is_ladr);
1222: SET_FIELD(&rmd.status, RMDS, BAM, !CSR_PROM(s) && is_bcast);
1.1.1.4 root 1223: if (crc_err) {
1224: SET_FIELD(&rmd.status, RMDS, CRC, 1);
1225: SET_FIELD(&rmd.status, RMDS, ERR, 1);
1226: }
1.1 root 1227: } else {
1.1.1.3 root 1228: SET_FIELD(&rmd.status, RMDS, OFLO, 1);
1229: SET_FIELD(&rmd.status, RMDS, BUFF, 1);
1230: SET_FIELD(&rmd.status, RMDS, ERR, 1);
1.1 root 1231: }
1232: RMDSTORE(&rmd, PHYSADDR(s,crda));
1233: s->csr[0] |= 0x0400;
1234:
1235: #ifdef PCNET_DEBUG
1.1.1.3 root 1236: printf("RCVRC=%d CRDA=0x%08x BLKS=%d\n",
1.1 root 1237: CSR_RCVRC(s), PHYSADDR(s,CSR_CRDA(s)), pktcount);
1238: #endif
1239: #ifdef PCNET_DEBUG_RMD
1240: PRINT_RMD(&rmd);
1.1.1.3 root 1241: #endif
1.1 root 1242:
1243: while (pktcount--) {
1244: if (CSR_RCVRC(s) <= 1)
1245: CSR_RCVRC(s) = CSR_RCVRL(s);
1246: else
1.1.1.3 root 1247: CSR_RCVRC(s)--;
1.1 root 1248: }
1.1.1.3 root 1249:
1.1 root 1250: pcnet_rdte_poll(s);
1251:
1.1.1.3 root 1252: }
1.1 root 1253: }
1254:
1255: pcnet_poll(s);
1.1.1.3 root 1256: pcnet_update_irq(s);
1.1.1.6 root 1257:
1258: return size_;
1.1 root 1259: }
1260:
1261: static void pcnet_transmit(PCNetState *s)
1262: {
1263: target_phys_addr_t xmit_cxda = 0;
1264: int count = CSR_XMTRL(s)-1;
1.1.1.4 root 1265: int add_crc = 0;
1266:
1.1 root 1267: s->xmit_pos = -1;
1.1.1.3 root 1268:
1.1 root 1269: if (!CSR_TXON(s)) {
1270: s->csr[0] &= ~0x0008;
1271: return;
1272: }
1273:
1274: s->tx_busy = 1;
1275:
1276: txagain:
1277: if (pcnet_tdte_poll(s)) {
1278: struct pcnet_TMD tmd;
1279:
1.1.1.3 root 1280: TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
1.1 root 1281:
1282: #ifdef PCNET_DEBUG_TMD
1283: printf(" TMDLOAD 0x%08x\n", PHYSADDR(s,CSR_CXDA(s)));
1284: PRINT_TMD(&tmd);
1285: #endif
1.1.1.3 root 1286: if (GET_FIELD(tmd.status, TMDS, STP)) {
1287: s->xmit_pos = 0;
1.1 root 1288: xmit_cxda = PHYSADDR(s,CSR_CXDA(s));
1.1.1.4 root 1289: if (BCR_SWSTYLE(s) != 1)
1290: add_crc = GET_FIELD(tmd.status, TMDS, ADDFCS);
1.1 root 1291: }
1.1.1.4 root 1292: if (!GET_FIELD(tmd.status, TMDS, ENP)) {
1293: int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
1294: s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
1295: s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
1296: s->xmit_pos += bcnt;
1297: } else if (s->xmit_pos >= 0) {
1.1.1.3 root 1298: int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
1299: s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
1300: s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
1301: s->xmit_pos += bcnt;
1.1 root 1302: #ifdef PCNET_DEBUG
1303: printf("pcnet_transmit size=%d\n", s->xmit_pos);
1.1.1.3 root 1304: #endif
1.1.1.4 root 1305: if (CSR_LOOP(s)) {
1306: if (BCR_SWSTYLE(s) == 1)
1307: add_crc = !GET_FIELD(tmd.status, TMDS, NOFCS);
1308: s->looptest = add_crc ? PCNET_LOOPTEST_CRC : PCNET_LOOPTEST_NOCRC;
1.1.1.6 root 1309: pcnet_receive(s->vc, s->buffer, s->xmit_pos);
1.1.1.4 root 1310: s->looptest = 0;
1311: } else
1.1.1.3 root 1312: if (s->vc)
1313: qemu_send_packet(s->vc, s->buffer, s->xmit_pos);
1.1 root 1314:
1315: s->csr[0] &= ~0x0008; /* clear TDMD */
1316: s->csr[4] |= 0x0004; /* set TXSTRT */
1317: s->xmit_pos = -1;
1318: }
1319:
1.1.1.3 root 1320: SET_FIELD(&tmd.status, TMDS, OWN, 0);
1.1 root 1321: TMDSTORE(&tmd, PHYSADDR(s,CSR_CXDA(s)));
1.1.1.3 root 1322: if (!CSR_TOKINTD(s) || (CSR_LTINTEN(s) && GET_FIELD(tmd.status, TMDS, LTINT)))
1.1 root 1323: s->csr[0] |= 0x0200; /* set TINT */
1324:
1325: if (CSR_XMTRC(s)<=1)
1326: CSR_XMTRC(s) = CSR_XMTRL(s);
1327: else
1328: CSR_XMTRC(s)--;
1329: if (count--)
1330: goto txagain;
1331:
1.1.1.3 root 1332: } else
1.1 root 1333: if (s->xmit_pos >= 0) {
1334: struct pcnet_TMD tmd;
1.1.1.6 root 1335: TMDLOAD(&tmd, xmit_cxda);
1.1.1.3 root 1336: SET_FIELD(&tmd.misc, TMDM, BUFF, 1);
1337: SET_FIELD(&tmd.misc, TMDM, UFLO, 1);
1338: SET_FIELD(&tmd.status, TMDS, ERR, 1);
1339: SET_FIELD(&tmd.status, TMDS, OWN, 0);
1.1.1.6 root 1340: TMDSTORE(&tmd, xmit_cxda);
1.1 root 1341: s->csr[0] |= 0x0200; /* set TINT */
1342: if (!CSR_DXSUFLO(s)) {
1343: s->csr[0] &= ~0x0010;
1344: } else
1345: if (count--)
1346: goto txagain;
1347: }
1348:
1349: s->tx_busy = 0;
1350: }
1351:
1352: static void pcnet_poll(PCNetState *s)
1353: {
1354: if (CSR_RXON(s)) {
1355: pcnet_rdte_poll(s);
1356: }
1357:
1.1.1.3 root 1358: if (CSR_TDMD(s) ||
1.1 root 1359: (CSR_TXON(s) && !CSR_DPOLL(s) && pcnet_tdte_poll(s)))
1360: {
1361: /* prevent recursion */
1362: if (s->tx_busy)
1363: return;
1364:
1365: pcnet_transmit(s);
1366: }
1367: }
1368:
1369: static void pcnet_poll_timer(void *opaque)
1370: {
1371: PCNetState *s = opaque;
1372:
1373: qemu_del_timer(s->poll_timer);
1374:
1375: if (CSR_TDMD(s)) {
1376: pcnet_transmit(s);
1377: }
1378:
1.1.1.3 root 1379: pcnet_update_irq(s);
1.1 root 1380:
1381: if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {
1382: uint64_t now = qemu_get_clock(vm_clock) * 33;
1383: if (!s->timer || !now)
1384: s->timer = now;
1385: else {
1386: uint64_t t = now - s->timer + CSR_POLL(s);
1387: if (t > 0xffffLL) {
1388: pcnet_poll(s);
1389: CSR_POLL(s) = CSR_PINT(s);
1390: } else
1391: CSR_POLL(s) = t;
1392: }
1.1.1.3 root 1393: qemu_mod_timer(s->poll_timer,
1.1 root 1394: pcnet_get_next_poll_time(s,qemu_get_clock(vm_clock)));
1395: }
1396: }
1397:
1398:
1399: static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value)
1400: {
1401: uint16_t val = new_value;
1402: #ifdef PCNET_DEBUG_CSR
1403: printf("pcnet_csr_writew rap=%d val=0x%04x\n", rap, val);
1404: #endif
1405: switch (rap) {
1406: case 0:
1407: s->csr[0] &= ~(val & 0x7f00); /* Clear any interrupt flags */
1408:
1409: s->csr[0] = (s->csr[0] & ~0x0040) | (val & 0x0048);
1410:
1411: val = (val & 0x007f) | (s->csr[0] & 0x7f00);
1412:
1413: /* IFF STOP, STRT and INIT are set, clear STRT and INIT */
1414: if ((val&7) == 7)
1415: val &= ~3;
1416:
1417: if (!CSR_STOP(s) && (val & 4))
1418: pcnet_stop(s);
1419:
1420: if (!CSR_INIT(s) && (val & 1))
1421: pcnet_init(s);
1422:
1423: if (!CSR_STRT(s) && (val & 2))
1424: pcnet_start(s);
1425:
1.1.1.3 root 1426: if (CSR_TDMD(s))
1.1 root 1427: pcnet_transmit(s);
1428:
1429: return;
1430: case 1:
1431: case 2:
1432: case 8:
1433: case 9:
1434: case 10:
1435: case 11:
1436: case 12:
1437: case 13:
1438: case 14:
1439: case 15:
1440: case 18: /* CRBAL */
1441: case 19: /* CRBAU */
1442: case 20: /* CXBAL */
1443: case 21: /* CXBAU */
1444: case 22: /* NRBAU */
1445: case 23: /* NRBAU */
1446: case 24:
1447: case 25:
1448: case 26:
1449: case 27:
1450: case 28:
1451: case 29:
1452: case 30:
1453: case 31:
1454: case 32:
1455: case 33:
1456: case 34:
1457: case 35:
1458: case 36:
1459: case 37:
1460: case 38:
1461: case 39:
1462: case 40: /* CRBC */
1463: case 41:
1464: case 42: /* CXBC */
1465: case 43:
1466: case 44:
1467: case 45:
1468: case 46: /* POLL */
1469: case 47: /* POLLINT */
1470: case 72:
1471: case 74:
1472: case 76: /* RCVRL */
1473: case 78: /* XMTRL */
1474: case 112:
1475: if (CSR_STOP(s) || CSR_SPND(s))
1476: break;
1477: return;
1478: case 3:
1479: break;
1480: case 4:
1.1.1.3 root 1481: s->csr[4] &= ~(val & 0x026a);
1.1 root 1482: val &= ~0x026a; val |= s->csr[4] & 0x026a;
1483: break;
1484: case 5:
1.1.1.3 root 1485: s->csr[5] &= ~(val & 0x0a90);
1.1 root 1486: val &= ~0x0a90; val |= s->csr[5] & 0x0a90;
1487: break;
1488: case 16:
1489: pcnet_csr_writew(s,1,val);
1490: return;
1491: case 17:
1492: pcnet_csr_writew(s,2,val);
1493: return;
1494: case 58:
1495: pcnet_bcr_writew(s,BCR_SWS,val);
1496: break;
1497: default:
1498: return;
1499: }
1500: s->csr[rap] = val;
1501: }
1502:
1503: static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap)
1504: {
1505: uint32_t val;
1506: switch (rap) {
1507: case 0:
1508: pcnet_update_irq(s);
1509: val = s->csr[0];
1510: val |= (val & 0x7800) ? 0x8000 : 0;
1511: break;
1512: case 16:
1513: return pcnet_csr_readw(s,1);
1514: case 17:
1515: return pcnet_csr_readw(s,2);
1516: case 58:
1517: return pcnet_bcr_readw(s,BCR_SWS);
1518: case 88:
1519: val = s->csr[89];
1520: val <<= 16;
1521: val |= s->csr[88];
1522: break;
1523: default:
1524: val = s->csr[rap];
1525: }
1526: #ifdef PCNET_DEBUG_CSR
1527: printf("pcnet_csr_readw rap=%d val=0x%04x\n", rap, val);
1528: #endif
1529: return val;
1530: }
1531:
1532: static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val)
1533: {
1534: rap &= 127;
1535: #ifdef PCNET_DEBUG_BCR
1536: printf("pcnet_bcr_writew rap=%d val=0x%04x\n", rap, val);
1537: #endif
1538: switch (rap) {
1539: case BCR_SWS:
1540: if (!(CSR_STOP(s) || CSR_SPND(s)))
1541: return;
1542: val &= ~0x0300;
1543: switch (val & 0x00ff) {
1544: case 0:
1545: val |= 0x0200;
1546: break;
1547: case 1:
1548: val |= 0x0100;
1549: break;
1550: case 2:
1551: case 3:
1552: val |= 0x0300;
1553: break;
1554: default:
1555: printf("Bad SWSTYLE=0x%02x\n", val & 0xff);
1556: val = 0x0200;
1557: break;
1558: }
1559: #ifdef PCNET_DEBUG
1560: printf("BCR_SWS=0x%04x\n", val);
1561: #endif
1562: case BCR_LNKST:
1563: case BCR_LED1:
1564: case BCR_LED2:
1565: case BCR_LED3:
1566: case BCR_MC:
1567: case BCR_FDC:
1568: case BCR_BSBC:
1569: case BCR_EECAS:
1570: case BCR_PLAT:
1571: s->bcr[rap] = val;
1572: break;
1573: default:
1574: break;
1575: }
1576: }
1577:
1578: static uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap)
1579: {
1580: uint32_t val;
1581: rap &= 127;
1582: switch (rap) {
1583: case BCR_LNKST:
1584: case BCR_LED1:
1585: case BCR_LED2:
1586: case BCR_LED3:
1587: val = s->bcr[rap] & ~0x8000;
1588: val |= (val & 0x017f & s->lnkst) ? 0x8000 : 0;
1589: break;
1590: default:
1591: val = rap < 32 ? s->bcr[rap] : 0;
1592: break;
1593: }
1594: #ifdef PCNET_DEBUG_BCR
1595: printf("pcnet_bcr_readw rap=%d val=0x%04x\n", rap, val);
1596: #endif
1597: return val;
1598: }
1599:
1.1.1.3 root 1600: static void pcnet_h_reset(void *opaque)
1.1 root 1601: {
1.1.1.2 root 1602: PCNetState *s = opaque;
1.1 root 1603: int i;
1604: uint16_t checksum;
1605:
1606: /* Initialize the PROM */
1607:
1.1.1.6 root 1608: memcpy(s->prom, s->macaddr, 6);
1.1 root 1609: s->prom[12] = s->prom[13] = 0x00;
1610: s->prom[14] = s->prom[15] = 0x57;
1611:
1612: for (i = 0,checksum = 0; i < 16; i++)
1613: checksum += s->prom[i];
1614: *(uint16_t *)&s->prom[12] = cpu_to_le16(checksum);
1615:
1616:
1617: s->bcr[BCR_MSRDA] = 0x0005;
1618: s->bcr[BCR_MSWRA] = 0x0005;
1619: s->bcr[BCR_MC ] = 0x0002;
1620: s->bcr[BCR_LNKST] = 0x00c0;
1621: s->bcr[BCR_LED1 ] = 0x0084;
1622: s->bcr[BCR_LED2 ] = 0x0088;
1623: s->bcr[BCR_LED3 ] = 0x0090;
1624: s->bcr[BCR_FDC ] = 0x0000;
1625: s->bcr[BCR_BSBC ] = 0x9001;
1626: s->bcr[BCR_EECAS] = 0x0002;
1627: s->bcr[BCR_SWS ] = 0x0200;
1628: s->bcr[BCR_PLAT ] = 0xff06;
1629:
1630: pcnet_s_reset(s);
1631: }
1632:
1633: static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
1634: {
1635: PCNetState *s = opaque;
1636: #ifdef PCNET_DEBUG
1637: printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
1.1.1.3 root 1638: #endif
1.1 root 1639: /* Check APROMWE bit to enable write access */
1640: if (pcnet_bcr_readw(s,2) & 0x80)
1641: s->prom[addr & 15] = val;
1.1.1.3 root 1642: }
1.1 root 1643:
1644: static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
1645: {
1646: PCNetState *s = opaque;
1647: uint32_t val = s->prom[addr &= 15];
1648: #ifdef PCNET_DEBUG
1649: printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val);
1650: #endif
1651: return val;
1652: }
1653:
1654: static void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
1655: {
1656: PCNetState *s = opaque;
1657: pcnet_poll_timer(s);
1658: #ifdef PCNET_DEBUG_IO
1659: printf("pcnet_ioport_writew addr=0x%08x val=0x%04x\n", addr, val);
1660: #endif
1661: if (!BCR_DWIO(s)) {
1662: switch (addr & 0x0f) {
1663: case 0x00: /* RDP */
1664: pcnet_csr_writew(s, s->rap, val);
1665: break;
1666: case 0x02:
1667: s->rap = val & 0x7f;
1668: break;
1669: case 0x06:
1670: pcnet_bcr_writew(s, s->rap, val);
1671: break;
1672: }
1673: }
1674: pcnet_update_irq(s);
1675: }
1676:
1677: static uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr)
1678: {
1679: PCNetState *s = opaque;
1680: uint32_t val = -1;
1681: pcnet_poll_timer(s);
1682: if (!BCR_DWIO(s)) {
1683: switch (addr & 0x0f) {
1684: case 0x00: /* RDP */
1685: val = pcnet_csr_readw(s, s->rap);
1686: break;
1687: case 0x02:
1688: val = s->rap;
1689: break;
1690: case 0x04:
1691: pcnet_s_reset(s);
1692: val = 0;
1693: break;
1694: case 0x06:
1695: val = pcnet_bcr_readw(s, s->rap);
1696: break;
1697: }
1698: }
1699: pcnet_update_irq(s);
1700: #ifdef PCNET_DEBUG_IO
1701: printf("pcnet_ioport_readw addr=0x%08x val=0x%04x\n", addr, val & 0xffff);
1702: #endif
1703: return val;
1704: }
1705:
1706: static void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
1707: {
1708: PCNetState *s = opaque;
1709: pcnet_poll_timer(s);
1710: #ifdef PCNET_DEBUG_IO
1711: printf("pcnet_ioport_writel addr=0x%08x val=0x%08x\n", addr, val);
1712: #endif
1713: if (BCR_DWIO(s)) {
1714: switch (addr & 0x0f) {
1715: case 0x00: /* RDP */
1716: pcnet_csr_writew(s, s->rap, val & 0xffff);
1717: break;
1718: case 0x04:
1719: s->rap = val & 0x7f;
1720: break;
1721: case 0x0c:
1722: pcnet_bcr_writew(s, s->rap, val & 0xffff);
1723: break;
1724: }
1725: } else
1726: if ((addr & 0x0f) == 0) {
1727: /* switch device to dword i/o mode */
1728: pcnet_bcr_writew(s, BCR_BSBC, pcnet_bcr_readw(s, BCR_BSBC) | 0x0080);
1729: #ifdef PCNET_DEBUG_IO
1730: printf("device switched into dword i/o mode\n");
1.1.1.3 root 1731: #endif
1.1 root 1732: }
1733: pcnet_update_irq(s);
1734: }
1735:
1736: static uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr)
1737: {
1738: PCNetState *s = opaque;
1739: uint32_t val = -1;
1740: pcnet_poll_timer(s);
1.1.1.3 root 1741: if (BCR_DWIO(s)) {
1.1 root 1742: switch (addr & 0x0f) {
1743: case 0x00: /* RDP */
1744: val = pcnet_csr_readw(s, s->rap);
1745: break;
1746: case 0x04:
1747: val = s->rap;
1748: break;
1749: case 0x08:
1750: pcnet_s_reset(s);
1751: val = 0;
1752: break;
1753: case 0x0c:
1754: val = pcnet_bcr_readw(s, s->rap);
1755: break;
1756: }
1757: }
1758: pcnet_update_irq(s);
1759: #ifdef PCNET_DEBUG_IO
1760: printf("pcnet_ioport_readl addr=0x%08x val=0x%08x\n", addr, val);
1761: #endif
1762: return val;
1763: }
1764:
1.1.1.3 root 1765: static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
1.1 root 1766: uint32_t addr, uint32_t size, int type)
1767: {
1.1.1.6 root 1768: PCNetState *d = &((PCIPCNetState *)pci_dev)->state;
1.1 root 1769:
1770: #ifdef PCNET_DEBUG_IO
1771: printf("pcnet_ioport_map addr=0x%04x size=0x%04x\n", addr, size);
1772: #endif
1773:
1774: register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
1775: register_ioport_read(addr, 16, 1, pcnet_aprom_readb, d);
1.1.1.3 root 1776:
1.1 root 1777: register_ioport_write(addr + 0x10, 0x10, 2, pcnet_ioport_writew, d);
1778: register_ioport_read(addr + 0x10, 0x10, 2, pcnet_ioport_readw, d);
1779: register_ioport_write(addr + 0x10, 0x10, 4, pcnet_ioport_writel, d);
1780: register_ioport_read(addr + 0x10, 0x10, 4, pcnet_ioport_readl, d);
1781: }
1782:
1783: static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1784: {
1785: PCNetState *d = opaque;
1786: #ifdef PCNET_DEBUG_IO
1.1.1.4 root 1787: printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr,
1788: val);
1.1 root 1789: #endif
1790: if (!(addr & 0x10))
1791: pcnet_aprom_writeb(d, addr & 0x0f, val);
1792: }
1793:
1.1.1.3 root 1794: static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
1.1 root 1795: {
1796: PCNetState *d = opaque;
1797: uint32_t val = -1;
1798: if (!(addr & 0x10))
1799: val = pcnet_aprom_readb(d, addr & 0x0f);
1800: #ifdef PCNET_DEBUG_IO
1.1.1.4 root 1801: printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr,
1802: val & 0xff);
1.1 root 1803: #endif
1804: return val;
1805: }
1806:
1807: static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1808: {
1809: PCNetState *d = opaque;
1810: #ifdef PCNET_DEBUG_IO
1.1.1.4 root 1811: printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr,
1812: val);
1.1 root 1813: #endif
1814: if (addr & 0x10)
1815: pcnet_ioport_writew(d, addr & 0x0f, val);
1816: else {
1817: addr &= 0x0f;
1818: pcnet_aprom_writeb(d, addr, val & 0xff);
1819: pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
1820: }
1821: }
1822:
1.1.1.3 root 1823: static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
1.1 root 1824: {
1825: PCNetState *d = opaque;
1826: uint32_t val = -1;
1827: if (addr & 0x10)
1828: val = pcnet_ioport_readw(d, addr & 0x0f);
1829: else {
1830: addr &= 0x0f;
1831: val = pcnet_aprom_readb(d, addr+1);
1832: val <<= 8;
1833: val |= pcnet_aprom_readb(d, addr);
1834: }
1835: #ifdef PCNET_DEBUG_IO
1.1.1.4 root 1836: printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr,
1837: val & 0xffff);
1.1 root 1838: #endif
1839: return val;
1840: }
1841:
1842: static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1843: {
1844: PCNetState *d = opaque;
1845: #ifdef PCNET_DEBUG_IO
1.1.1.4 root 1846: printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr,
1847: val);
1.1 root 1848: #endif
1849: if (addr & 0x10)
1850: pcnet_ioport_writel(d, addr & 0x0f, val);
1851: else {
1852: addr &= 0x0f;
1853: pcnet_aprom_writeb(d, addr, val & 0xff);
1854: pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
1855: pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
1856: pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
1857: }
1858: }
1859:
1.1.1.3 root 1860: static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
1.1 root 1861: {
1862: PCNetState *d = opaque;
1863: uint32_t val;
1864: if (addr & 0x10)
1865: val = pcnet_ioport_readl(d, addr & 0x0f);
1866: else {
1867: addr &= 0x0f;
1868: val = pcnet_aprom_readb(d, addr+3);
1869: val <<= 8;
1870: val |= pcnet_aprom_readb(d, addr+2);
1871: val <<= 8;
1872: val |= pcnet_aprom_readb(d, addr+1);
1873: val <<= 8;
1874: val |= pcnet_aprom_readb(d, addr);
1875: }
1876: #ifdef PCNET_DEBUG_IO
1.1.1.4 root 1877: printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr,
1878: val);
1.1 root 1879: #endif
1880: return val;
1881: }
1882:
1883:
1.1.1.2 root 1884: static void pcnet_save(QEMUFile *f, void *opaque)
1885: {
1886: PCNetState *s = opaque;
1887: unsigned int i;
1888:
1889: if (s->pci_dev)
1890: pci_device_save(s->pci_dev, f);
1891:
1.1.1.4 root 1892: qemu_put_sbe32(f, s->rap);
1893: qemu_put_sbe32(f, s->isr);
1894: qemu_put_sbe32(f, s->lnkst);
1.1.1.2 root 1895: qemu_put_be32s(f, &s->rdra);
1896: qemu_put_be32s(f, &s->tdra);
1897: qemu_put_buffer(f, s->prom, 16);
1898: for (i = 0; i < 128; i++)
1899: qemu_put_be16s(f, &s->csr[i]);
1900: for (i = 0; i < 32; i++)
1901: qemu_put_be16s(f, &s->bcr[i]);
1902: qemu_put_be64s(f, &s->timer);
1.1.1.4 root 1903: qemu_put_sbe32(f, s->xmit_pos);
1904: qemu_put_sbe32(f, s->recv_pos);
1.1.1.2 root 1905: qemu_put_buffer(f, s->buffer, 4096);
1.1.1.4 root 1906: qemu_put_sbe32(f, s->tx_busy);
1.1.1.2 root 1907: qemu_put_timer(f, s->poll_timer);
1908: }
1909:
1910: static int pcnet_load(QEMUFile *f, void *opaque, int version_id)
1911: {
1912: PCNetState *s = opaque;
1913: int i, ret;
1914:
1915: if (version_id != 2)
1916: return -EINVAL;
1917:
1918: if (s->pci_dev) {
1919: ret = pci_device_load(s->pci_dev, f);
1920: if (ret < 0)
1921: return ret;
1922: }
1923:
1.1.1.4 root 1924: qemu_get_sbe32s(f, &s->rap);
1925: qemu_get_sbe32s(f, &s->isr);
1926: qemu_get_sbe32s(f, &s->lnkst);
1.1.1.2 root 1927: qemu_get_be32s(f, &s->rdra);
1928: qemu_get_be32s(f, &s->tdra);
1929: qemu_get_buffer(f, s->prom, 16);
1930: for (i = 0; i < 128; i++)
1931: qemu_get_be16s(f, &s->csr[i]);
1932: for (i = 0; i < 32; i++)
1933: qemu_get_be16s(f, &s->bcr[i]);
1934: qemu_get_be64s(f, &s->timer);
1.1.1.4 root 1935: qemu_get_sbe32s(f, &s->xmit_pos);
1936: qemu_get_sbe32s(f, &s->recv_pos);
1.1.1.2 root 1937: qemu_get_buffer(f, s->buffer, 4096);
1.1.1.4 root 1938: qemu_get_sbe32s(f, &s->tx_busy);
1.1.1.2 root 1939: qemu_get_timer(f, s->poll_timer);
1940:
1941: return 0;
1942: }
1943:
1.1.1.5 root 1944: static void pcnet_common_cleanup(PCNetState *d)
1945: {
1946: unregister_savevm("pcnet", d);
1947:
1948: qemu_del_timer(d->poll_timer);
1949: qemu_free_timer(d->poll_timer);
1950: }
1951:
1.1.1.6 root 1952: static void pcnet_common_init(DeviceState *dev, PCNetState *s,
1953: NetCleanup *cleanup)
1.1.1.2 root 1954: {
1.1.1.6 root 1955: s->poll_timer = qemu_new_timer(vm_clock, pcnet_poll_timer, s);
1.1.1.2 root 1956:
1.1.1.6 root 1957: qdev_get_macaddr(dev, s->macaddr);
1958: s->vc = qdev_get_vlan_client(dev,
1959: pcnet_can_receive, pcnet_receive, NULL,
1960: cleanup, s);
1961: pcnet_h_reset(s);
1962: register_savevm("pcnet", -1, 2, pcnet_save, pcnet_load, s);
1.1.1.2 root 1963: }
1964:
1965: /* PCI interface */
1966:
1.1 root 1967: static CPUWriteMemoryFunc *pcnet_mmio_write[] = {
1968: (CPUWriteMemoryFunc *)&pcnet_mmio_writeb,
1969: (CPUWriteMemoryFunc *)&pcnet_mmio_writew,
1970: (CPUWriteMemoryFunc *)&pcnet_mmio_writel
1971: };
1972:
1973: static CPUReadMemoryFunc *pcnet_mmio_read[] = {
1974: (CPUReadMemoryFunc *)&pcnet_mmio_readb,
1975: (CPUReadMemoryFunc *)&pcnet_mmio_readw,
1976: (CPUReadMemoryFunc *)&pcnet_mmio_readl
1977: };
1978:
1.1.1.3 root 1979: static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
1.1 root 1980: uint32_t addr, uint32_t size, int type)
1981: {
1.1.1.6 root 1982: PCIPCNetState *d = (PCIPCNetState *)pci_dev;
1.1 root 1983:
1984: #ifdef PCNET_DEBUG_IO
1.1.1.4 root 1985: printf("pcnet_mmio_map addr=0x%08x 0x%08x\n", addr, size);
1.1 root 1986: #endif
1987:
1.1.1.6 root 1988: cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->state.mmio_index);
1.1 root 1989: }
1990:
1.1.1.2 root 1991: static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
1992: uint8_t *buf, int len, int do_bswap)
1993: {
1994: cpu_physical_memory_write(addr, buf, len);
1995: }
1996:
1997: static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
1998: uint8_t *buf, int len, int do_bswap)
1999: {
2000: cpu_physical_memory_read(addr, buf, len);
2001: }
2002:
1.1.1.5 root 2003: static void pci_pcnet_cleanup(VLANClientState *vc)
2004: {
2005: PCNetState *d = vc->opaque;
2006:
2007: pcnet_common_cleanup(d);
2008: }
2009:
2010: static int pci_pcnet_uninit(PCIDevice *dev)
2011: {
1.1.1.6 root 2012: PCIPCNetState *d = (PCIPCNetState *)dev;
1.1.1.5 root 2013:
1.1.1.6 root 2014: cpu_unregister_io_memory(d->state.mmio_index);
1.1.1.5 root 2015:
2016: return 0;
2017: }
2018:
1.1.1.6 root 2019: static void pci_pcnet_init(PCIDevice *pci_dev)
1.1 root 2020: {
1.1.1.6 root 2021: PCIPCNetState *d = (PCIPCNetState *)pci_dev;
2022: PCNetState *s = &d->state;
1.1 root 2023: uint8_t *pci_conf;
2024:
2025: #if 0
1.1.1.3 root 2026: printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
1.1 root 2027: sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
2028: #endif
2029:
1.1.1.6 root 2030: pci_dev->unregister = pci_pcnet_uninit;
1.1.1.5 root 2031:
1.1.1.6 root 2032: pci_conf = pci_dev->config;
1.1.1.3 root 2033:
1.1.1.4 root 2034: pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_AMD);
2035: pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_AMD_LANCE);
1.1.1.3 root 2036: *(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007);
1.1 root 2037: *(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);
2038: pci_conf[0x08] = 0x10;
2039: pci_conf[0x09] = 0x00;
1.1.1.4 root 2040: pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
1.1.1.6 root 2041: pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
1.1.1.3 root 2042:
1.1 root 2043: *(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);
2044: *(uint32_t *)&pci_conf[0x14] = cpu_to_le32(0x00000000);
1.1.1.3 root 2045:
1.1 root 2046: pci_conf[0x3d] = 1; // interrupt pin 0
2047: pci_conf[0x3e] = 0x06;
2048: pci_conf[0x3f] = 0xff;
2049:
2050: /* Handler for memory-mapped I/O */
1.1.1.6 root 2051: s->mmio_index =
2052: cpu_register_io_memory(pcnet_mmio_read, pcnet_mmio_write, &d->state);
1.1 root 2053:
1.1.1.6 root 2054: pci_register_bar((PCIDevice *)d, 0, PCNET_IOPORT_SIZE,
1.1 root 2055: PCI_ADDRESS_SPACE_IO, pcnet_ioport_map);
1.1.1.3 root 2056:
1.1.1.6 root 2057: pci_register_bar((PCIDevice *)d, 1, PCNET_PNPMMIO_SIZE,
1.1 root 2058: PCI_ADDRESS_SPACE_MEM, pcnet_mmio_map);
1.1.1.3 root 2059:
1.1.1.6 root 2060: s->irq = pci_dev->irq[0];
2061: s->phys_mem_read = pci_physical_memory_read;
2062: s->phys_mem_write = pci_physical_memory_write;
2063: s->pci_dev = pci_dev;
1.1.1.5 root 2064:
1.1.1.6 root 2065: pcnet_common_init(&pci_dev->qdev, s, pci_pcnet_cleanup);
1.1.1.2 root 2066: }
1.1 root 2067:
1.1.1.2 root 2068: /* SPARC32 interface */
1.1 root 2069:
1.1.1.2 root 2070: #if defined (TARGET_SPARC) && !defined(TARGET_SPARC64) // Avoid compile failure
1.1.1.3 root 2071: #include "sun4m.h"
1.1.1.2 root 2072:
1.1.1.3 root 2073: static void parent_lance_reset(void *opaque, int irq, int level)
2074: {
1.1.1.6 root 2075: SysBusPCNetState *d = opaque;
1.1.1.3 root 2076: if (level)
1.1.1.6 root 2077: pcnet_h_reset(&d->state);
1.1.1.3 root 2078: }
1.1.1.2 root 2079:
1.1.1.3 root 2080: static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
2081: uint32_t val)
2082: {
1.1.1.6 root 2083: SysBusPCNetState *d = opaque;
1.1.1.3 root 2084: #ifdef PCNET_DEBUG_IO
2085: printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr,
2086: val & 0xffff);
2087: #endif
1.1.1.6 root 2088: pcnet_ioport_writew(&d->state, addr, val & 0xffff);
1.1.1.3 root 2089: }
1.1.1.2 root 2090:
1.1.1.3 root 2091: static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
1.1.1.2 root 2092: {
1.1.1.6 root 2093: SysBusPCNetState *d = opaque;
1.1.1.3 root 2094: uint32_t val;
2095:
1.1.1.6 root 2096: val = pcnet_ioport_readw(&d->state, addr);
1.1.1.3 root 2097: #ifdef PCNET_DEBUG_IO
1.1.1.4 root 2098: printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr,
1.1.1.3 root 2099: val & 0xffff);
2100: #endif
1.1.1.2 root 2101:
1.1.1.3 root 2102: return val & 0xffff;
1.1.1.2 root 2103: }
2104:
1.1.1.3 root 2105: static CPUReadMemoryFunc *lance_mem_read[3] = {
2106: NULL,
2107: lance_mem_readw,
2108: NULL,
2109: };
2110:
2111: static CPUWriteMemoryFunc *lance_mem_write[3] = {
2112: NULL,
2113: lance_mem_writew,
2114: NULL,
2115: };
2116:
1.1.1.5 root 2117: static void lance_cleanup(VLANClientState *vc)
2118: {
2119: PCNetState *d = vc->opaque;
2120:
2121: pcnet_common_cleanup(d);
2122: }
2123:
1.1.1.6 root 2124: static void lance_init(SysBusDevice *dev)
1.1.1.2 root 2125: {
1.1.1.6 root 2126: SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
2127: PCNetState *s = &d->state;
1.1.1.2 root 2128:
1.1.1.6 root 2129: s->mmio_index =
2130: cpu_register_io_memory(lance_mem_read, lance_mem_write, d);
1.1.1.4 root 2131:
1.1.1.6 root 2132: qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
1.1.1.2 root 2133:
1.1.1.6 root 2134: sysbus_init_mmio(dev, 4, s->mmio_index);
1.1.1.2 root 2135:
1.1.1.6 root 2136: sysbus_init_irq(dev, &s->irq);
1.1.1.3 root 2137:
1.1.1.6 root 2138: s->phys_mem_read = ledma_memory_read;
2139: s->phys_mem_write = ledma_memory_write;
1.1.1.3 root 2140:
1.1.1.6 root 2141: pcnet_common_init(&dev->qdev, s, lance_cleanup);
2142: }
1.1.1.2 root 2143:
1.1.1.6 root 2144: static SysBusDeviceInfo lance_info = {
2145: .init = lance_init,
2146: .qdev.name = "lance",
2147: .qdev.size = sizeof(SysBusPCNetState),
2148: .qdev.props = (Property[]) {
2149: {
2150: .name = "dma",
2151: .info = &qdev_prop_ptr,
2152: .offset = offsetof(SysBusPCNetState, state.dma_opaque),
2153: },
2154: {/* end of list */}
2155: }
2156: };
1.1.1.2 root 2157:
2158: #endif /* TARGET_SPARC */
1.1.1.6 root 2159:
2160: static PCIDeviceInfo pcnet_info = {
2161: .qdev.name = "pcnet",
2162: .qdev.size = sizeof(PCIPCNetState),
2163: .init = pci_pcnet_init,
2164: };
2165:
2166: static void pcnet_register_devices(void)
2167: {
2168: pci_qdev_register(&pcnet_info);
2169: #if defined (TARGET_SPARC) && !defined(TARGET_SPARC64)
2170: sysbus_register_withprop(&lance_info);
2171: #endif
2172: }
2173:
2174: device_init(pcnet_register_devices)
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