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1.1 root 1: /*
2: * QEMU i440FX/PIIX3 PCI Bridge Emulation
3: *
4: * Copyright (c) 2006 Fabrice Bellard
1.1.1.3 ! root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24:
1.1.1.3 ! root 25: #include "hw.h"
! 26: #include "pc.h"
! 27: #include "pci.h"
! 28:
1.1 root 29: typedef uint32_t pci_addr_t;
30: #include "pci_host.h"
31:
32: typedef PCIHostState I440FXState;
33:
34: static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
35: {
36: I440FXState *s = opaque;
37: s->config_reg = val;
38: }
39:
40: static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
41: {
42: I440FXState *s = opaque;
43: return s->config_reg;
44: }
45:
1.1.1.3 ! root 46: static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);
1.1 root 47:
1.1.1.2 root 48: /* return the global irq number corresponding to a given device irq
49: pin. We could also use the bus number to have a more precise
50: mapping. */
51: static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
52: {
53: int slot_addend;
54: slot_addend = (pci_dev->devfn >> 3) - 1;
55: return (irq_num + slot_addend) & 3;
56: }
57:
58: static uint32_t isa_page_descs[384 / 4];
59: static uint8_t smm_enabled;
1.1.1.3 ! root 60: static int pci_irq_levels[4];
1.1.1.2 root 61:
62: static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)
63: {
64: uint32_t addr;
65:
66: // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
67: switch(r) {
68: case 3:
69: /* RAM */
1.1.1.3 ! root 70: cpu_register_physical_memory(start, end - start,
1.1.1.2 root 71: start);
72: break;
73: case 1:
74: /* ROM (XXX: not quite correct) */
1.1.1.3 ! root 75: cpu_register_physical_memory(start, end - start,
1.1.1.2 root 76: start | IO_MEM_ROM);
77: break;
78: case 2:
79: case 0:
80: /* XXX: should distinguish read/write cases */
81: for(addr = start; addr < end; addr += 4096) {
1.1.1.3 ! root 82: cpu_register_physical_memory(addr, 4096,
1.1.1.2 root 83: isa_page_descs[(addr - 0xa0000) >> 12]);
84: }
85: break;
86: }
87: }
88:
89: static void i440fx_update_memory_mappings(PCIDevice *d)
90: {
91: int i, r;
92: uint32_t smram, addr;
93:
94: update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);
95: for(i = 0; i < 12; i++) {
96: r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
97: update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
98: }
99: smram = d->config[0x72];
100: if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
101: cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
102: } else {
103: for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
1.1.1.3 ! root 104: cpu_register_physical_memory(addr, 4096,
1.1.1.2 root 105: isa_page_descs[(addr - 0xa0000) >> 12]);
106: }
107: }
108: }
109:
110: void i440fx_set_smm(PCIDevice *d, int val)
111: {
112: val = (val != 0);
113: if (smm_enabled != val) {
114: smm_enabled = val;
115: i440fx_update_memory_mappings(d);
116: }
117: }
118:
119:
120: /* XXX: suppress when better memory API. We make the assumption that
121: no device (in particular the VGA) changes the memory mappings in
122: the 0xa0000-0x100000 range */
123: void i440fx_init_memory_mappings(PCIDevice *d)
124: {
125: int i;
126: for(i = 0; i < 96; i++) {
127: isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
128: }
129: }
130:
1.1.1.3 ! root 131: static void i440fx_write_config(PCIDevice *d,
1.1.1.2 root 132: uint32_t address, uint32_t val, int len)
133: {
134: /* XXX: implement SMRAM.D_LOCK */
135: pci_default_write_config(d, address, val, len);
136: if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
137: i440fx_update_memory_mappings(d);
138: }
139:
140: static void i440fx_save(QEMUFile* f, void *opaque)
141: {
142: PCIDevice *d = opaque;
1.1.1.3 ! root 143: int i;
! 144:
1.1.1.2 root 145: pci_device_save(d, f);
146: qemu_put_8s(f, &smm_enabled);
1.1.1.3 ! root 147:
! 148: for (i = 0; i < 4; i++)
! 149: qemu_put_be32(f, pci_irq_levels[i]);
1.1.1.2 root 150: }
151:
152: static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
153: {
154: PCIDevice *d = opaque;
1.1.1.3 ! root 155: int ret, i;
1.1.1.2 root 156:
1.1.1.3 ! root 157: if (version_id > 2)
1.1.1.2 root 158: return -EINVAL;
159: ret = pci_device_load(d, f);
160: if (ret < 0)
161: return ret;
162: i440fx_update_memory_mappings(d);
163: qemu_get_8s(f, &smm_enabled);
1.1.1.3 ! root 164:
! 165: if (version_id >= 2)
! 166: for (i = 0; i < 4; i++)
! 167: pci_irq_levels[i] = qemu_get_be32(f);
! 168:
1.1.1.2 root 169: return 0;
170: }
171:
1.1.1.3 ! root 172: PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
1.1 root 173: {
174: PCIBus *b;
175: PCIDevice *d;
176: I440FXState *s;
177:
178: s = qemu_mallocz(sizeof(I440FXState));
1.1.1.3 ! root 179: b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
1.1 root 180: s->bus = b;
181:
182: register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
183: register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
184:
185: register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
186: register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
187: register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
188: register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
189: register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
190: register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
191:
1.1.1.3 ! root 192: d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
1.1.1.2 root 193: NULL, i440fx_write_config);
1.1 root 194:
195: d->config[0x00] = 0x86; // vendor_id
196: d->config[0x01] = 0x80;
197: d->config[0x02] = 0x37; // device_id
198: d->config[0x03] = 0x12;
199: d->config[0x08] = 0x02; // revision
200: d->config[0x0a] = 0x00; // class_sub = host2pci
201: d->config[0x0b] = 0x06; // class_base = PCI_bridge
202: d->config[0x0e] = 0x00; // header_type
1.1.1.2 root 203:
204: d->config[0x72] = 0x02; /* SMRAM */
205:
1.1.1.3 ! root 206: register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);
1.1.1.2 root 207: *pi440fx_state = d;
1.1 root 208: return b;
209: }
210:
211: /* PIIX3 PCI to ISA bridge */
212:
1.1.1.2 root 213: PCIDevice *piix3_dev;
214: PCIDevice *piix4_dev;
1.1 root 215:
216: /* just used for simpler irq handling. */
217: #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
218:
1.1.1.3 ! root 219: static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
1.1 root 220: {
1.1.1.2 root 221: int i, pic_irq, pic_level;
1.1 root 222:
1.1.1.3 ! root 223: piix3_dev->config[0x60 + irq_num] &= ~0x80; // enable bit
1.1.1.2 root 224: pci_irq_levels[irq_num] = level;
1.1 root 225:
226: /* now we change the pic irq level according to the piix irq mappings */
227: /* XXX: optimize */
228: pic_irq = piix3_dev->config[0x60 + irq_num];
229: if (pic_irq < 16) {
1.1.1.2 root 230: /* The pic level is the logical OR of all the PCI irqs mapped
1.1 root 231: to it */
232: pic_level = 0;
1.1.1.2 root 233: for (i = 0; i < 4; i++) {
234: if (pic_irq == piix3_dev->config[0x60 + i])
235: pic_level |= pci_irq_levels[i];
236: }
1.1.1.3 ! root 237: qemu_set_irq(pic[pic_irq], pic_level);
1.1 root 238: }
239: }
240:
241: static void piix3_reset(PCIDevice *d)
242: {
243: uint8_t *pci_conf = d->config;
244:
245: pci_conf[0x04] = 0x07; // master, memory and I/O
246: pci_conf[0x05] = 0x00;
247: pci_conf[0x06] = 0x00;
248: pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
249: pci_conf[0x4c] = 0x4d;
250: pci_conf[0x4e] = 0x03;
251: pci_conf[0x4f] = 0x00;
252: pci_conf[0x60] = 0x80;
253: pci_conf[0x69] = 0x02;
254: pci_conf[0x70] = 0x80;
255: pci_conf[0x76] = 0x0c;
256: pci_conf[0x77] = 0x0c;
257: pci_conf[0x78] = 0x02;
258: pci_conf[0x79] = 0x00;
259: pci_conf[0x80] = 0x00;
260: pci_conf[0x82] = 0x00;
261: pci_conf[0xa0] = 0x08;
1.1.1.2 root 262: pci_conf[0xa2] = 0x00;
263: pci_conf[0xa3] = 0x00;
264: pci_conf[0xa4] = 0x00;
265: pci_conf[0xa5] = 0x00;
266: pci_conf[0xa6] = 0x00;
267: pci_conf[0xa7] = 0x00;
268: pci_conf[0xa8] = 0x0f;
269: pci_conf[0xaa] = 0x00;
270: pci_conf[0xab] = 0x00;
271: pci_conf[0xac] = 0x00;
272: pci_conf[0xae] = 0x00;
273: }
274:
275: static void piix4_reset(PCIDevice *d)
276: {
277: uint8_t *pci_conf = d->config;
278:
279: pci_conf[0x04] = 0x07; // master, memory and I/O
280: pci_conf[0x05] = 0x00;
281: pci_conf[0x06] = 0x00;
282: pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
283: pci_conf[0x4c] = 0x4d;
284: pci_conf[0x4e] = 0x03;
285: pci_conf[0x4f] = 0x00;
286: pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
287: pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
288: pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
289: pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
290: pci_conf[0x69] = 0x02;
291: pci_conf[0x70] = 0x80;
292: pci_conf[0x76] = 0x0c;
293: pci_conf[0x77] = 0x0c;
294: pci_conf[0x78] = 0x02;
295: pci_conf[0x79] = 0x00;
296: pci_conf[0x80] = 0x00;
297: pci_conf[0x82] = 0x00;
1.1 root 298: pci_conf[0xa0] = 0x08;
299: pci_conf[0xa2] = 0x00;
300: pci_conf[0xa3] = 0x00;
301: pci_conf[0xa4] = 0x00;
302: pci_conf[0xa5] = 0x00;
303: pci_conf[0xa6] = 0x00;
304: pci_conf[0xa7] = 0x00;
305: pci_conf[0xa8] = 0x0f;
306: pci_conf[0xaa] = 0x00;
307: pci_conf[0xab] = 0x00;
308: pci_conf[0xac] = 0x00;
309: pci_conf[0xae] = 0x00;
310: }
311:
1.1.1.2 root 312: static void piix_save(QEMUFile* f, void *opaque)
313: {
314: PCIDevice *d = opaque;
315: pci_device_save(d, f);
316: }
317:
318: static int piix_load(QEMUFile* f, void *opaque, int version_id)
319: {
320: PCIDevice *d = opaque;
321: if (version_id != 2)
322: return -EINVAL;
323: return pci_device_load(d, f);
324: }
325:
326: int piix3_init(PCIBus *bus, int devfn)
1.1 root 327: {
1.1.1.2 root 328: PCIDevice *d;
329: uint8_t *pci_conf;
1.1 root 330:
1.1.1.2 root 331: d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice),
332: devfn, NULL, NULL);
333: register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
1.1 root 334:
1.1.1.2 root 335: piix3_dev = d;
336: pci_conf = d->config;
1.1 root 337:
1.1.1.2 root 338: pci_conf[0x00] = 0x86; // Intel
339: pci_conf[0x01] = 0x80;
340: pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
341: pci_conf[0x03] = 0x70;
342: pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
343: pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
344: pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
1.1 root 345:
1.1.1.2 root 346: piix3_reset(d);
347: return d->devfn;
1.1 root 348: }
349:
1.1.1.2 root 350: int piix4_init(PCIBus *bus, int devfn)
1.1 root 351: {
1.1.1.2 root 352: PCIDevice *d;
353: uint8_t *pci_conf;
1.1 root 354:
1.1.1.2 root 355: d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice),
356: devfn, NULL, NULL);
357: register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);
1.1 root 358:
1.1.1.2 root 359: piix4_dev = d;
360: pci_conf = d->config;
1.1 root 361:
1.1.1.2 root 362: pci_conf[0x00] = 0x86; // Intel
363: pci_conf[0x01] = 0x80;
364: pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
365: pci_conf[0x03] = 0x71;
366: pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
367: pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
368: pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
1.1 root 369:
1.1.1.2 root 370: piix4_reset(d);
371: return d->devfn;
1.1 root 372: }
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