Diff for /qemu/hw/ppc.h between versions 1.1.1.3 and 1.1.1.4

version 1.1.1.3, 2018/04/24 17:37:07 version 1.1.1.4, 2018/04/24 18:28:06
Line 13  static inline void clk_setup (clk_setup_ Line 13  static inline void clk_setup (clk_setup_
   
 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);  clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
 /* Embedded PowerPC DCR management */  /* Embedded PowerPC DCR management */
 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);  typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);  typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),  int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
                   int (*dcr_write_error)(int dcrn));                    int (*dcr_write_error)(int dcrn));
 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,  int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
Line 40  enum { Line 40  enum {
     ARCH_PREP = 0,      ARCH_PREP = 0,
     ARCH_MAC99,      ARCH_MAC99,
     ARCH_HEATHROW,      ARCH_HEATHROW,
       ARCH_MAC99_U3,
 };  };
   
 #define FW_CFG_PPC_WIDTH        (FW_CFG_ARCH_LOCAL + 0x00)  #define FW_CFG_PPC_WIDTH        (FW_CFG_ARCH_LOCAL + 0x00)
 #define FW_CFG_PPC_HEIGHT       (FW_CFG_ARCH_LOCAL + 0x01)  #define FW_CFG_PPC_HEIGHT       (FW_CFG_ARCH_LOCAL + 0x01)
 #define FW_CFG_PPC_DEPTH        (FW_CFG_ARCH_LOCAL + 0x02)  #define FW_CFG_PPC_DEPTH        (FW_CFG_ARCH_LOCAL + 0x02)
   #define FW_CFG_PPC_TBFREQ       (FW_CFG_ARCH_LOCAL + 0x03)
   
 #define PPC_SERIAL_MM_BAUDBASE 399193  #define PPC_SERIAL_MM_BAUDBASE 399193

Removed from v.1.1.1.3  
changed lines
  Added in v.1.1.1.4


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