version 1.1.1.4, 2018/04/24 18:28:06
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version 1.1.1.6, 2018/04/24 18:59:22
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Line 19 int ppc_dcr_init (CPUState *env, int (*d
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Line 19 int ppc_dcr_init (CPUState *env, int (*d
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int (*dcr_write_error)(int dcrn)); |
int (*dcr_write_error)(int dcrn)); |
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
dcr_read_cb drc_read, dcr_write_cb dcr_write); |
dcr_read_cb drc_read, dcr_write_cb dcr_write); |
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq); |
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq, |
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unsigned int decr_excp); |
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/* Embedded PowerPC reset */ |
/* Embedded PowerPC reset */ |
void ppc40x_core_reset (CPUState *env); |
void ppc40x_core_reset (CPUState *env); |
void ppc40x_chip_reset (CPUState *env); |
void ppc40x_chip_reset (CPUState *env); |
Line 34 void ppc40x_irq_init (CPUState *env);
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Line 36 void ppc40x_irq_init (CPUState *env);
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void ppce500_irq_init (CPUState *env); |
void ppce500_irq_init (CPUState *env); |
void ppc6xx_irq_init (CPUState *env); |
void ppc6xx_irq_init (CPUState *env); |
void ppc970_irq_init (CPUState *env); |
void ppc970_irq_init (CPUState *env); |
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void ppcPOWER7_irq_init (CPUState *env); |
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/* PPC machines for OpenBIOS */ |
/* PPC machines for OpenBIOS */ |
enum { |
enum { |
Line 47 enum {
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Line 50 enum {
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#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03) |
#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03) |
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#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05) |
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#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06) |
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#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07) |
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#define PPC_SERIAL_MM_BAUDBASE 399193 |
#define PPC_SERIAL_MM_BAUDBASE 399193 |