version 1.1.1.4, 2018/04/24 18:28:06
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version 1.1.1.7, 2018/04/24 19:26:51
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void ppc_set_irq (CPUState *env, int n_IRQ, int level); |
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/* PowerPC hardware exceptions management helpers */ |
/* PowerPC hardware exceptions management helpers */ |
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); |
typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); |
typedef struct clk_setup_t clk_setup_t; |
typedef struct clk_setup_t clk_setup_t; |
Line 11 static inline void clk_setup (clk_setup_
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Line 13 static inline void clk_setup (clk_setup_
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(*clk->cb)(clk->opaque, freq); |
(*clk->cb)(clk->opaque, freq); |
} |
} |
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struct ppc_tb_t { |
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/* Time base management */ |
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int64_t tb_offset; /* Compensation */ |
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int64_t atb_offset; /* Compensation */ |
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uint32_t tb_freq; /* TB frequency */ |
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/* Decrementer management */ |
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uint64_t decr_next; /* Tick for next decr interrupt */ |
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uint32_t decr_freq; /* decrementer frequency */ |
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struct QEMUTimer *decr_timer; |
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/* Hypervisor decrementer management */ |
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uint64_t hdecr_next; /* Tick for next hdecr interrupt */ |
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struct QEMUTimer *hdecr_timer; |
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uint64_t purr_load; |
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uint64_t purr_start; |
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void *opaque; |
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uint32_t flags; |
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}; |
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/* PPC Timers flags */ |
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#define PPC_TIMER_BOOKE (1 << 0) /* Enable Booke support */ |
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#define PPC_TIMER_E500 (1 << 1) /* Enable e500 support */ |
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#define PPC_DECR_UNDERFLOW_TRIGGERED (1 << 2) /* Decr interrupt triggered when |
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* the most significant bit |
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* changes from 0 to 1. |
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*/ |
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#define PPC_DECR_ZERO_TRIGGERED (1 << 3) /* Decr interrupt triggered when |
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* the decrementer reaches zero. |
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*/ |
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uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset); |
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); |
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); |
/* Embedded PowerPC DCR management */ |
/* Embedded PowerPC DCR management */ |
typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn); |
typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn); |
Line 19 int ppc_dcr_init (CPUState *env, int (*d
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Line 51 int ppc_dcr_init (CPUState *env, int (*d
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int (*dcr_write_error)(int dcrn)); |
int (*dcr_write_error)(int dcrn)); |
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
dcr_read_cb drc_read, dcr_write_cb dcr_write); |
dcr_read_cb drc_read, dcr_write_cb dcr_write); |
clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq); |
clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq, |
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unsigned int decr_excp); |
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/* Embedded PowerPC reset */ |
/* Embedded PowerPC reset */ |
void ppc40x_core_reset (CPUState *env); |
void ppc40x_core_reset (CPUState *env); |
void ppc40x_chip_reset (CPUState *env); |
void ppc40x_chip_reset (CPUState *env); |
Line 34 void ppc40x_irq_init (CPUState *env);
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Line 68 void ppc40x_irq_init (CPUState *env);
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void ppce500_irq_init (CPUState *env); |
void ppce500_irq_init (CPUState *env); |
void ppc6xx_irq_init (CPUState *env); |
void ppc6xx_irq_init (CPUState *env); |
void ppc970_irq_init (CPUState *env); |
void ppc970_irq_init (CPUState *env); |
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void ppcPOWER7_irq_init (CPUState *env); |
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/* PPC machines for OpenBIOS */ |
/* PPC machines for OpenBIOS */ |
enum { |
enum { |
Line 47 enum {
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Line 82 enum {
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#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
#define FW_CFG_PPC_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
#define FW_CFG_PPC_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03) |
#define FW_CFG_PPC_TBFREQ (FW_CFG_ARCH_LOCAL + 0x03) |
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#define FW_CFG_PPC_IS_KVM (FW_CFG_ARCH_LOCAL + 0x05) |
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#define FW_CFG_PPC_KVM_HC (FW_CFG_ARCH_LOCAL + 0x06) |
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#define FW_CFG_PPC_KVM_PID (FW_CFG_ARCH_LOCAL + 0x07) |
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#define PPC_SERIAL_MM_BAUDBASE 399193 |
#define PPC_SERIAL_MM_BAUDBASE 399193 |
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/* ppc_booke.c */ |
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void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags); |