Diff for /qemu/hw/ppc.h between versions 1.1.1.6 and 1.1.1.7

version 1.1.1.6, 2018/04/24 18:59:22 version 1.1.1.7, 2018/04/24 19:26:51
Line 1 Line 1
   void ppc_set_irq (CPUState *env, int n_IRQ, int level);
   
 /* PowerPC hardware exceptions management helpers */  /* PowerPC hardware exceptions management helpers */
 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);  typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
 typedef struct clk_setup_t clk_setup_t;  typedef struct clk_setup_t clk_setup_t;
Line 11  static inline void clk_setup (clk_setup_ Line 13  static inline void clk_setup (clk_setup_
         (*clk->cb)(clk->opaque, freq);          (*clk->cb)(clk->opaque, freq);
 }  }
   
   struct ppc_tb_t {
       /* Time base management */
       int64_t  tb_offset;    /* Compensation                    */
       int64_t  atb_offset;   /* Compensation                    */
       uint32_t tb_freq;      /* TB frequency                    */
       /* Decrementer management */
       uint64_t decr_next;    /* Tick for next decr interrupt    */
       uint32_t decr_freq;    /* decrementer frequency           */
       struct QEMUTimer *decr_timer;
       /* Hypervisor decrementer management */
       uint64_t hdecr_next;    /* Tick for next hdecr interrupt  */
       struct QEMUTimer *hdecr_timer;
       uint64_t purr_load;
       uint64_t purr_start;
       void *opaque;
       uint32_t flags;
   };
   
   /* PPC Timers flags */
   #define PPC_TIMER_BOOKE              (1 << 0) /* Enable Booke support */
   #define PPC_TIMER_E500               (1 << 1) /* Enable e500 support */
   #define PPC_DECR_UNDERFLOW_TRIGGERED (1 << 2) /* Decr interrupt triggered when
                                                  * the most significant bit
                                                  * changes from 0 to 1.
                                                  */
   #define PPC_DECR_ZERO_TRIGGERED      (1 << 3) /* Decr interrupt triggered when
                                                  * the decrementer reaches zero.
                                                  */
   
   uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);  clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
 /* Embedded PowerPC DCR management */  /* Embedded PowerPC DCR management */
 typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);  typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
Line 19  int ppc_dcr_init (CPUState *env, int (*d Line 51  int ppc_dcr_init (CPUState *env, int (*d
                   int (*dcr_write_error)(int dcrn));                    int (*dcr_write_error)(int dcrn));
 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,  int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
                       dcr_read_cb drc_read, dcr_write_cb dcr_write);                        dcr_read_cb drc_read, dcr_write_cb dcr_write);
 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq,  clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq,
                                   unsigned int decr_excp);                                    unsigned int decr_excp);
   
 /* Embedded PowerPC reset */  /* Embedded PowerPC reset */
Line 55  enum { Line 87  enum {
 #define FW_CFG_PPC_KVM_PID      (FW_CFG_ARCH_LOCAL + 0x07)  #define FW_CFG_PPC_KVM_PID      (FW_CFG_ARCH_LOCAL + 0x07)
   
 #define PPC_SERIAL_MM_BAUDBASE 399193  #define PPC_SERIAL_MM_BAUDBASE 399193
   
   /* ppc_booke.c */
   void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags);

Removed from v.1.1.1.6  
changed lines
  Added in v.1.1.1.7


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