Diff for /qemu/hw/ppc.h between versions 1.1.1.7 and 1.1.1.8

version 1.1.1.7, 2018/04/24 19:26:51 version 1.1.1.8, 2018/04/24 19:46:37
Line 1 Line 1
 void ppc_set_irq (CPUState *env, int n_IRQ, int level);  void ppc_set_irq (CPUPPCState *env, int n_IRQ, int level);
   
 /* PowerPC hardware exceptions management helpers */  /* PowerPC hardware exceptions management helpers */
 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);  typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
Line 43  struct ppc_tb_t { Line 43  struct ppc_tb_t {
                                                */                                                 */
   
 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);  uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);  clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
 /* Embedded PowerPC DCR management */  /* Embedded PowerPC DCR management */
 typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);  typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
 typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);  typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),  int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
                   int (*dcr_write_error)(int dcrn));                    int (*dcr_write_error)(int dcrn));
 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,  int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
                       dcr_read_cb drc_read, dcr_write_cb dcr_write);                        dcr_read_cb drc_read, dcr_write_cb dcr_write);
 clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq,  clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
                                   unsigned int decr_excp);                                    unsigned int decr_excp);
   
 /* Embedded PowerPC reset */  /* Embedded PowerPC reset */
 void ppc40x_core_reset (CPUState *env);  void ppc40x_core_reset (CPUPPCState *env);
 void ppc40x_chip_reset (CPUState *env);  void ppc40x_chip_reset (CPUPPCState *env);
 void ppc40x_system_reset (CPUState *env);  void ppc40x_system_reset (CPUPPCState *env);
 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);  void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
   
 extern CPUWriteMemoryFunc * const PPC_io_write[];  extern CPUWriteMemoryFunc * const PPC_io_write[];
 extern CPUReadMemoryFunc * const PPC_io_read[];  extern CPUReadMemoryFunc * const PPC_io_read[];
 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);  void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
   
 void ppc40x_irq_init (CPUState *env);  void ppc40x_irq_init (CPUPPCState *env);
 void ppce500_irq_init (CPUState *env);  void ppce500_irq_init (CPUPPCState *env);
 void ppc6xx_irq_init (CPUState *env);  void ppc6xx_irq_init (CPUPPCState *env);
 void ppc970_irq_init (CPUState *env);  void ppc970_irq_init (CPUPPCState *env);
 void ppcPOWER7_irq_init (CPUState *env);  void ppcPOWER7_irq_init (CPUPPCState *env);
   
 /* PPC machines for OpenBIOS */  /* PPC machines for OpenBIOS */
 enum {  enum {
Line 89  enum { Line 89  enum {
 #define PPC_SERIAL_MM_BAUDBASE 399193  #define PPC_SERIAL_MM_BAUDBASE 399193
   
 /* ppc_booke.c */  /* ppc_booke.c */
 void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags);  void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags);

Removed from v.1.1.1.7  
changed lines
  Added in v.1.1.1.8


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