Annotation of qemu/hw/ppc.h, revision 1.1.1.1
1.1 root 1: /* PowerPC hardware exceptions management helpers */
2: typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
3: typedef struct clk_setup_t clk_setup_t;
4: struct clk_setup_t {
5: clk_setup_cb cb;
6: void *opaque;
7: };
8: static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
9: {
10: if (clk->cb != NULL)
11: (*clk->cb)(clk->opaque, freq);
12: }
13:
14: clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
15: /* Embedded PowerPC DCR management */
16: typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
17: typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
18: int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
19: int (*dcr_write_error)(int dcrn));
20: int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
21: dcr_read_cb drc_read, dcr_write_cb dcr_write);
22: clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
23: /* Embedded PowerPC reset */
24: void ppc40x_core_reset (CPUState *env);
25: void ppc40x_chip_reset (CPUState *env);
26: void ppc40x_system_reset (CPUState *env);
27: void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
28:
29: extern CPUWriteMemoryFunc *PPC_io_write[];
30: extern CPUReadMemoryFunc *PPC_io_read[];
31: void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
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