Annotation of qemu/hw/ppc.h, revision 1.1.1.6

1.1       root        1: /* PowerPC hardware exceptions management helpers */
                      2: typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
                      3: typedef struct clk_setup_t clk_setup_t;
                      4: struct clk_setup_t {
                      5:     clk_setup_cb cb;
                      6:     void *opaque;
                      7: };
                      8: static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
                      9: {
                     10:     if (clk->cb != NULL)
                     11:         (*clk->cb)(clk->opaque, freq);
                     12: }
                     13: 
                     14: clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
                     15: /* Embedded PowerPC DCR management */
1.1.1.4   root       16: typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
                     17: typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
1.1       root       18: int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
                     19:                   int (*dcr_write_error)(int dcrn));
                     20: int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
                     21:                       dcr_read_cb drc_read, dcr_write_cb dcr_write);
1.1.1.5   root       22: clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq,
                     23:                                   unsigned int decr_excp);
                     24: 
1.1       root       25: /* Embedded PowerPC reset */
                     26: void ppc40x_core_reset (CPUState *env);
                     27: void ppc40x_chip_reset (CPUState *env);
                     28: void ppc40x_system_reset (CPUState *env);
                     29: void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
                     30: 
1.1.1.3   root       31: extern CPUWriteMemoryFunc * const PPC_io_write[];
                     32: extern CPUReadMemoryFunc * const PPC_io_read[];
1.1       root       33: void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1.1.1.2   root       34: 
                     35: void ppc40x_irq_init (CPUState *env);
                     36: void ppce500_irq_init (CPUState *env);
                     37: void ppc6xx_irq_init (CPUState *env);
                     38: void ppc970_irq_init (CPUState *env);
1.1.1.6 ! root       39: void ppcPOWER7_irq_init (CPUState *env);
1.1.1.2   root       40: 
                     41: /* PPC machines for OpenBIOS */
                     42: enum {
                     43:     ARCH_PREP = 0,
                     44:     ARCH_MAC99,
                     45:     ARCH_HEATHROW,
1.1.1.4   root       46:     ARCH_MAC99_U3,
1.1.1.2   root       47: };
                     48: 
1.1.1.3   root       49: #define FW_CFG_PPC_WIDTH       (FW_CFG_ARCH_LOCAL + 0x00)
                     50: #define FW_CFG_PPC_HEIGHT      (FW_CFG_ARCH_LOCAL + 0x01)
                     51: #define FW_CFG_PPC_DEPTH       (FW_CFG_ARCH_LOCAL + 0x02)
1.1.1.4   root       52: #define FW_CFG_PPC_TBFREQ      (FW_CFG_ARCH_LOCAL + 0x03)
1.1.1.5   root       53: #define FW_CFG_PPC_IS_KVM       (FW_CFG_ARCH_LOCAL + 0x05)
                     54: #define FW_CFG_PPC_KVM_HC       (FW_CFG_ARCH_LOCAL + 0x06)
                     55: #define FW_CFG_PPC_KVM_PID      (FW_CFG_ARCH_LOCAL + 0x07)
1.1.1.3   root       56: 
                     57: #define PPC_SERIAL_MM_BAUDBASE 399193

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