File:  [Qemu by Fabrice Bellard] / qemu / hw / ppc.h
Revision 1.1.1.3 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 17:37:07 2018 UTC (2 years, 2 months ago) by root
Branches: qemu, MAIN
CVS tags: qemu0125, qemu0124, qemu0123, qemu0122, qemu0121, qemu0120, HEAD
qemu 0.12.0

    1: /* PowerPC hardware exceptions management helpers */
    2: typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
    3: typedef struct clk_setup_t clk_setup_t;
    4: struct clk_setup_t {
    5:     clk_setup_cb cb;
    6:     void *opaque;
    7: };
    8: static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
    9: {
   10:     if (clk->cb != NULL)
   11:         (*clk->cb)(clk->opaque, freq);
   12: }
   13: 
   14: clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
   15: /* Embedded PowerPC DCR management */
   16: typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
   17: typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
   18: int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
   19:                   int (*dcr_write_error)(int dcrn));
   20: int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
   21:                       dcr_read_cb drc_read, dcr_write_cb dcr_write);
   22: clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
   23: /* Embedded PowerPC reset */
   24: void ppc40x_core_reset (CPUState *env);
   25: void ppc40x_chip_reset (CPUState *env);
   26: void ppc40x_system_reset (CPUState *env);
   27: void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
   28: 
   29: extern CPUWriteMemoryFunc * const PPC_io_write[];
   30: extern CPUReadMemoryFunc * const PPC_io_read[];
   31: void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
   32: 
   33: void ppc40x_irq_init (CPUState *env);
   34: void ppce500_irq_init (CPUState *env);
   35: void ppc6xx_irq_init (CPUState *env);
   36: void ppc970_irq_init (CPUState *env);
   37: 
   38: /* PPC machines for OpenBIOS */
   39: enum {
   40:     ARCH_PREP = 0,
   41:     ARCH_MAC99,
   42:     ARCH_HEATHROW,
   43: };
   44: 
   45: #define FW_CFG_PPC_WIDTH	(FW_CFG_ARCH_LOCAL + 0x00)
   46: #define FW_CFG_PPC_HEIGHT	(FW_CFG_ARCH_LOCAL + 0x01)
   47: #define FW_CFG_PPC_DEPTH	(FW_CFG_ARCH_LOCAL + 0x02)
   48: 
   49: #define PPC_SERIAL_MM_BAUDBASE 399193

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