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qemu 1.1.1

    1: void ppc_set_irq (CPUPPCState *env, int n_IRQ, int level);
    2: 
    3: /* PowerPC hardware exceptions management helpers */
    4: typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
    5: typedef struct clk_setup_t clk_setup_t;
    6: struct clk_setup_t {
    7:     clk_setup_cb cb;
    8:     void *opaque;
    9: };
   10: static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
   11: {
   12:     if (clk->cb != NULL)
   13:         (*clk->cb)(clk->opaque, freq);
   14: }
   15: 
   16: struct ppc_tb_t {
   17:     /* Time base management */
   18:     int64_t  tb_offset;    /* Compensation                    */
   19:     int64_t  atb_offset;   /* Compensation                    */
   20:     uint32_t tb_freq;      /* TB frequency                    */
   21:     /* Decrementer management */
   22:     uint64_t decr_next;    /* Tick for next decr interrupt    */
   23:     uint32_t decr_freq;    /* decrementer frequency           */
   24:     struct QEMUTimer *decr_timer;
   25:     /* Hypervisor decrementer management */
   26:     uint64_t hdecr_next;    /* Tick for next hdecr interrupt  */
   27:     struct QEMUTimer *hdecr_timer;
   28:     uint64_t purr_load;
   29:     uint64_t purr_start;
   30:     void *opaque;
   31:     uint32_t flags;
   32: };
   33: 
   34: /* PPC Timers flags */
   35: #define PPC_TIMER_BOOKE              (1 << 0) /* Enable Booke support */
   36: #define PPC_TIMER_E500               (1 << 1) /* Enable e500 support */
   37: #define PPC_DECR_UNDERFLOW_TRIGGERED (1 << 2) /* Decr interrupt triggered when
   38:                                                * the most significant bit
   39:                                                * changes from 0 to 1.
   40:                                                */
   41: #define PPC_DECR_ZERO_TRIGGERED      (1 << 3) /* Decr interrupt triggered when
   42:                                                * the decrementer reaches zero.
   43:                                                */
   44: 
   45: uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
   46: clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
   47: /* Embedded PowerPC DCR management */
   48: typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
   49: typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
   50: int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
   51:                   int (*dcr_write_error)(int dcrn));
   52: int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
   53:                       dcr_read_cb drc_read, dcr_write_cb dcr_write);
   54: clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
   55:                                   unsigned int decr_excp);
   56: 
   57: /* Embedded PowerPC reset */
   58: void ppc40x_core_reset (CPUPPCState *env);
   59: void ppc40x_chip_reset (CPUPPCState *env);
   60: void ppc40x_system_reset (CPUPPCState *env);
   61: void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
   62: 
   63: extern CPUWriteMemoryFunc * const PPC_io_write[];
   64: extern CPUReadMemoryFunc * const PPC_io_read[];
   65: void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
   66: 
   67: void ppc40x_irq_init (CPUPPCState *env);
   68: void ppce500_irq_init (CPUPPCState *env);
   69: void ppc6xx_irq_init (CPUPPCState *env);
   70: void ppc970_irq_init (CPUPPCState *env);
   71: void ppcPOWER7_irq_init (CPUPPCState *env);
   72: 
   73: /* PPC machines for OpenBIOS */
   74: enum {
   75:     ARCH_PREP = 0,
   76:     ARCH_MAC99,
   77:     ARCH_HEATHROW,
   78:     ARCH_MAC99_U3,
   79: };
   80: 
   81: #define FW_CFG_PPC_WIDTH	(FW_CFG_ARCH_LOCAL + 0x00)
   82: #define FW_CFG_PPC_HEIGHT	(FW_CFG_ARCH_LOCAL + 0x01)
   83: #define FW_CFG_PPC_DEPTH	(FW_CFG_ARCH_LOCAL + 0x02)
   84: #define FW_CFG_PPC_TBFREQ	(FW_CFG_ARCH_LOCAL + 0x03)
   85: #define FW_CFG_PPC_IS_KVM       (FW_CFG_ARCH_LOCAL + 0x05)
   86: #define FW_CFG_PPC_KVM_HC       (FW_CFG_ARCH_LOCAL + 0x06)
   87: #define FW_CFG_PPC_KVM_PID      (FW_CFG_ARCH_LOCAL + 0x07)
   88: 
   89: #define PPC_SERIAL_MM_BAUDBASE 399193
   90: 
   91: /* ppc_booke.c */
   92: void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags);