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1.1 root 1: /*
2: * QEMU PowerPC 405 shared definitions
3: *
4: * Copyright (c) 2007 Jocelyn Mayer
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24:
25: #if !defined(PPC_405_H)
26: #define PPC_405_H
27:
28: #include "ppc4xx.h"
29:
30: /* Bootinfo as set-up by u-boot */
31: typedef struct ppc4xx_bd_info_t ppc4xx_bd_info_t;
32: struct ppc4xx_bd_info_t {
33: uint32_t bi_memstart;
34: uint32_t bi_memsize;
35: uint32_t bi_flashstart;
36: uint32_t bi_flashsize;
37: uint32_t bi_flashoffset; /* 0x10 */
38: uint32_t bi_sramstart;
39: uint32_t bi_sramsize;
40: uint32_t bi_bootflags;
41: uint32_t bi_ipaddr; /* 0x20 */
42: uint8_t bi_enetaddr[6];
43: uint16_t bi_ethspeed;
44: uint32_t bi_intfreq;
45: uint32_t bi_busfreq; /* 0x30 */
46: uint32_t bi_baudrate;
47: uint8_t bi_s_version[4];
48: uint8_t bi_r_version[32];
49: uint32_t bi_procfreq;
50: uint32_t bi_plb_busfreq;
51: uint32_t bi_pci_busfreq;
52: uint8_t bi_pci_enetaddr[6];
53: uint32_t bi_pci_enetaddr2[6];
54: uint32_t bi_opbfreq;
55: uint32_t bi_iic_fast[2];
56: };
57:
58: /* PowerPC 405 core */
59: ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
60: uint32_t flags);
61:
62: /* PowerPC 4xx peripheral local bus arbitrer */
63: void ppc4xx_plb_init (CPUState *env);
64: /* PLB to OPB bridge */
65: void ppc4xx_pob_init (CPUState *env);
66: /* OPB arbitrer */
67: void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
68: target_phys_addr_t offset);
69: /* SDRAM controller */
70: void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
71: target_phys_addr_t *ram_bases,
72: target_phys_addr_t *ram_sizes,
73: int do_init);
74: /* Peripheral controller */
75: void ppc405_ebc_init (CPUState *env);
76: /* DMA controller */
77: void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]);
78: /* GPIO */
79: void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
80: target_phys_addr_t offset);
81: /* Serial ports */
82: void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
83: target_phys_addr_t offset, qemu_irq irq,
84: CharDriverState *chr);
85: /* On Chip Memory */
86: void ppc405_ocm_init (CPUState *env, unsigned long offset);
87: /* I2C controller */
88: void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
89: target_phys_addr_t offset, qemu_irq irq);
90: /* General purpose timers */
91: void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
92: target_phys_addr_t offset, qemu_irq irq[5]);
93: /* Memory access layer */
94: void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]);
95: /* PowerPC 405 microcontrollers */
96: CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
97: target_phys_addr_t ram_sizes[4],
98: uint32_t sysclk, qemu_irq **picp,
99: ram_addr_t *offsetp, int do_init);
100: CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
101: target_phys_addr_t ram_sizes[2],
102: uint32_t sysclk, qemu_irq **picp,
103: ram_addr_t *offsetp, int do_init);
104: /* IBM STBxxx microcontrollers */
105: CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
106: target_phys_addr_t ram_sizes[2],
107: uint32_t sysclk, qemu_irq **picp,
108: ram_addr_t *offsetp);
109:
110: #endif /* !defined(PPC_405_H) */
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