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1.1 root 1: /*
2: * Qemu PowerPC 440 chip emulation
3: *
4: * Copyright 2007 IBM Corporation.
5: * Authors:
6: * Jerone Young <[email protected]>
7: * Christian Ehrhardt <[email protected]>
8: * Hollis Blanchard <[email protected]>
9: *
10: * This work is licensed under the GNU GPL license version 2 or later.
11: *
12: */
13:
14: #include "hw.h"
1.1.1.3 root 15: #include "pc.h"
1.1 root 16: #include "isa.h"
17: #include "ppc.h"
18: #include "ppc4xx.h"
19: #include "ppc440.h"
20: #include "ppc405.h"
21: #include "sysemu.h"
22: #include "kvm.h"
23:
24: #define PPC440EP_PCI_CONFIG 0xeec00000
25: #define PPC440EP_PCI_INTACK 0xeed00000
26: #define PPC440EP_PCI_SPECIAL 0xeed00000
27: #define PPC440EP_PCI_REGS 0xef400000
28: #define PPC440EP_PCI_IO 0xe8000000
29: #define PPC440EP_PCI_IOLEN 0x00010000
30:
31: #define PPC440EP_SDRAM_NR_BANKS 4
32:
33: static const unsigned int ppc440ep_sdram_bank_sizes[] = {
34: 256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
35: };
36:
1.1.1.7 ! root 37: CPUState *ppc440ep_init(MemoryRegion *address_space_mem, ram_addr_t *ram_size,
! 38: PCIBus **pcip, const unsigned int pci_irq_nrs[4],
! 39: int do_init, const char *cpu_model)
1.1 root 40: {
1.1.1.7 ! root 41: MemoryRegion *ram_memories
! 42: = g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
1.1 root 43: target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
44: target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
45: CPUState *env;
46: qemu_irq *pic;
47: qemu_irq *irqs;
48: qemu_irq *pci_irqs;
49:
1.1.1.6 root 50: if (cpu_model == NULL) {
51: cpu_model = "440-Xilinx"; // XXX: should be 440EP
52: }
1.1.1.2 root 53: env = cpu_init(cpu_model);
1.1 root 54: if (!env) {
55: fprintf(stderr, "Unable to initialize CPU!\n");
56: exit(1);
57: }
58:
59: ppc_dcr_init(env, NULL, NULL);
60:
61: /* interrupt controller */
1.1.1.7 ! root 62: irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
1.1 root 63: irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
64: irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
65: pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
66:
67: /* SDRAM controller */
68: memset(ram_bases, 0, sizeof(ram_bases));
69: memset(ram_sizes, 0, sizeof(ram_sizes));
70: *ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS,
1.1.1.7 ! root 71: ram_memories,
1.1 root 72: ram_bases, ram_sizes,
73: ppc440ep_sdram_bank_sizes);
74: /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
1.1.1.7 ! root 75: ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
! 76: ram_bases, ram_sizes, do_init);
1.1 root 77:
78: /* PCI */
1.1.1.7 ! root 79: pci_irqs = g_malloc(sizeof(qemu_irq) * 4);
1.1 root 80: pci_irqs[0] = pic[pci_irq_nrs[0]];
81: pci_irqs[1] = pic[pci_irq_nrs[1]];
82: pci_irqs[2] = pic[pci_irq_nrs[2]];
83: pci_irqs[3] = pic[pci_irq_nrs[3]];
84: *pcip = ppc4xx_pci_init(env, pci_irqs,
85: PPC440EP_PCI_CONFIG,
86: PPC440EP_PCI_INTACK,
87: PPC440EP_PCI_SPECIAL,
88: PPC440EP_PCI_REGS);
89: if (!*pcip)
90: printf("couldn't create PCI controller!\n");
91:
1.1.1.5 root 92: isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
1.1 root 93:
1.1.1.3 root 94: if (serial_hds[0] != NULL) {
1.1.1.7 ! root 95: serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
! 96: PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
! 97: DEVICE_BIG_ENDIAN);
1.1.1.3 root 98: }
99: if (serial_hds[1] != NULL) {
1.1.1.7 ! root 100: serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
! 101: PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
! 102: DEVICE_BIG_ENDIAN);
1.1.1.3 root 103: }
1.1 root 104:
105: return env;
106: }
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