--- qemu/hw/ppc_mac.h	2018/04/24 16:48:20	1.1.1.1
+++ qemu/hw/ppc_mac.h	2018/04/24 18:37:13	1.1.1.6
@@ -28,15 +28,17 @@
 /* SMP is not enabled, for now */
 #define MAX_CPUS 1
 
+#define BIOS_SIZE     (1024 * 1024)
 #define BIOS_FILENAME "ppc_rom.bin"
-#define VGABIOS_FILENAME "video.x"
 #define NVRAM_SIZE        0x2000
+#define PROM_FILENAME    "openbios-ppc"
+#define PROM_ADDR         0xfff00000
 
 #define KERNEL_LOAD_ADDR 0x01000000
-#define INITRD_LOAD_ADDR 0x01800000
+#define CMDLINE_ADDR     0x027ff000
+#define INITRD_LOAD_ADDR 0x02800000
 
-/* DBDMA */
-void dbdma_init (int *dbdma_mem_index);
+#define ESCC_CLOCK 3686400
 
 /* Cuda */
 void cuda_init (int *cuda_mem_index, qemu_irq irq);
@@ -44,10 +46,7 @@ void cuda_init (int *cuda_mem_index, qem
 /* MacIO */
 void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
                  int dbdma_mem_index, int cuda_mem_index, void *nvram,
-                 int nb_ide, int *ide_mem_index);
-
-/* NewWorld PowerMac IDE */
-int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
+                 int nb_ide, int *ide_mem_index, int escc_mem_index);
 
 /* Heathrow PIC */
 qemu_irq *heathrow_pic_init(int *pmem_index,
@@ -58,11 +57,13 @@ PCIBus *pci_grackle_init(uint32_t base,
 
 /* UniNorth PCI */
 PCIBus *pci_pmac_init(qemu_irq *pic);
+PCIBus *pci_pmac_u3_init(qemu_irq *pic);
 
 /* Mac NVRAM */
 typedef struct MacIONVRAMState MacIONVRAMState;
 
-MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size);
+MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size,
+                                   unsigned int it_shift);
 void macio_nvram_map (void *opaque, target_phys_addr_t mem_base);
 void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
 uint32_t macio_nvram_read (void *opaque, uint32_t addr);
@@ -109,17 +110,4 @@ void adb_mouse_init(ADBBusState *bus);
 
 extern ADBBusState adb_bus;
 
-/* openpic.c */
-/* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
-enum {
-    OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
-    OPENPIC_OUTPUT_CINT,    /* critical IRQ              */
-    OPENPIC_OUTPUT_MCK,     /* Machine check event       */
-    OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */
-    OPENPIC_OUTPUT_RESET,   /* Core reset event          */
-    OPENPIC_OUTPUT_NB,
-};
-qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
-                        qemu_irq **irqs, qemu_irq irq_out);
-
 #endif /* !defined(__PPC_MAC_H__) */