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1.1 ! root 1: /* ! 2: * Intel XScale PXA255/270 processor support. ! 3: * ! 4: * Copyright (c) 2006 Openedhand Ltd. ! 5: * Written by Andrzej Zaborowski <[email protected]> ! 6: * ! 7: * This code is licenced under the GNU GPL v2. ! 8: */ ! 9: #ifndef PXA_H ! 10: # define PXA_H "pxa.h" ! 11: ! 12: /* Interrupt numbers */ ! 13: # define PXA2XX_PIC_SSP3 0 ! 14: # define PXA2XX_PIC_USBH2 2 ! 15: # define PXA2XX_PIC_USBH1 3 ! 16: # define PXA2XX_PIC_KEYPAD 4 ! 17: # define PXA2XX_PIC_PWRI2C 6 ! 18: # define PXA25X_PIC_HWUART 7 ! 19: # define PXA27X_PIC_OST_4_11 7 ! 20: # define PXA2XX_PIC_GPIO_0 8 ! 21: # define PXA2XX_PIC_GPIO_1 9 ! 22: # define PXA2XX_PIC_GPIO_X 10 ! 23: # define PXA2XX_PIC_I2S 13 ! 24: # define PXA26X_PIC_ASSP 15 ! 25: # define PXA25X_PIC_NSSP 16 ! 26: # define PXA27X_PIC_SSP2 16 ! 27: # define PXA2XX_PIC_LCD 17 ! 28: # define PXA2XX_PIC_I2C 18 ! 29: # define PXA2XX_PIC_ICP 19 ! 30: # define PXA2XX_PIC_STUART 20 ! 31: # define PXA2XX_PIC_BTUART 21 ! 32: # define PXA2XX_PIC_FFUART 22 ! 33: # define PXA2XX_PIC_MMC 23 ! 34: # define PXA2XX_PIC_SSP 24 ! 35: # define PXA2XX_PIC_DMA 25 ! 36: # define PXA2XX_PIC_OST_0 26 ! 37: # define PXA2XX_PIC_RTC1HZ 30 ! 38: # define PXA2XX_PIC_RTCALARM 31 ! 39: ! 40: /* DMA requests */ ! 41: # define PXA2XX_RX_RQ_I2S 2 ! 42: # define PXA2XX_TX_RQ_I2S 3 ! 43: # define PXA2XX_RX_RQ_BTUART 4 ! 44: # define PXA2XX_TX_RQ_BTUART 5 ! 45: # define PXA2XX_RX_RQ_FFUART 6 ! 46: # define PXA2XX_TX_RQ_FFUART 7 ! 47: # define PXA2XX_RX_RQ_SSP1 13 ! 48: # define PXA2XX_TX_RQ_SSP1 14 ! 49: # define PXA2XX_RX_RQ_SSP2 15 ! 50: # define PXA2XX_TX_RQ_SSP2 16 ! 51: # define PXA2XX_RX_RQ_ICP 17 ! 52: # define PXA2XX_TX_RQ_ICP 18 ! 53: # define PXA2XX_RX_RQ_STUART 19 ! 54: # define PXA2XX_TX_RQ_STUART 20 ! 55: # define PXA2XX_RX_RQ_MMCI 21 ! 56: # define PXA2XX_TX_RQ_MMCI 22 ! 57: # define PXA2XX_USB_RQ(x) ((x) + 24) ! 58: # define PXA2XX_RX_RQ_SSP3 66 ! 59: # define PXA2XX_TX_RQ_SSP3 67 ! 60: ! 61: # define PXA2XX_SDRAM_BASE 0xa0000000 ! 62: # define PXA2XX_INTERNAL_BASE 0x5c000000 ! 63: # define PXA2XX_INTERNAL_SIZE 0x40000 ! 64: ! 65: /* pxa2xx_pic.c */ ! 66: qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env); ! 67: ! 68: /* pxa2xx_timer.c */ ! 69: void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs); ! 70: void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4); ! 71: ! 72: /* pxa2xx_gpio.c */ ! 73: struct pxa2xx_gpio_info_s; ! 74: struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base, ! 75: CPUState *env, qemu_irq *pic, int lines); ! 76: qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s); ! 77: void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s, ! 78: int line, qemu_irq handler); ! 79: void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler); ! 80: ! 81: /* pxa2xx_dma.c */ ! 82: struct pxa2xx_dma_state_s; ! 83: struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base, ! 84: qemu_irq irq); ! 85: struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base, ! 86: qemu_irq irq); ! 87: void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on); ! 88: ! 89: /* pxa2xx_lcd.c */ ! 90: struct pxa2xx_lcdc_s; ! 91: struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, ! 92: qemu_irq irq, DisplayState *ds); ! 93: void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler); ! 94: void pxa2xx_lcdc_oritentation(void *opaque, int angle); ! 95: ! 96: /* pxa2xx_mmci.c */ ! 97: struct pxa2xx_mmci_s; ! 98: struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base, ! 99: BlockDriverState *bd, qemu_irq irq, void *dma); ! 100: void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly, ! 101: qemu_irq coverswitch); ! 102: ! 103: /* pxa2xx_pcmcia.c */ ! 104: struct pxa2xx_pcmcia_s; ! 105: struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base); ! 106: int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card); ! 107: int pxa2xx_pcmcia_dettach(void *opaque); ! 108: void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); ! 109: ! 110: /* pxa2xx_keypad.c */ ! 111: struct keymap { ! 112: int column; ! 113: int row; ! 114: }; ! 115: struct pxa2xx_keypad_s; ! 116: struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base, ! 117: qemu_irq irq); ! 118: void pxa27x_register_keypad(struct pxa2xx_keypad_s *kp, struct keymap *map, ! 119: int size); ! 120: ! 121: /* pxa2xx.c */ ! 122: struct pxa2xx_ssp_s; ! 123: void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port, ! 124: uint32_t (*readfn)(void *opaque), ! 125: void (*writefn)(void *opaque, uint32_t value), void *opaque); ! 126: ! 127: struct pxa2xx_i2c_s; ! 128: struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base, ! 129: qemu_irq irq, uint32_t page_size); ! 130: i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s); ! 131: ! 132: struct pxa2xx_i2s_s; ! 133: struct pxa2xx_fir_s; ! 134: ! 135: struct pxa2xx_state_s { ! 136: CPUState *env; ! 137: qemu_irq *pic; ! 138: qemu_irq reset; ! 139: struct pxa2xx_dma_state_s *dma; ! 140: struct pxa2xx_gpio_info_s *gpio; ! 141: struct pxa2xx_lcdc_s *lcd; ! 142: struct pxa2xx_ssp_s **ssp; ! 143: struct pxa2xx_i2c_s *i2c[2]; ! 144: struct pxa2xx_mmci_s *mmc; ! 145: struct pxa2xx_pcmcia_s *pcmcia[2]; ! 146: struct pxa2xx_i2s_s *i2s; ! 147: struct pxa2xx_fir_s *fir; ! 148: struct pxa2xx_keypad_s *kp; ! 149: ! 150: /* Power management */ ! 151: target_phys_addr_t pm_base; ! 152: uint32_t pm_regs[0x40]; ! 153: ! 154: /* Clock management */ ! 155: target_phys_addr_t cm_base; ! 156: uint32_t cm_regs[4]; ! 157: uint32_t clkcfg; ! 158: ! 159: /* Memory management */ ! 160: target_phys_addr_t mm_base; ! 161: uint32_t mm_regs[0x1a]; ! 162: ! 163: /* Performance monitoring */ ! 164: uint32_t pmnc; ! 165: ! 166: /* Real-Time clock */ ! 167: target_phys_addr_t rtc_base; ! 168: uint32_t rttr; ! 169: uint32_t rtsr; ! 170: uint32_t rtar; ! 171: uint32_t rdar1; ! 172: uint32_t rdar2; ! 173: uint32_t ryar1; ! 174: uint32_t ryar2; ! 175: uint32_t swar1; ! 176: uint32_t swar2; ! 177: uint32_t piar; ! 178: uint32_t last_rcnr; ! 179: uint32_t last_rdcr; ! 180: uint32_t last_rycr; ! 181: uint32_t last_swcr; ! 182: uint32_t last_rtcpicr; ! 183: int64_t last_hz; ! 184: int64_t last_sw; ! 185: int64_t last_pi; ! 186: QEMUTimer *rtc_hz; ! 187: QEMUTimer *rtc_rdal1; ! 188: QEMUTimer *rtc_rdal2; ! 189: QEMUTimer *rtc_swal1; ! 190: QEMUTimer *rtc_swal2; ! 191: QEMUTimer *rtc_pi; ! 192: }; ! 193: ! 194: struct pxa2xx_i2s_s { ! 195: target_phys_addr_t base; ! 196: qemu_irq irq; ! 197: struct pxa2xx_dma_state_s *dma; ! 198: void (*data_req)(void *, int, int); ! 199: ! 200: uint32_t control[2]; ! 201: uint32_t status; ! 202: uint32_t mask; ! 203: uint32_t clk; ! 204: ! 205: int enable; ! 206: int rx_len; ! 207: int tx_len; ! 208: void (*codec_out)(void *, uint32_t); ! 209: uint32_t (*codec_in)(void *); ! 210: void *opaque; ! 211: ! 212: int fifo_len; ! 213: uint32_t fifo[16]; ! 214: }; ! 215: ! 216: # define PA_FMT "0x%08lx" ! 217: # define REG_FMT "0x" TARGET_FMT_plx ! 218: ! 219: struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds, ! 220: const char *revision); ! 221: struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds); ! 222: ! 223: /* usb-ohci.c */ ! 224: void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn, ! 225: qemu_irq irq); ! 226: ! 227: #endif /* PXA_H */
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