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1.1 root 1: /*
2: * Renesas SH7751R R2D-PLUS emulation
3: *
4: * Copyright (c) 2007 Magnus Damm
1.1.1.2 root 5: * Copyright (c) 2008 Paul Mundt
1.1 root 6: *
7: * Permission is hereby granted, free of charge, to any person obtaining a copy
8: * of this software and associated documentation files (the "Software"), to deal
9: * in the Software without restriction, including without limitation the rights
10: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11: * copies of the Software, and to permit persons to whom the Software is
12: * furnished to do so, subject to the following conditions:
13: *
14: * The above copyright notice and this permission notice shall be included in
15: * all copies or substantial portions of the Software.
16: *
17: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23: * THE SOFTWARE.
24: */
25:
26: #include "hw.h"
27: #include "sh.h"
1.1.1.2 root 28: #include "devices.h"
1.1 root 29: #include "sysemu.h"
30: #include "boards.h"
1.1.1.2 root 31: #include "pci.h"
1.1.1.5 root 32: #include "sh_pci.h"
1.1.1.2 root 33: #include "net.h"
34: #include "sh7750_regs.h"
1.1.1.5 root 35: #include "ide.h"
36: #include "loader.h"
1.1.1.6 ! root 37: #include "usb.h"
! 38: #include "flash.h"
! 39:
! 40: #define FLASH_BASE 0x00000000
! 41: #define FLASH_SIZE 0x02000000
1.1 root 42:
43: #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
44: #define SDRAM_SIZE 0x04000000
45:
1.1.1.2 root 46: #define SM501_VRAM_SIZE 0x800000
47:
1.1.1.6 ! root 48: #define BOOT_PARAMS_OFFSET 0x0010000
1.1.1.3 root 49: /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
1.1.1.6 ! root 50: #define LINUX_LOAD_OFFSET 0x0800000
! 51: #define INITRD_LOAD_OFFSET 0x1800000
1.1.1.3 root 52:
1.1.1.2 root 53: #define PA_IRLMSK 0x00
54: #define PA_POWOFF 0x30
55: #define PA_VERREG 0x32
56: #define PA_OUTPORT 0x36
57:
58: typedef struct {
59: uint16_t bcr;
60: uint16_t irlmsk;
61: uint16_t irlmon;
62: uint16_t cfctl;
63: uint16_t cfpow;
64: uint16_t dispctl;
65: uint16_t sdmpow;
66: uint16_t rtcce;
67: uint16_t pcicd;
68: uint16_t voyagerrts;
69: uint16_t cfrst;
70: uint16_t admrts;
71: uint16_t extrst;
72: uint16_t cfcdintclr;
73: uint16_t keyctlclr;
74: uint16_t pad0;
75: uint16_t pad1;
76: uint16_t verreg;
77: uint16_t inport;
78: uint16_t outport;
79: uint16_t bverreg;
80:
81: /* output pin */
82: qemu_irq irl;
83: } r2d_fpga_t;
84:
85: enum r2d_fpga_irq {
86: PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
87: SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
88: NR_IRQS
89: };
90:
91: static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
92: [CF_IDE] = { 1, 1<<9 },
93: [CF_CD] = { 2, 1<<8 },
94: [PCI_INTA] = { 9, 1<<14 },
95: [PCI_INTB] = { 10, 1<<13 },
96: [PCI_INTC] = { 3, 1<<12 },
97: [PCI_INTD] = { 0, 1<<11 },
98: [SM501] = { 4, 1<<10 },
99: [KEY] = { 5, 1<<6 },
100: [RTC_A] = { 6, 1<<5 },
101: [RTC_T] = { 7, 1<<4 },
102: [SDCARD] = { 8, 1<<7 },
103: [EXT] = { 11, 1<<0 },
104: [TP] = { 12, 1<<15 },
105: };
106:
107: static void update_irl(r2d_fpga_t *fpga)
108: {
109: int i, irl = 15;
110: for (i = 0; i < NR_IRQS; i++)
111: if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
112: if (irqtab[i].irl < irl)
113: irl = irqtab[i].irl;
114: qemu_set_irq(fpga->irl, irl ^ 15);
115: }
116:
117: static void r2d_fpga_irq_set(void *opaque, int n, int level)
118: {
119: r2d_fpga_t *fpga = opaque;
120: if (level)
121: fpga->irlmon |= irqtab[n].msk;
122: else
123: fpga->irlmon &= ~irqtab[n].msk;
124: update_irl(fpga);
125: }
126:
127: static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
128: {
129: r2d_fpga_t *s = opaque;
130:
131: switch (addr) {
132: case PA_IRLMSK:
133: return s->irlmsk;
134: case PA_OUTPORT:
135: return s->outport;
136: case PA_POWOFF:
1.1.1.6 ! root 137: return 0x00;
1.1.1.2 root 138: case PA_VERREG:
139: return 0x10;
140: }
141:
142: return 0;
143: }
144:
145: static void
146: r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
147: {
148: r2d_fpga_t *s = opaque;
149:
150: switch (addr) {
151: case PA_IRLMSK:
152: s->irlmsk = value;
153: update_irl(s);
154: break;
155: case PA_OUTPORT:
156: s->outport = value;
157: break;
158: case PA_POWOFF:
1.1.1.6 ! root 159: if (value & 1) {
! 160: qemu_system_shutdown_request();
! 161: }
! 162: break;
1.1.1.2 root 163: case PA_VERREG:
164: /* Discard writes */
165: break;
166: }
167: }
168:
1.1.1.5 root 169: static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
1.1.1.2 root 170: r2d_fpga_read,
171: r2d_fpga_read,
172: NULL,
173: };
174:
1.1.1.5 root 175: static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
1.1.1.2 root 176: r2d_fpga_write,
177: r2d_fpga_write,
178: NULL,
179: };
180:
181: static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
182: {
183: int iomemtype;
184: r2d_fpga_t *s;
185:
186: s = qemu_mallocz(sizeof(r2d_fpga_t));
187:
188: s->irl = irl;
189:
1.1.1.4 root 190: iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
1.1.1.2 root 191: r2d_fpga_writefn, s);
192: cpu_register_physical_memory(base, 0x40, iomemtype);
193: return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
194: }
195:
1.1.1.5 root 196: static void r2d_pci_set_irq(void *opaque, int n, int l)
1.1.1.2 root 197: {
1.1.1.5 root 198: qemu_irq *p = opaque;
199:
1.1.1.2 root 200: qemu_set_irq(p[n], l);
201: }
202:
203: static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
204: {
205: const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
206: return intx[d->devfn >> 3];
207: }
208:
1.1.1.6 ! root 209: static struct __attribute__((__packed__))
! 210: {
! 211: int mount_root_rdonly;
! 212: int ramdisk_flags;
! 213: int orig_root_dev;
! 214: int loader_type;
! 215: int initrd_start;
! 216: int initrd_size;
! 217:
! 218: char pad[232];
! 219:
! 220: char kernel_cmdline[256];
! 221: } boot_params;
! 222:
1.1.1.4 root 223: static void r2d_init(ram_addr_t ram_size,
1.1.1.2 root 224: const char *boot_device,
1.1 root 225: const char *kernel_filename, const char *kernel_cmdline,
226: const char *initrd_filename, const char *cpu_model)
227: {
228: CPUState *env;
229: struct SH7750State *s;
1.1.1.4 root 230: ram_addr_t sdram_addr;
1.1.1.2 root 231: qemu_irq *irq;
1.1.1.5 root 232: DriveInfo *dinfo;
1.1.1.2 root 233: int i;
1.1 root 234:
235: if (!cpu_model)
1.1.1.2 root 236: cpu_model = "SH7751R";
1.1 root 237:
238: env = cpu_init(cpu_model);
239: if (!env) {
240: fprintf(stderr, "Unable to find CPU definition\n");
241: exit(1);
242: }
243:
244: /* Allocate memory space */
1.1.1.6 ! root 245: sdram_addr = qemu_ram_alloc(NULL, "r2d.sdram", SDRAM_SIZE);
1.1.1.2 root 246: cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
1.1 root 247: /* Register peripherals */
248: s = sh7750_init(env);
1.1.1.2 root 249: irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
1.1.1.6 ! root 250: sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
1.1.1.2 root 251:
1.1.1.4 root 252: sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
1.1.1.2 root 253:
254: /* onboard CF (True IDE mode, Master only). */
1.1.1.6 ! root 255: dinfo = drive_get(IF_IDE, 0, 0);
! 256: mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
! 257: dinfo, NULL);
! 258:
! 259: /* onboard flash memory */
! 260: dinfo = drive_get(IF_PFLASH, 0, 0);
! 261: pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE),
! 262: dinfo ? dinfo->bdrv : NULL, (16 * 1024),
! 263: FLASH_SIZE >> 16,
! 264: 1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
! 265: 0x555, 0x2aa, 0);
1.1.1.2 root 266:
267: /* NIC: rtl8139 on-board, and 2 slots. */
268: for (i = 0; i < nb_nics; i++)
1.1.1.5 root 269: pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);
1.1.1.2 root 270:
1.1.1.6 ! root 271: /* USB keyboard */
! 272: usbdevice_create("keyboard");
! 273:
1.1 root 274: /* Todo: register on board registers */
1.1.1.6 ! root 275: memset(&boot_params, 0, sizeof(boot_params));
! 276:
1.1.1.3 root 277: if (kernel_filename) {
1.1.1.6 ! root 278: int kernel_size;
1.1 root 279:
1.1.1.6 ! root 280: kernel_size = load_image_targphys(kernel_filename,
! 281: SDRAM_BASE + LINUX_LOAD_OFFSET,
! 282: INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
! 283: if (kernel_size < 0) {
! 284: fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
! 285: exit(1);
! 286: }
! 287:
! 288: /* initialization which should be done by firmware */
! 289: stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
! 290: stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
! 291: env->pc = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
! 292: }
! 293:
! 294: if (initrd_filename) {
! 295: int initrd_size;
! 296:
! 297: initrd_size = load_image_targphys(initrd_filename,
! 298: SDRAM_BASE + INITRD_LOAD_OFFSET,
! 299: SDRAM_SIZE - INITRD_LOAD_OFFSET);
! 300:
! 301: if (initrd_size < 0) {
! 302: fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
! 303: exit(1);
! 304: }
! 305:
! 306: /* initialization which should be done by firmware */
! 307: boot_params.loader_type = 1;
! 308: boot_params.initrd_start = INITRD_LOAD_OFFSET;
! 309: boot_params.initrd_size = initrd_size;
1.1 root 310: }
1.1.1.6 ! root 311:
! 312: if (kernel_cmdline) {
! 313: strncpy(boot_params.kernel_cmdline, kernel_cmdline,
! 314: sizeof(boot_params.kernel_cmdline));
! 315: }
! 316:
! 317: rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
! 318: SDRAM_BASE + BOOT_PARAMS_OFFSET);
1.1 root 319: }
320:
1.1.1.4 root 321: static QEMUMachine r2d_machine = {
1.1.1.2 root 322: .name = "r2d",
323: .desc = "r2d-plus board",
324: .init = r2d_init,
1.1 root 325: };
1.1.1.4 root 326:
327: static void r2d_machine_init(void)
328: {
329: qemu_register_machine(&r2d_machine);
330: }
331:
332: machine_init(r2d_machine_init);
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