![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to r2d.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / hw|
Return to r2d.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu / hw |
1.1 root 1: /*
2: * Renesas SH7751R R2D-PLUS emulation
3: *
4: * Copyright (c) 2007 Magnus Damm
1.1.1.2 root 5: * Copyright (c) 2008 Paul Mundt
1.1 root 6: *
7: * Permission is hereby granted, free of charge, to any person obtaining a copy
8: * of this software and associated documentation files (the "Software"), to deal
9: * in the Software without restriction, including without limitation the rights
10: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11: * copies of the Software, and to permit persons to whom the Software is
12: * furnished to do so, subject to the following conditions:
13: *
14: * The above copyright notice and this permission notice shall be included in
15: * all copies or substantial portions of the Software.
16: *
17: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23: * THE SOFTWARE.
24: */
25:
1.1.1.7 root 26: #include "sysbus.h"
1.1 root 27: #include "hw.h"
28: #include "sh.h"
1.1.1.2 root 29: #include "devices.h"
1.1 root 30: #include "sysemu.h"
31: #include "boards.h"
1.1.1.2 root 32: #include "pci.h"
33: #include "net.h"
34: #include "sh7750_regs.h"
1.1.1.5 root 35: #include "ide.h"
36: #include "loader.h"
1.1.1.6 root 37: #include "usb.h"
38: #include "flash.h"
1.1.1.7 root 39: #include "blockdev.h"
1.1.1.8 root 40: #include "exec-memory.h"
1.1.1.6 root 41:
42: #define FLASH_BASE 0x00000000
43: #define FLASH_SIZE 0x02000000
1.1 root 44:
45: #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
46: #define SDRAM_SIZE 0x04000000
47:
1.1.1.2 root 48: #define SM501_VRAM_SIZE 0x800000
49:
1.1.1.6 root 50: #define BOOT_PARAMS_OFFSET 0x0010000
1.1.1.3 root 51: /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
1.1.1.6 root 52: #define LINUX_LOAD_OFFSET 0x0800000
53: #define INITRD_LOAD_OFFSET 0x1800000
1.1.1.3 root 54:
1.1.1.2 root 55: #define PA_IRLMSK 0x00
56: #define PA_POWOFF 0x30
57: #define PA_VERREG 0x32
58: #define PA_OUTPORT 0x36
59:
60: typedef struct {
61: uint16_t bcr;
62: uint16_t irlmsk;
63: uint16_t irlmon;
64: uint16_t cfctl;
65: uint16_t cfpow;
66: uint16_t dispctl;
67: uint16_t sdmpow;
68: uint16_t rtcce;
69: uint16_t pcicd;
70: uint16_t voyagerrts;
71: uint16_t cfrst;
72: uint16_t admrts;
73: uint16_t extrst;
74: uint16_t cfcdintclr;
75: uint16_t keyctlclr;
76: uint16_t pad0;
77: uint16_t pad1;
78: uint16_t verreg;
79: uint16_t inport;
80: uint16_t outport;
81: uint16_t bverreg;
82:
83: /* output pin */
84: qemu_irq irl;
1.1.1.8 root 85: MemoryRegion iomem;
1.1.1.2 root 86: } r2d_fpga_t;
87:
88: enum r2d_fpga_irq {
89: PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
90: SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
91: NR_IRQS
92: };
93:
94: static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
95: [CF_IDE] = { 1, 1<<9 },
96: [CF_CD] = { 2, 1<<8 },
97: [PCI_INTA] = { 9, 1<<14 },
98: [PCI_INTB] = { 10, 1<<13 },
99: [PCI_INTC] = { 3, 1<<12 },
100: [PCI_INTD] = { 0, 1<<11 },
101: [SM501] = { 4, 1<<10 },
102: [KEY] = { 5, 1<<6 },
103: [RTC_A] = { 6, 1<<5 },
104: [RTC_T] = { 7, 1<<4 },
105: [SDCARD] = { 8, 1<<7 },
106: [EXT] = { 11, 1<<0 },
107: [TP] = { 12, 1<<15 },
108: };
109:
110: static void update_irl(r2d_fpga_t *fpga)
111: {
112: int i, irl = 15;
113: for (i = 0; i < NR_IRQS; i++)
114: if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
115: if (irqtab[i].irl < irl)
116: irl = irqtab[i].irl;
117: qemu_set_irq(fpga->irl, irl ^ 15);
118: }
119:
120: static void r2d_fpga_irq_set(void *opaque, int n, int level)
121: {
122: r2d_fpga_t *fpga = opaque;
123: if (level)
124: fpga->irlmon |= irqtab[n].msk;
125: else
126: fpga->irlmon &= ~irqtab[n].msk;
127: update_irl(fpga);
128: }
129:
130: static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
131: {
132: r2d_fpga_t *s = opaque;
133:
134: switch (addr) {
135: case PA_IRLMSK:
136: return s->irlmsk;
137: case PA_OUTPORT:
138: return s->outport;
139: case PA_POWOFF:
1.1.1.6 root 140: return 0x00;
1.1.1.2 root 141: case PA_VERREG:
142: return 0x10;
143: }
144:
145: return 0;
146: }
147:
148: static void
149: r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
150: {
151: r2d_fpga_t *s = opaque;
152:
153: switch (addr) {
154: case PA_IRLMSK:
155: s->irlmsk = value;
156: update_irl(s);
157: break;
158: case PA_OUTPORT:
159: s->outport = value;
160: break;
161: case PA_POWOFF:
1.1.1.6 root 162: if (value & 1) {
163: qemu_system_shutdown_request();
164: }
165: break;
1.1.1.2 root 166: case PA_VERREG:
167: /* Discard writes */
168: break;
169: }
170: }
171:
1.1.1.8 root 172: static const MemoryRegionOps r2d_fpga_ops = {
173: .old_mmio = {
174: .read = { r2d_fpga_read, r2d_fpga_read, NULL, },
175: .write = { r2d_fpga_write, r2d_fpga_write, NULL, },
176: },
177: .endianness = DEVICE_NATIVE_ENDIAN,
1.1.1.2 root 178: };
179:
1.1.1.8 root 180: static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
181: target_phys_addr_t base, qemu_irq irl)
1.1.1.2 root 182: {
183: r2d_fpga_t *s;
184:
1.1.1.8 root 185: s = g_malloc0(sizeof(r2d_fpga_t));
1.1.1.2 root 186:
187: s->irl = irl;
188:
1.1.1.8 root 189: memory_region_init_io(&s->iomem, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
190: memory_region_add_subregion(sysmem, base, &s->iomem);
1.1.1.2 root 191: return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
192: }
193:
1.1.1.7 root 194: typedef struct ResetData {
1.1.1.9 ! root 195: CPUSH4State *env;
1.1.1.7 root 196: uint32_t vector;
197: } ResetData;
1.1.1.2 root 198:
1.1.1.7 root 199: static void main_cpu_reset(void *opaque)
1.1.1.2 root 200: {
1.1.1.7 root 201: ResetData *s = (ResetData *)opaque;
1.1.1.9 ! root 202: CPUSH4State *env = s->env;
1.1.1.7 root 203:
1.1.1.9 ! root 204: cpu_state_reset(env);
1.1.1.7 root 205: env->pc = s->vector;
1.1.1.2 root 206: }
207:
1.1.1.8 root 208: static struct QEMU_PACKED
1.1.1.6 root 209: {
210: int mount_root_rdonly;
211: int ramdisk_flags;
212: int orig_root_dev;
213: int loader_type;
214: int initrd_start;
215: int initrd_size;
216:
217: char pad[232];
218:
219: char kernel_cmdline[256];
220: } boot_params;
221:
1.1.1.4 root 222: static void r2d_init(ram_addr_t ram_size,
1.1.1.2 root 223: const char *boot_device,
1.1 root 224: const char *kernel_filename, const char *kernel_cmdline,
225: const char *initrd_filename, const char *cpu_model)
226: {
1.1.1.9 ! root 227: CPUSH4State *env;
1.1.1.7 root 228: ResetData *reset_info;
1.1 root 229: struct SH7750State *s;
1.1.1.8 root 230: MemoryRegion *sdram = g_new(MemoryRegion, 1);
1.1.1.2 root 231: qemu_irq *irq;
1.1.1.5 root 232: DriveInfo *dinfo;
1.1.1.2 root 233: int i;
1.1.1.9 ! root 234: DeviceState *dev;
! 235: SysBusDevice *busdev;
1.1.1.8 root 236: MemoryRegion *address_space_mem = get_system_memory();
1.1 root 237:
238: if (!cpu_model)
1.1.1.2 root 239: cpu_model = "SH7751R";
1.1 root 240:
241: env = cpu_init(cpu_model);
242: if (!env) {
243: fprintf(stderr, "Unable to find CPU definition\n");
244: exit(1);
245: }
1.1.1.8 root 246: reset_info = g_malloc0(sizeof(ResetData));
1.1.1.7 root 247: reset_info->env = env;
248: reset_info->vector = env->pc;
249: qemu_register_reset(main_cpu_reset, reset_info);
1.1 root 250:
251: /* Allocate memory space */
1.1.1.9 ! root 252: memory_region_init_ram(sdram, "r2d.sdram", SDRAM_SIZE);
! 253: vmstate_register_ram_global(sdram);
1.1.1.8 root 254: memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
1.1 root 255: /* Register peripherals */
1.1.1.9 ! root 256: s = sh7750_init(env, address_space_mem);
1.1.1.8 root 257: irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
1.1.1.9 ! root 258:
! 259: dev = qdev_create(NULL, "sh_pci");
! 260: busdev = sysbus_from_qdev(dev);
! 261: qdev_init_nofail(dev);
! 262: sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
! 263: sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
! 264: sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
! 265: sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
! 266: sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
! 267: sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
1.1.1.2 root 268:
1.1.1.8 root 269: sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE,
270: irq[SM501], serial_hds[2]);
1.1.1.2 root 271:
272: /* onboard CF (True IDE mode, Master only). */
1.1.1.6 root 273: dinfo = drive_get(IF_IDE, 0, 0);
1.1.1.9 ! root 274: mmio_ide_init(0x14001000, 0x1400080c, address_space_mem, irq[CF_IDE], 1,
1.1.1.6 root 275: dinfo, NULL);
276:
277: /* onboard flash memory */
278: dinfo = drive_get(IF_PFLASH, 0, 0);
1.1.1.8 root 279: pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
1.1.1.6 root 280: dinfo ? dinfo->bdrv : NULL, (16 * 1024),
281: FLASH_SIZE >> 16,
282: 1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
283: 0x555, 0x2aa, 0);
1.1.1.2 root 284:
285: /* NIC: rtl8139 on-board, and 2 slots. */
286: for (i = 0; i < nb_nics; i++)
1.1.1.5 root 287: pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);
1.1.1.2 root 288:
1.1.1.6 root 289: /* USB keyboard */
290: usbdevice_create("keyboard");
291:
1.1 root 292: /* Todo: register on board registers */
1.1.1.6 root 293: memset(&boot_params, 0, sizeof(boot_params));
294:
1.1.1.3 root 295: if (kernel_filename) {
1.1.1.6 root 296: int kernel_size;
1.1 root 297:
1.1.1.6 root 298: kernel_size = load_image_targphys(kernel_filename,
299: SDRAM_BASE + LINUX_LOAD_OFFSET,
300: INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
301: if (kernel_size < 0) {
302: fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
303: exit(1);
304: }
305:
306: /* initialization which should be done by firmware */
307: stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
308: stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
1.1.1.7 root 309: reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
1.1.1.6 root 310: }
311:
312: if (initrd_filename) {
313: int initrd_size;
314:
315: initrd_size = load_image_targphys(initrd_filename,
316: SDRAM_BASE + INITRD_LOAD_OFFSET,
317: SDRAM_SIZE - INITRD_LOAD_OFFSET);
318:
319: if (initrd_size < 0) {
320: fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
321: exit(1);
322: }
323:
324: /* initialization which should be done by firmware */
325: boot_params.loader_type = 1;
326: boot_params.initrd_start = INITRD_LOAD_OFFSET;
327: boot_params.initrd_size = initrd_size;
1.1 root 328: }
1.1.1.6 root 329:
330: if (kernel_cmdline) {
331: strncpy(boot_params.kernel_cmdline, kernel_cmdline,
332: sizeof(boot_params.kernel_cmdline));
333: }
334:
335: rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
336: SDRAM_BASE + BOOT_PARAMS_OFFSET);
1.1 root 337: }
338:
1.1.1.4 root 339: static QEMUMachine r2d_machine = {
1.1.1.2 root 340: .name = "r2d",
341: .desc = "r2d-plus board",
342: .init = r2d_init,
1.1 root 343: };
1.1.1.4 root 344:
345: static void r2d_machine_init(void)
346: {
347: qemu_register_machine(&r2d_machine);
348: }
349:
350: machine_init(r2d_machine_init);
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.