Annotation of qemu/hw/realview_gic.c, revision 1.1.1.1

1.1       root        1: /*
                      2:  * ARM RealView Emulation Baseboard Interrupt Controller
                      3:  *
                      4:  * Copyright (c) 2006-2007 CodeSourcery.
                      5:  * Written by Paul Brook
                      6:  *
                      7:  * This code is licenced under the GPL.
                      8:  */
                      9: 
                     10: #include "hw.h"
                     11: #include "primecell.h"
                     12: 
                     13: #define GIC_NIRQ 96
                     14: #define NCPU 1
                     15: 
                     16: /* Only a single "CPU" interface is present.  */
                     17: static inline int
                     18: gic_get_current_cpu(void)
                     19: {
                     20:   return 0;
                     21: }
                     22: 
                     23: #include "arm_gic.c"
                     24: 
                     25: static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset)
                     26: {
                     27:     gic_state *s = (gic_state *)opaque;
                     28:     offset -= s->base;
                     29:     return gic_cpu_read(s, gic_get_current_cpu(), offset);
                     30: }
                     31: 
                     32: static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset,
                     33:                           uint32_t value)
                     34: {
                     35:     gic_state *s = (gic_state *)opaque;
                     36:     offset -= s->base;
                     37:     gic_cpu_write(s, gic_get_current_cpu(), offset, value);
                     38: }
                     39: 
                     40: static CPUReadMemoryFunc *realview_gic_cpu_readfn[] = {
                     41:    realview_gic_cpu_read,
                     42:    realview_gic_cpu_read,
                     43:    realview_gic_cpu_read
                     44: };
                     45: 
                     46: static CPUWriteMemoryFunc *realview_gic_cpu_writefn[] = {
                     47:    realview_gic_cpu_write,
                     48:    realview_gic_cpu_write,
                     49:    realview_gic_cpu_write
                     50: };
                     51: 
                     52: qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq)
                     53: {
                     54:     gic_state *s;
                     55:     int iomemtype;
                     56: 
                     57:     s = gic_init(base, &parent_irq);
                     58:     if (!s)
                     59:         return NULL;
                     60:     iomemtype = cpu_register_io_memory(0, realview_gic_cpu_readfn,
                     61:                                        realview_gic_cpu_writefn, s);
                     62:     cpu_register_physical_memory(base, 0x00001000, iomemtype);
                     63:     return s->in;
                     64: }

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