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Annotation of qemu/hw/realview_gic.c, revision 1.1.1.5

1.1       root        1: /*
                      2:  * ARM RealView Emulation Baseboard Interrupt Controller
                      3:  *
                      4:  * Copyright (c) 2006-2007 CodeSourcery.
                      5:  * Written by Paul Brook
                      6:  *
                      7:  * This code is licenced under the GPL.
                      8:  */
                      9: 
1.1.1.3   root       10: #include "sysbus.h"
1.1       root       11: 
                     12: #define GIC_NIRQ 96
                     13: #define NCPU 1
                     14: 
                     15: /* Only a single "CPU" interface is present.  */
                     16: static inline int
                     17: gic_get_current_cpu(void)
                     18: {
                     19:   return 0;
                     20: }
                     21: 
                     22: #include "arm_gic.c"
                     23: 
1.1.1.3   root       24: typedef struct {
                     25:     gic_state gic;
                     26:     int iomemtype;
                     27: } RealViewGICState;
                     28: 
1.1       root       29: static uint32_t realview_gic_cpu_read(void *opaque, target_phys_addr_t offset)
                     30: {
                     31:     gic_state *s = (gic_state *)opaque;
                     32:     return gic_cpu_read(s, gic_get_current_cpu(), offset);
                     33: }
                     34: 
                     35: static void realview_gic_cpu_write(void *opaque, target_phys_addr_t offset,
                     36:                           uint32_t value)
                     37: {
                     38:     gic_state *s = (gic_state *)opaque;
                     39:     gic_cpu_write(s, gic_get_current_cpu(), offset, value);
                     40: }
                     41: 
1.1.1.4   root       42: static CPUReadMemoryFunc * const realview_gic_cpu_readfn[] = {
1.1       root       43:    realview_gic_cpu_read,
                     44:    realview_gic_cpu_read,
                     45:    realview_gic_cpu_read
                     46: };
                     47: 
1.1.1.4   root       48: static CPUWriteMemoryFunc * const realview_gic_cpu_writefn[] = {
1.1       root       49:    realview_gic_cpu_write,
                     50:    realview_gic_cpu_write,
                     51:    realview_gic_cpu_write
                     52: };
                     53: 
1.1.1.3   root       54: static void realview_gic_map(SysBusDevice *dev, target_phys_addr_t base)
1.1       root       55: {
1.1.1.3   root       56:     RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
                     57:     cpu_register_physical_memory(base, 0x1000, s->iomemtype);
                     58:     cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype);
                     59: }
                     60: 
1.1.1.4   root       61: static int realview_gic_init(SysBusDevice *dev)
1.1.1.3   root       62: {
                     63:     RealViewGICState *s = FROM_SYSBUSGIC(RealViewGICState, dev);
1.1       root       64: 
1.1.1.3   root       65:     gic_init(&s->gic);
                     66:     s->iomemtype = cpu_register_io_memory(realview_gic_cpu_readfn,
1.1.1.5 ! root       67:                                           realview_gic_cpu_writefn, s,
        !            68:                                           DEVICE_NATIVE_ENDIAN);
1.1.1.3   root       69:     sysbus_init_mmio_cb(dev, 0x2000, realview_gic_map);
1.1.1.4   root       70:     return 0;
1.1       root       71: }
1.1.1.3   root       72: 
                     73: static void realview_gic_register_devices(void)
                     74: {
                     75:     sysbus_register_dev("realview_gic", sizeof(RealViewGICState),
                     76:                         realview_gic_init);
                     77: }
                     78: 
                     79: device_init(realview_gic_register_devices)