Annotation of qemu/hw/sh7750_regs.h, revision 1.1.1.1

1.1       root        1: /*
                      2:  * SH-7750 memory-mapped registers
                      3:  * This file based on information provided in the following document:
                      4:  * "Hitachi SuperH (tm) RISC engine. SH7750 Series (SH7750, SH7750S)
                      5:  *  Hardware Manual"
                      6:  *  Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
                      7:  *
                      8:  * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
                      9:  * Author: Alexandra Kossovsky <sasha@oktet.ru>
                     10:  *         Victor V. Vengerov <vvv@oktet.ru>
                     11:  *
                     12:  * The license and distribution terms for this file may be
                     13:  * found in the file LICENSE in this distribution or at
                     14:  *  http://www.rtems.com/license/LICENSE.
                     15:  * 
                     16:  * @(#) sh7750_regs.h,v 1.2.4.1 2003/09/04 18:46:00 joel Exp
                     17:  */
                     18: 
                     19: #ifndef __SH7750_REGS_H__
                     20: #define __SH7750_REGS_H__
                     21: 
                     22: /* 
                     23:  * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address)  and 
                     24:  * in 0x1f000000 - 0x1fffffff (area 7 address)
                     25:  */
                     26: #define SH7750_P4_BASE       0xff000000        /* Accessable only in 
                     27:                                           priveleged mode */
                     28: #define SH7750_A7_BASE       0x1f000000        /* Accessable only using TLB */
                     29: 
                     30: #define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))
                     31: #define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))
                     32: 
                     33: /* 
                     34:  * MMU Registers 
                     35:  */
                     36: 
                     37: /* Page Table Entry High register - PTEH */
                     38: #define SH7750_PTEH_REGOFS    0x000000 /* offset */
                     39: #define SH7750_PTEH           SH7750_P4_REG32(SH7750_PTEH_REGOFS)
                     40: #define SH7750_PTEH_A7        SH7750_A7_REG32(SH7750_PTEH_REGOFS)
                     41: #define SH7750_PTEH_VPN       0xfffffd00       /* Virtual page number */
                     42: #define SH7750_PTEH_VPN_S     10
                     43: #define SH7750_PTEH_ASID      0x000000ff       /* Address space identifier */
                     44: #define SH7750_PTEH_ASID_S    0
                     45: 
                     46: /* Page Table Entry Low register - PTEL */
                     47: #define SH7750_PTEL_REGOFS    0x000004 /* offset */
                     48: #define SH7750_PTEL           SH7750_P4_REG32(SH7750_PTEL_REGOFS)
                     49: #define SH7750_PTEL_A7        SH7750_A7_REG32(SH7750_PTEL_REGOFS)
                     50: #define SH7750_PTEL_PPN       0x1ffffc00       /* Physical page number */
                     51: #define SH7750_PTEL_PPN_S     10
                     52: #define SH7750_PTEL_V         0x00000100       /* Validity (0-entry is invalid) */
                     53: #define SH7750_PTEL_SZ1       0x00000080       /* Page size bit 1 */
                     54: #define SH7750_PTEL_SZ0       0x00000010       /* Page size bit 0 */
                     55: #define SH7750_PTEL_SZ_1KB    0x00000000       /*   1-kbyte page */
                     56: #define SH7750_PTEL_SZ_4KB    0x00000010       /*   4-kbyte page */
                     57: #define SH7750_PTEL_SZ_64KB   0x00000080       /*   64-kbyte page */
                     58: #define SH7750_PTEL_SZ_1MB    0x00000090       /*   1-Mbyte page */
                     59: #define SH7750_PTEL_PR        0x00000060       /* Protection Key Data */
                     60: #define SH7750_PTEL_PR_ROPO   0x00000000       /*   read-only in priv mode */
                     61: #define SH7750_PTEL_PR_RWPO   0x00000020       /*   read-write in priv mode */
                     62: #define SH7750_PTEL_PR_ROPU   0x00000040       /*   read-only in priv or user mode */
                     63: #define SH7750_PTEL_PR_RWPU   0x00000060       /*   read-write in priv or user mode */
                     64: #define SH7750_PTEL_C         0x00000008       /* Cacheability 
                     65:                                                   (0 - page not cacheable) */
                     66: #define SH7750_PTEL_D         0x00000004       /* Dirty bit (1 - write has been 
                     67:                                                   performed to a page) */
                     68: #define SH7750_PTEL_SH        0x00000002       /* Share Status bit (1 - page are
                     69:                                                   shared by processes) */
                     70: #define SH7750_PTEL_WT        0x00000001       /* Write-through bit, specifies the
                     71:                                                   cache write mode:
                     72:                                                   0 - Copy-back mode
                     73:                                                   1 - Write-through mode */
                     74: 
                     75: /* Page Table Entry Assistance register - PTEA */
                     76: #define SH7750_PTEA_REGOFS    0x000034 /* offset */
                     77: #define SH7750_PTEA           SH7750_P4_REG32(SH7750_PTEA_REGOFS)
                     78: #define SH7750_PTEA_A7        SH7750_A7_REG32(SH7750_PTEA_REGOFS)
                     79: #define SH7750_PTEA_TC        0x00000008       /* Timing Control bit
                     80:                                                   0 - use area 5 wait states
                     81:                                                   1 - use area 6 wait states */
                     82: #define SH7750_PTEA_SA        0x00000007       /* Space Attribute bits: */
                     83: #define SH7750_PTEA_SA_UNDEF  0x00000000       /*    0 - undefined */
                     84: #define SH7750_PTEA_SA_IOVAR  0x00000001       /*    1 - variable-size I/O space */
                     85: #define SH7750_PTEA_SA_IO8    0x00000002       /*    2 - 8-bit I/O space */
                     86: #define SH7750_PTEA_SA_IO16   0x00000003       /*    3 - 16-bit I/O space */
                     87: #define SH7750_PTEA_SA_CMEM8  0x00000004       /*    4 - 8-bit common memory space */
                     88: #define SH7750_PTEA_SA_CMEM16 0x00000005       /*    5 - 16-bit common memory space */
                     89: #define SH7750_PTEA_SA_AMEM8  0x00000006       /*    6 - 8-bit attr memory space */
                     90: #define SH7750_PTEA_SA_AMEM16 0x00000007       /*    7 - 16-bit attr memory space */
                     91: 
                     92: 
                     93: /* Translation table base register */
                     94: #define SH7750_TTB_REGOFS     0x000008 /* offset */
                     95: #define SH7750_TTB            SH7750_P4_REG32(SH7750_TTB_REGOFS)
                     96: #define SH7750_TTB_A7         SH7750_A7_REG32(SH7750_TTB_REGOFS)
                     97: 
                     98: /* TLB exeption address register - TEA */
                     99: #define SH7750_TEA_REGOFS     0x00000c /* offset */
                    100: #define SH7750_TEA            SH7750_P4_REG32(SH7750_TEA_REGOFS)
                    101: #define SH7750_TEA_A7         SH7750_A7_REG32(SH7750_TEA_REGOFS)
                    102: 
                    103: /* MMU control register - MMUCR */
                    104: #define SH7750_MMUCR_REGOFS   0x000010 /* offset */
                    105: #define SH7750_MMUCR          SH7750_P4_REG32(SH7750_MMUCR_REGOFS)
                    106: #define SH7750_MMUCR_A7       SH7750_A7_REG32(SH7750_MMUCR_REGOFS)
                    107: #define SH7750_MMUCR_AT       0x00000001       /* Address translation bit */
                    108: #define SH7750_MMUCR_TI       0x00000004       /* TLB invalidate */
                    109: #define SH7750_MMUCR_SV       0x00000100       /* Single Virtual Mode bit */
                    110: #define SH7750_MMUCR_SQMD     0x00000200       /* Store Queue Mode bit */
                    111: #define SH7750_MMUCR_URC      0x0000FC00       /* UTLB Replace Counter */
                    112: #define SH7750_MMUCR_URC_S    10
                    113: #define SH7750_MMUCR_URB      0x00FC0000       /* UTLB Replace Boundary */
                    114: #define SH7750_MMUCR_URB_S    18
                    115: #define SH7750_MMUCR_LRUI     0xFC000000       /* Least Recently Used ITLB */
                    116: #define SH7750_MMUCR_LRUI_S   26
                    117: 
                    118: 
                    119: 
                    120: 
                    121: /*
                    122:  * Cache registers
                    123:  *   IC -- instructions cache
                    124:  *   OC -- operand cache
                    125:  */
                    126: 
                    127: /* Cache Control Register - CCR */
                    128: #define SH7750_CCR_REGOFS     0x00001c /* offset */
                    129: #define SH7750_CCR            SH7750_P4_REG32(SH7750_CCR_REGOFS)
                    130: #define SH7750_CCR_A7         SH7750_A7_REG32(SH7750_CCR_REGOFS)
                    131: 
                    132: #define SH7750_CCR_IIX      0x00008000 /* IC index enable bit */
                    133: #define SH7750_CCR_ICI      0x00000800 /* IC invalidation bit: 
                    134:                                           set it to clear IC */
                    135: #define SH7750_CCR_ICE      0x00000100 /* IC enable bit */
                    136: #define SH7750_CCR_OIX      0x00000080 /* OC index enable bit */
                    137: #define SH7750_CCR_ORA      0x00000020 /* OC RAM enable bit 
                    138:                                           if you set OCE = 0, 
                    139:                                           you should set ORA = 0 */
                    140: #define SH7750_CCR_OCI      0x00000008 /* OC invalidation bit */
                    141: #define SH7750_CCR_CB       0x00000004 /* Copy-back bit for P1 area */
                    142: #define SH7750_CCR_WT       0x00000002 /* Write-through bit for P0,U0,P3 area */
                    143: #define SH7750_CCR_OCE      0x00000001 /* OC enable bit */
                    144: 
                    145: /* Queue address control register 0 - QACR0 */
                    146: #define SH7750_QACR0_REGOFS   0x000038 /* offset */
                    147: #define SH7750_QACR0          SH7750_P4_REG32(SH7750_QACR0_REGOFS)
                    148: #define SH7750_QACR0_A7       SH7750_A7_REG32(SH7750_QACR0_REGOFS)
                    149: 
                    150: /* Queue address control register 1 - QACR1 */
                    151: #define SH7750_QACR1_REGOFS   0x00003c /* offset */
                    152: #define SH7750_QACR1          SH7750_P4_REG32(SH7750_QACR1_REGOFS)
                    153: #define SH7750_QACR1_A7       SH7750_A7_REG32(SH7750_QACR1_REGOFS)
                    154: 
                    155: 
                    156: /*
                    157:  * Exeption-related registers
                    158:  */
                    159: 
                    160: /* Immediate data for TRAPA instuction - TRA */
                    161: #define SH7750_TRA_REGOFS     0x000020 /* offset */
                    162: #define SH7750_TRA            SH7750_P4_REG32(SH7750_TRA_REGOFS)
                    163: #define SH7750_TRA_A7         SH7750_A7_REG32(SH7750_TRA_REGOFS)
                    164: 
                    165: #define SH7750_TRA_IMM      0x000003fd /* Immediate data operand */
                    166: #define SH7750_TRA_IMM_S    2
                    167: 
                    168: /* Exeption event register - EXPEVT */
                    169: #define SH7750_EXPEVT_REGOFS  0x000024
                    170: #define SH7750_EXPEVT         SH7750_P4_REG32(SH7750_EXPEVT_REGOFS)
                    171: #define SH7750_EXPEVT_A7      SH7750_A7_REG32(SH7750_EXPEVT_REGOFS)
                    172: 
                    173: #define SH7750_EXPEVT_EX      0x00000fff       /* Exeption code */
                    174: #define SH7750_EXPEVT_EX_S    0
                    175: 
                    176: /* Interrupt event register */
                    177: #define SH7750_INTEVT_REGOFS  0x000028
                    178: #define SH7750_INTEVT         SH7750_P4_REG32(SH7750_INTEVT_REGOFS)
                    179: #define SH7750_INTEVT_A7      SH7750_A7_REG32(SH7750_INTEVT_REGOFS)
                    180: #define SH7750_INTEVT_EX    0x00000fff /* Exeption code */
                    181: #define SH7750_INTEVT_EX_S  0
                    182: 
                    183: /*
                    184:  * Exception/interrupt codes
                    185:  */
                    186: #define SH7750_EVT_TO_NUM(evt)  ((evt) >> 5)
                    187: 
                    188: /* Reset exception category */
                    189: #define SH7750_EVT_POWER_ON_RST        0x000   /* Power-on reset */
                    190: #define SH7750_EVT_MANUAL_RST          0x020   /* Manual reset */
                    191: #define SH7750_EVT_TLB_MULT_HIT        0x140   /* TLB multiple-hit exception */
                    192: 
                    193: /* General exception category */
                    194: #define SH7750_EVT_USER_BREAK          0x1E0   /* User break */
                    195: #define SH7750_EVT_IADDR_ERR           0x0E0   /* Instruction address error */
                    196: #define SH7750_EVT_TLB_READ_MISS       0x040   /* ITLB miss exception /
                    197:                                                   DTLB miss exception (read) */
                    198: #define SH7750_EVT_TLB_READ_PROTV      0x0A0   /* ITLB protection violation /
                    199:                                                   DTLB protection violation (read) */
                    200: #define SH7750_EVT_ILLEGAL_INSTR       0x180   /* General Illegal Instruction
                    201:                                                   exception */
                    202: #define SH7750_EVT_SLOT_ILLEGAL_INSTR  0x1A0   /* Slot Illegal Instruction
                    203:                                                   exception */
                    204: #define SH7750_EVT_FPU_DISABLE         0x800   /* General FPU disable exception */
                    205: #define SH7750_EVT_SLOT_FPU_DISABLE    0x820   /* Slot FPU disable exception */
                    206: #define SH7750_EVT_DATA_READ_ERR       0x0E0   /* Data address error (read) */
                    207: #define SH7750_EVT_DATA_WRITE_ERR      0x100   /* Data address error (write) */
                    208: #define SH7750_EVT_DTLB_WRITE_MISS     0x060   /* DTLB miss exception (write) */
                    209: #define SH7750_EVT_DTLB_WRITE_PROTV    0x0C0   /* DTLB protection violation
                    210:                                                   exception (write) */
                    211: #define SH7750_EVT_FPU_EXCEPTION       0x120   /* FPU exception */
                    212: #define SH7750_EVT_INITIAL_PGWRITE     0x080   /* Initial Page Write exception */
                    213: #define SH7750_EVT_TRAPA               0x160   /* Unconditional trap (TRAPA) */
                    214: 
                    215: /* Interrupt exception category */
                    216: #define SH7750_EVT_NMI                 0x1C0   /* Non-maskable interrupt */
                    217: #define SH7750_EVT_IRQ0                0x200   /* External Interrupt 0 */
                    218: #define SH7750_EVT_IRQ1                0x220   /* External Interrupt 1 */
                    219: #define SH7750_EVT_IRQ2                0x240   /* External Interrupt 2 */
                    220: #define SH7750_EVT_IRQ3                0x260   /* External Interrupt 3 */
                    221: #define SH7750_EVT_IRQ4                0x280   /* External Interrupt 4 */
                    222: #define SH7750_EVT_IRQ5                0x2A0   /* External Interrupt 5 */
                    223: #define SH7750_EVT_IRQ6                0x2C0   /* External Interrupt 6 */
                    224: #define SH7750_EVT_IRQ7                0x2E0   /* External Interrupt 7 */
                    225: #define SH7750_EVT_IRQ8                0x300   /* External Interrupt 8 */
                    226: #define SH7750_EVT_IRQ9                0x320   /* External Interrupt 9 */
                    227: #define SH7750_EVT_IRQA                0x340   /* External Interrupt A */
                    228: #define SH7750_EVT_IRQB                0x360   /* External Interrupt B */
                    229: #define SH7750_EVT_IRQC                0x380   /* External Interrupt C */
                    230: #define SH7750_EVT_IRQD                0x3A0   /* External Interrupt D */
                    231: #define SH7750_EVT_IRQE                0x3C0   /* External Interrupt E */
                    232: 
                    233: /* Peripheral Module Interrupts - Timer Unit (TMU) */
                    234: #define SH7750_EVT_TUNI0               0x400   /* TMU Underflow Interrupt 0 */
                    235: #define SH7750_EVT_TUNI1               0x420   /* TMU Underflow Interrupt 1 */
                    236: #define SH7750_EVT_TUNI2               0x440   /* TMU Underflow Interrupt 2 */
                    237: #define SH7750_EVT_TICPI2              0x460   /* TMU Input Capture Interrupt 2 */
                    238: 
                    239: /* Peripheral Module Interrupts - Real-Time Clock (RTC) */
                    240: #define SH7750_EVT_RTC_ATI             0x480   /* Alarm Interrupt Request */
                    241: #define SH7750_EVT_RTC_PRI             0x4A0   /* Periodic Interrupt Request */
                    242: #define SH7750_EVT_RTC_CUI             0x4C0   /* Carry Interrupt Request */
                    243: 
                    244: /* Peripheral Module Interrupts - Serial Communication Interface (SCI) */
                    245: #define SH7750_EVT_SCI_ERI             0x4E0   /* Receive Error */
                    246: #define SH7750_EVT_SCI_RXI             0x500   /* Receive Data Register Full */
                    247: #define SH7750_EVT_SCI_TXI             0x520   /* Transmit Data Register Empty */
                    248: #define SH7750_EVT_SCI_TEI             0x540   /* Transmit End */
                    249: 
                    250: /* Peripheral Module Interrupts - Watchdog Timer (WDT) */
                    251: #define SH7750_EVT_WDT_ITI             0x560   /* Interval Timer Interrupt
                    252:                                                   (used when WDT operates in
                    253:                                                   interval timer mode) */
                    254: 
                    255: /* Peripheral Module Interrupts - Memory Refresh Unit (REF) */
                    256: #define SH7750_EVT_REF_RCMI            0x580   /* Compare-match Interrupt */
                    257: #define SH7750_EVT_REF_ROVI            0x5A0   /* Refresh Counter Overflow 
                    258:                                                   interrupt */
                    259: 
                    260: /* Peripheral Module Interrupts - Hitachi User Debug Interface (H-UDI) */
                    261: #define SH7750_EVT_HUDI                0x600   /* UDI interrupt */
                    262: 
                    263: /* Peripheral Module Interrupts - General-Purpose I/O (GPIO) */
                    264: #define SH7750_EVT_GPIO                0x620   /* GPIO Interrupt */
                    265: 
                    266: /* Peripheral Module Interrupts - DMA Controller (DMAC) */
                    267: #define SH7750_EVT_DMAC_DMTE0          0x640   /* DMAC 0 Transfer End Interrupt */
                    268: #define SH7750_EVT_DMAC_DMTE1          0x660   /* DMAC 1 Transfer End Interrupt */
                    269: #define SH7750_EVT_DMAC_DMTE2          0x680   /* DMAC 2 Transfer End Interrupt */
                    270: #define SH7750_EVT_DMAC_DMTE3          0x6A0   /* DMAC 3 Transfer End Interrupt */
                    271: #define SH7750_EVT_DMAC_DMAE           0x6C0   /* DMAC Address Error Interrupt */
                    272: 
                    273: /* Peripheral Module Interrupts - Serial Communication Interface with FIFO */
                    274: /*                                                                  (SCIF) */
                    275: #define SH7750_EVT_SCIF_ERI            0x700   /* Receive Error */
                    276: #define SH7750_EVT_SCIF_RXI            0x720   /* Receive FIFO Data Full or
                    277:                                                   Receive Data ready interrupt */
                    278: #define SH7750_EVT_SCIF_BRI            0x740   /* Break or overrun error */
                    279: #define SH7750_EVT_SCIF_TXI            0x760   /* Transmit FIFO Data Empty */
                    280: 
                    281: /*
                    282:  * Power Management
                    283:  */
                    284: #define SH7750_STBCR_REGOFS   0xC00004 /* offset */
                    285: #define SH7750_STBCR          SH7750_P4_REG32(SH7750_STBCR_REGOFS)
                    286: #define SH7750_STBCR_A7       SH7750_A7_REG32(SH7750_STBCR_REGOFS)
                    287: 
                    288: #define SH7750_STBCR_STBY     0x80     /* Specifies a transition to standby mode:
                    289:                                           0 - Transition to SLEEP mode on SLEEP
                    290:                                           1 - Transition to STANDBY mode on SLEEP */
                    291: #define SH7750_STBCR_PHZ      0x40     /* State of peripheral module pins in
                    292:                                           standby mode:
                    293:                                           0 - normal state
                    294:                                           1 - high-impendance state */
                    295: 
                    296: #define SH7750_STBCR_PPU      0x20     /* Peripheral module pins pull-up controls */
                    297: #define SH7750_STBCR_MSTP4    0x10     /* Stopping the clock supply to DMAC */
                    298: #define SH7750_STBCR_DMAC_STP SH7750_STBCR_MSTP4
                    299: #define SH7750_STBCR_MSTP3    0x08     /* Stopping the clock supply to SCIF */
                    300: #define SH7750_STBCR_SCIF_STP SH7750_STBCR_MSTP3
                    301: #define SH7750_STBCR_MSTP2    0x04     /* Stopping the clock supply to TMU */
                    302: #define SH7750_STBCR_TMU_STP  SH7750_STBCR_MSTP2
                    303: #define SH7750_STBCR_MSTP1    0x02     /* Stopping the clock supply to RTC */
                    304: #define SH7750_STBCR_RTC_STP  SH7750_STBCR_MSTP1
                    305: #define SH7750_STBCR_MSPT0    0x01     /* Stopping the clock supply to SCI */
                    306: #define SH7750_STBCR_SCI_STP  SH7750_STBCR_MSTP0
                    307: 
                    308: #define SH7750_STBCR_STBY     0x80
                    309: 
                    310: 
                    311: #define SH7750_STBCR2_REGOFS  0xC00010 /* offset */
                    312: #define SH7750_STBCR2         SH7750_P4_REG32(SH7750_STBCR2_REGOFS)
                    313: #define SH7750_STBCR2_A7      SH7750_A7_REG32(SH7750_STBCR2_REGOFS)
                    314: 
                    315: #define SH7750_STBCR2_DSLP    0x80     /* Specifies transition to deep sleep mode:
                    316:                                           0 - transition to sleep or standby mode
                    317:                                           as it is specified in STBY bit
                    318:                                           1 - transition to deep sleep mode on
                    319:                                           execution of SLEEP instruction */
                    320: #define SH7750_STBCR2_MSTP6   0x02     /* Stopping the clock supply to Store Queue
                    321:                                           in the cache controller */
                    322: #define SH7750_STBCR2_SQ_STP  SH7750_STBCR2_MSTP6
                    323: #define SH7750_STBCR2_MSTP5   0x01     /* Stopping the clock supply to the User
                    324:                                           Break Controller (UBC) */
                    325: #define SH7750_STBCR2_UBC_STP SH7750_STBCR2_MSTP5
                    326: 
                    327: /*
                    328:  * Clock Pulse Generator (CPG)
                    329:  */
                    330: #define SH7750_FRQCR_REGOFS   0xC00000 /* offset */
                    331: #define SH7750_FRQCR          SH7750_P4_REG32(SH7750_FRQCR_REGOFS)
                    332: #define SH7750_FRQCR_A7       SH7750_A7_REG32(SH7750_FRQCR_REGOFS)
                    333: 
                    334: #define SH7750_FRQCR_CKOEN    0x0800   /* Clock Output Enable 
                    335:                                           0 - CKIO pin goes to HiZ/pullup
                    336:                                           1 - Clock is output from CKIO */
                    337: #define SH7750_FRQCR_PLL1EN   0x0400   /* PLL circuit 1 enable */
                    338: #define SH7750_FRQCR_PLL2EN   0x0200   /* PLL circuit 2 enable */
                    339: 
                    340: #define SH7750_FRQCR_IFC      0x01C0   /* CPU clock frequency division ratio: */
                    341: #define SH7750_FRQCR_IFCDIV1  0x0000   /*    0 - * 1 */
                    342: #define SH7750_FRQCR_IFCDIV2  0x0040   /*    1 - * 1/2 */
                    343: #define SH7750_FRQCR_IFCDIV3  0x0080   /*    2 - * 1/3 */
                    344: #define SH7750_FRQCR_IFCDIV4  0x00C0   /*    3 - * 1/4 */
                    345: #define SH7750_FRQCR_IFCDIV6  0x0100   /*    4 - * 1/6 */
                    346: #define SH7750_FRQCR_IFCDIV8  0x0140   /*    5 - * 1/8 */
                    347: 
                    348: #define SH7750_FRQCR_BFC      0x0038   /* Bus clock frequency division ratio: */
                    349: #define SH7750_FRQCR_BFCDIV1  0x0000   /*    0 - * 1 */
                    350: #define SH7750_FRQCR_BFCDIV2  0x0008   /*    1 - * 1/2 */
                    351: #define SH7750_FRQCR_BFCDIV3  0x0010   /*    2 - * 1/3 */
                    352: #define SH7750_FRQCR_BFCDIV4  0x0018   /*    3 - * 1/4 */
                    353: #define SH7750_FRQCR_BFCDIV6  0x0020   /*    4 - * 1/6 */
                    354: #define SH7750_FRQCR_BFCDIV8  0x0028   /*    5 - * 1/8 */
                    355: 
                    356: #define SH7750_FRQCR_PFC      0x0007   /* Peripheral module clock frequency
                    357:                                           division ratio: */
                    358: #define SH7750_FRQCR_PFCDIV2  0x0000   /*    0 - * 1/2 */
                    359: #define SH7750_FRQCR_PFCDIV3  0x0001   /*    1 - * 1/3 */
                    360: #define SH7750_FRQCR_PFCDIV4  0x0002   /*    2 - * 1/4 */
                    361: #define SH7750_FRQCR_PFCDIV6  0x0003   /*    3 - * 1/6 */
                    362: #define SH7750_FRQCR_PFCDIV8  0x0004   /*    4 - * 1/8 */
                    363: 
                    364: /*
                    365:  * Watchdog Timer (WDT)
                    366:  */
                    367: 
                    368: /* Watchdog Timer Counter register - WTCNT */
                    369: #define SH7750_WTCNT_REGOFS   0xC00008 /* offset */
                    370: #define SH7750_WTCNT          SH7750_P4_REG32(SH7750_WTCNT_REGOFS)
                    371: #define SH7750_WTCNT_A7       SH7750_A7_REG32(SH7750_WTCNT_REGOFS)
                    372: #define SH7750_WTCNT_KEY      0x5A00   /* When WTCNT byte register written,
                    373:                                           you have to set the upper byte to
                    374:                                           0x5A */
                    375: 
                    376: /* Watchdog Timer Control/Status register - WTCSR */
                    377: #define SH7750_WTCSR_REGOFS   0xC0000C /* offset */
                    378: #define SH7750_WTCSR          SH7750_P4_REG32(SH7750_WTCSR_REGOFS)
                    379: #define SH7750_WTCSR_A7       SH7750_A7_REG32(SH7750_WTCSR_REGOFS)
                    380: #define SH7750_WTCSR_KEY      0xA500   /* When WTCSR byte register written,
                    381:                                           you have to set the upper byte to
                    382:                                           0xA5 */
                    383: #define SH7750_WTCSR_TME      0x80     /* Timer enable (1-upcount start) */
                    384: #define SH7750_WTCSR_MODE     0x40     /* Timer Mode Select: */
                    385: #define SH7750_WTCSR_MODE_WT  0x40     /*    Watchdog Timer Mode */
                    386: #define SH7750_WTCSR_MODE_IT  0x00     /*    Interval Timer Mode */
                    387: #define SH7750_WTCSR_RSTS     0x20     /* Reset Select: */
                    388: #define SH7750_WTCSR_RST_MAN  0x20     /*    Manual Reset */
                    389: #define SH7750_WTCSR_RST_PWR  0x00     /*    Power-on Reset */
                    390: #define SH7750_WTCSR_WOVF     0x10     /* Watchdog Timer Overflow Flag */
                    391: #define SH7750_WTCSR_IOVF     0x08     /* Interval Timer Overflow Flag */
                    392: #define SH7750_WTCSR_CKS      0x07     /* Clock Select: */
                    393: #define SH7750_WTCSR_CKS_DIV32   0x00  /*   1/32 of frequency divider 2 input */
                    394: #define SH7750_WTCSR_CKS_DIV64   0x01  /*   1/64 */
                    395: #define SH7750_WTCSR_CKS_DIV128  0x02  /*   1/128 */
                    396: #define SH7750_WTCSR_CKS_DIV256  0x03  /*   1/256 */
                    397: #define SH7750_WTCSR_CKS_DIV512  0x04  /*   1/512 */
                    398: #define SH7750_WTCSR_CKS_DIV1024 0x05  /*   1/1024 */
                    399: #define SH7750_WTCSR_CKS_DIV2048 0x06  /*   1/2048 */
                    400: #define SH7750_WTCSR_CKS_DIV4096 0x07  /*   1/4096 */
                    401: 
                    402: /*
                    403:  * Real-Time Clock (RTC)
                    404:  */
                    405: /* 64-Hz Counter Register (byte, read-only) - R64CNT */
                    406: #define SH7750_R64CNT_REGOFS  0xC80000 /* offset */
                    407: #define SH7750_R64CNT         SH7750_P4_REG32(SH7750_R64CNT_REGOFS)
                    408: #define SH7750_R64CNT_A7      SH7750_A7_REG32(SH7750_R64CNT_REGOFS)
                    409: 
                    410: /* Second Counter Register (byte, BCD-coded) - RSECCNT */
                    411: #define SH7750_RSECCNT_REGOFS 0xC80004 /* offset */
                    412: #define SH7750_RSECCNT        SH7750_P4_REG32(SH7750_RSECCNT_REGOFS)
                    413: #define SH7750_RSECCNT_A7     SH7750_A7_REG32(SH7750_RSECCNT_REGOFS)
                    414: 
                    415: /* Minute Counter Register (byte, BCD-coded) - RMINCNT */
                    416: #define SH7750_RMINCNT_REGOFS 0xC80008 /* offset */
                    417: #define SH7750_RMINCNT        SH7750_P4_REG32(SH7750_RMINCNT_REGOFS)
                    418: #define SH7750_RMINCNT_A7     SH7750_A7_REG32(SH7750_RMINCNT_REGOFS)
                    419: 
                    420: /* Hour Counter Register (byte, BCD-coded) - RHRCNT */
                    421: #define SH7750_RHRCNT_REGOFS  0xC8000C /* offset */
                    422: #define SH7750_RHRCNT         SH7750_P4_REG32(SH7750_RHRCNT_REGOFS)
                    423: #define SH7750_RHRCNT_A7      SH7750_A7_REG32(SH7750_RHRCNT_REGOFS)
                    424: 
                    425: /* Day-of-Week Counter Register (byte) - RWKCNT */
                    426: #define SH7750_RWKCNT_REGOFS  0xC80010 /* offset */
                    427: #define SH7750_RWKCNT         SH7750_P4_REG32(SH7750_RWKCNT_REGOFS)
                    428: #define SH7750_RWKCNT_A7      SH7750_A7_REG32(SH7750_RWKCNT_REGOFS)
                    429: 
                    430: #define SH7750_RWKCNT_SUN     0        /* Sunday */
                    431: #define SH7750_RWKCNT_MON     1        /* Monday */
                    432: #define SH7750_RWKCNT_TUE     2        /* Tuesday */
                    433: #define SH7750_RWKCNT_WED     3        /* Wednesday */
                    434: #define SH7750_RWKCNT_THU     4        /* Thursday */
                    435: #define SH7750_RWKCNT_FRI     5        /* Friday */
                    436: #define SH7750_RWKCNT_SAT     6        /* Saturday */
                    437: 
                    438: /* Day Counter Register (byte, BCD-coded) - RDAYCNT */
                    439: #define SH7750_RDAYCNT_REGOFS 0xC80014 /* offset */
                    440: #define SH7750_RDAYCNT        SH7750_P4_REG32(SH7750_RDAYCNT_REGOFS)
                    441: #define SH7750_RDAYCNT_A7     SH7750_A7_REG32(SH7750_RDAYCNT_REGOFS)
                    442: 
                    443: /* Month Counter Register (byte, BCD-coded) - RMONCNT */
                    444: #define SH7750_RMONCNT_REGOFS 0xC80018 /* offset */
                    445: #define SH7750_RMONCNT        SH7750_P4_REG32(SH7750_RMONCNT_REGOFS)
                    446: #define SH7750_RMONCNT_A7     SH7750_A7_REG32(SH7750_RMONCNT_REGOFS)
                    447: 
                    448: /* Year Counter Register (half, BCD-coded) - RYRCNT */
                    449: #define SH7750_RYRCNT_REGOFS  0xC8001C /* offset */
                    450: #define SH7750_RYRCNT         SH7750_P4_REG32(SH7750_RYRCNT_REGOFS)
                    451: #define SH7750_RYRCNT_A7      SH7750_A7_REG32(SH7750_RYRCNT_REGOFS)
                    452: 
                    453: /* Second Alarm Register (byte, BCD-coded) - RSECAR */
                    454: #define SH7750_RSECAR_REGOFS  0xC80020 /* offset */
                    455: #define SH7750_RSECAR         SH7750_P4_REG32(SH7750_RSECAR_REGOFS)
                    456: #define SH7750_RSECAR_A7      SH7750_A7_REG32(SH7750_RSECAR_REGOFS)
                    457: #define SH7750_RSECAR_ENB     0x80     /* Second Alarm Enable */
                    458: 
                    459: /* Minute Alarm Register (byte, BCD-coded) - RMINAR */
                    460: #define SH7750_RMINAR_REGOFS  0xC80024 /* offset */
                    461: #define SH7750_RMINAR         SH7750_P4_REG32(SH7750_RMINAR_REGOFS)
                    462: #define SH7750_RMINAR_A7      SH7750_A7_REG32(SH7750_RMINAR_REGOFS)
                    463: #define SH7750_RMINAR_ENB     0x80     /* Minute Alarm Enable */
                    464: 
                    465: /* Hour Alarm Register (byte, BCD-coded) - RHRAR */
                    466: #define SH7750_RHRAR_REGOFS   0xC80028 /* offset */
                    467: #define SH7750_RHRAR          SH7750_P4_REG32(SH7750_RHRAR_REGOFS)
                    468: #define SH7750_RHRAR_A7       SH7750_A7_REG32(SH7750_RHRAR_REGOFS)
                    469: #define SH7750_RHRAR_ENB      0x80     /* Hour Alarm Enable */
                    470: 
                    471: /* Day-of-Week Alarm Register (byte) - RWKAR */
                    472: #define SH7750_RWKAR_REGOFS   0xC8002C /* offset */
                    473: #define SH7750_RWKAR          SH7750_P4_REG32(SH7750_RWKAR_REGOFS)
                    474: #define SH7750_RWKAR_A7       SH7750_A7_REG32(SH7750_RWKAR_REGOFS)
                    475: #define SH7750_RWKAR_ENB      0x80     /* Day-of-week Alarm Enable */
                    476: 
                    477: #define SH7750_RWKAR_SUN      0        /* Sunday */
                    478: #define SH7750_RWKAR_MON      1        /* Monday */
                    479: #define SH7750_RWKAR_TUE      2        /* Tuesday */
                    480: #define SH7750_RWKAR_WED      3        /* Wednesday */
                    481: #define SH7750_RWKAR_THU      4        /* Thursday */
                    482: #define SH7750_RWKAR_FRI      5        /* Friday */
                    483: #define SH7750_RWKAR_SAT      6        /* Saturday */
                    484: 
                    485: /* Day Alarm Register (byte, BCD-coded) - RDAYAR */
                    486: #define SH7750_RDAYAR_REGOFS  0xC80030 /* offset */
                    487: #define SH7750_RDAYAR         SH7750_P4_REG32(SH7750_RDAYAR_REGOFS)
                    488: #define SH7750_RDAYAR_A7      SH7750_A7_REG32(SH7750_RDAYAR_REGOFS)
                    489: #define SH7750_RDAYAR_ENB     0x80     /* Day Alarm Enable */
                    490: 
                    491: /* Month Counter Register (byte, BCD-coded) - RMONAR */
                    492: #define SH7750_RMONAR_REGOFS  0xC80034 /* offset */
                    493: #define SH7750_RMONAR         SH7750_P4_REG32(SH7750_RMONAR_REGOFS)
                    494: #define SH7750_RMONAR_A7      SH7750_A7_REG32(SH7750_RMONAR_REGOFS)
                    495: #define SH7750_RMONAR_ENB     0x80     /* Month Alarm Enable */
                    496: 
                    497: /* RTC Control Register 1 (byte) - RCR1 */
                    498: #define SH7750_RCR1_REGOFS    0xC80038 /* offset */
                    499: #define SH7750_RCR1           SH7750_P4_REG32(SH7750_RCR1_REGOFS)
                    500: #define SH7750_RCR1_A7        SH7750_A7_REG32(SH7750_RCR1_REGOFS)
                    501: #define SH7750_RCR1_CF        0x80     /* Carry Flag */
                    502: #define SH7750_RCR1_CIE       0x10     /* Carry Interrupt Enable */
                    503: #define SH7750_RCR1_AIE       0x08     /* Alarm Interrupt Enable */
                    504: #define SH7750_RCR1_AF        0x01     /* Alarm Flag */
                    505: 
                    506: /* RTC Control Register 2 (byte) - RCR2 */
                    507: #define SH7750_RCR2_REGOFS    0xC8003C /* offset */
                    508: #define SH7750_RCR2           SH7750_P4_REG32(SH7750_RCR2_REGOFS)
                    509: #define SH7750_RCR2_A7        SH7750_A7_REG32(SH7750_RCR2_REGOFS)
                    510: #define SH7750_RCR2_PEF        0x80    /* Periodic Interrupt Flag */
                    511: #define SH7750_RCR2_PES        0x70    /* Periodic Interrupt Enable: */
                    512: #define SH7750_RCR2_PES_DIS    0x00    /*   Periodic Interrupt Disabled */
                    513: #define SH7750_RCR2_PES_DIV256 0x10    /*   Generated at 1/256 sec interval */
                    514: #define SH7750_RCR2_PES_DIV64  0x20    /*   Generated at 1/64 sec interval */
                    515: #define SH7750_RCR2_PES_DIV16  0x30    /*   Generated at 1/16 sec interval */
                    516: #define SH7750_RCR2_PES_DIV4   0x40    /*   Generated at 1/4 sec interval */
                    517: #define SH7750_RCR2_PES_DIV2   0x50    /*   Generated at 1/2 sec interval */
                    518: #define SH7750_RCR2_PES_x1     0x60    /*   Generated at 1 sec interval */
                    519: #define SH7750_RCR2_PES_x2     0x70    /*   Generated at 2 sec interval */
                    520: #define SH7750_RCR2_RTCEN      0x08    /* RTC Crystal Oscillator is Operated */
                    521: #define SH7750_RCR2_ADJ        0x04    /* 30-Second Adjastment */
                    522: #define SH7750_RCR2_RESET      0x02    /* Frequency divider circuits are reset */
                    523: #define SH7750_RCR2_START      0x01    /* 0 - sec, min, hr, day-of-week, month,
                    524:                                           year counters are stopped
                    525:                                           1 - sec, min, hr, day-of-week, month,
                    526:                                           year counters operate normally */
                    527: 
                    528: 
                    529: /*
                    530:  * Timer Unit (TMU)
                    531:  */
                    532: /* Timer Output Control Register (byte) - TOCR */
                    533: #define SH7750_TOCR_REGOFS    0xD80000 /* offset */
                    534: #define SH7750_TOCR           SH7750_P4_REG32(SH7750_TOCR_REGOFS)
                    535: #define SH7750_TOCR_A7        SH7750_A7_REG32(SH7750_TOCR_REGOFS)
                    536: #define SH7750_TOCR_TCOE      0x01     /* Timer Clock Pin Control:
                    537:                                           0 - TCLK is used as external clock
                    538:                                           input or input capture control
                    539:                                           1 - TCLK is used as on-chip RTC
                    540:                                           output clock pin */
                    541: 
                    542: /* Timer Start Register (byte) - TSTR */
                    543: #define SH7750_TSTR_REGOFS    0xD80004 /* offset */
                    544: #define SH7750_TSTR           SH7750_P4_REG32(SH7750_TSTR_REGOFS)
                    545: #define SH7750_TSTR_A7        SH7750_A7_REG32(SH7750_TSTR_REGOFS)
                    546: #define SH7750_TSTR_STR2      0x04     /* TCNT2 performs count operations */
                    547: #define SH7750_TSTR_STR1      0x02     /* TCNT1 performs count operations */
                    548: #define SH7750_TSTR_STR0      0x01     /* TCNT0 performs count operations */
                    549: #define SH7750_TSTR_STR(n)    (1 << (n))
                    550: 
                    551: /* Timer Constant Register - TCOR0, TCOR1, TCOR2 */
                    552: #define SH7750_TCOR_REGOFS(n) (0xD80008 + ((n)*12))    /* offset */
                    553: #define SH7750_TCOR(n)        SH7750_P4_REG32(SH7750_TCOR_REGOFS(n))
                    554: #define SH7750_TCOR_A7(n)     SH7750_A7_REG32(SH7750_TCOR_REGOFS(n))
                    555: #define SH7750_TCOR0          SH7750_TCOR(0)
                    556: #define SH7750_TCOR1          SH7750_TCOR(1)
                    557: #define SH7750_TCOR2          SH7750_TCOR(2)
                    558: #define SH7750_TCOR0_A7       SH7750_TCOR_A7(0)
                    559: #define SH7750_TCOR1_A7       SH7750_TCOR_A7(1)
                    560: #define SH7750_TCOR2_A7       SH7750_TCOR_A7(2)
                    561: 
                    562: /* Timer Counter Register - TCNT0, TCNT1, TCNT2 */
                    563: #define SH7750_TCNT_REGOFS(n) (0xD8000C + ((n)*12))    /* offset */
                    564: #define SH7750_TCNT(n)        SH7750_P4_REG32(SH7750_TCNT_REGOFS(n))
                    565: #define SH7750_TCNT_A7(n)     SH7750_A7_REG32(SH7750_TCNT_REGOFS(n))
                    566: #define SH7750_TCNT0          SH7750_TCNT(0)
                    567: #define SH7750_TCNT1          SH7750_TCNT(1)
                    568: #define SH7750_TCNT2          SH7750_TCNT(2)
                    569: #define SH7750_TCNT0_A7       SH7750_TCNT_A7(0)
                    570: #define SH7750_TCNT1_A7       SH7750_TCNT_A7(1)
                    571: #define SH7750_TCNT2_A7       SH7750_TCNT_A7(2)
                    572: 
                    573: /* Timer Control Register (half) - TCR0, TCR1, TCR2 */
                    574: #define SH7750_TCR_REGOFS(n)  (0xD80010 + ((n)*12))    /* offset */
                    575: #define SH7750_TCR(n)         SH7750_P4_REG32(SH7750_TCR_REGOFS(n))
                    576: #define SH7750_TCR_A7(n)      SH7750_A7_REG32(SH7750_TCR_REGOFS(n))
                    577: #define SH7750_TCR0           SH7750_TCR(0)
                    578: #define SH7750_TCR1           SH7750_TCR(1)
                    579: #define SH7750_TCR2           SH7750_TCR(2)
                    580: #define SH7750_TCR0_A7        SH7750_TCR_A7(0)
                    581: #define SH7750_TCR1_A7        SH7750_TCR_A7(1)
                    582: #define SH7750_TCR2_A7        SH7750_TCR_A7(2)
                    583: 
                    584: #define SH7750_TCR2_ICPF       0x200   /* Input Capture Interrupt Flag
                    585:                                           (1 - input capture has occured) */
                    586: #define SH7750_TCR_UNF         0x100   /* Underflow flag */
                    587: #define SH7750_TCR2_ICPE       0x0C0   /* Input Capture Control: */
                    588: #define SH7750_TCR2_ICPE_DIS   0x000   /*   Input Capture function is not used */
                    589: #define SH7750_TCR2_ICPE_NOINT 0x080   /*   Input Capture function is used, but
                    590:                                           input capture interrupt is not
                    591:                                           enabled */
                    592: #define SH7750_TCR2_ICPE_INT   0x0C0   /*   Input Capture function is used,
                    593:                                           input capture interrupt enabled */
                    594: #define SH7750_TCR_UNIE        0x020   /* Underflow Interrupt Control
                    595:                                           (1 - underflow interrupt enabled) */
                    596: #define SH7750_TCR_CKEG        0x018   /* Clock Edge selection: */
                    597: #define SH7750_TCR_CKEG_RAISE  0x000   /*   Count/capture on rising edge */
                    598: #define SH7750_TCR_CKEG_FALL   0x008   /*   Count/capture on falling edge */
                    599: #define SH7750_TCR_CKEG_BOTH   0x018   /*   Count/capture on both rising and
                    600:                                           falling edges */
                    601: #define SH7750_TCR_TPSC         0x007  /* Timer prescaler */
                    602: #define SH7750_TCR_TPSC_DIV4    0x000  /*   Counts on peripheral clock/4 */
                    603: #define SH7750_TCR_TPSC_DIV16   0x001  /*   Counts on peripheral clock/16 */
                    604: #define SH7750_TCR_TPSC_DIV64   0x002  /*   Counts on peripheral clock/64 */
                    605: #define SH7750_TCR_TPSC_DIV256  0x003  /*   Counts on peripheral clock/256 */
                    606: #define SH7750_TCR_TPSC_DIV1024 0x004  /*   Counts on peripheral clock/1024 */
                    607: #define SH7750_TCR_TPSC_RTC     0x006  /*   Counts on on-chip RTC output clk */
                    608: #define SH7750_TCR_TPSC_EXT     0x007  /*   Counts on external clock */
                    609: 
                    610: /* Input Capture Register (read-only) - TCPR2 */
                    611: #define SH7750_TCPR2_REGOFS   0xD8002C /* offset */
                    612: #define SH7750_TCPR2          SH7750_P4_REG32(SH7750_TCPR2_REGOFS)
                    613: #define SH7750_TCPR2_A7       SH7750_A7_REG32(SH7750_TCPR2_REGOFS)
                    614: 
                    615: /*
                    616:  * Bus State Controller - BSC
                    617:  */
                    618: /* Bus Control Register 1 - BCR1 */
                    619: #define SH7750_BCR1_REGOFS    0x800000 /* offset */
                    620: #define SH7750_BCR1           SH7750_P4_REG32(SH7750_BCR1_REGOFS)
                    621: #define SH7750_BCR1_A7        SH7750_A7_REG32(SH7750_BCR1_REGOFS)
                    622: #define SH7750_BCR1_ENDIAN    0x80000000       /* Endianness (1 - little endian) */
                    623: #define SH7750_BCR1_MASTER    0x40000000       /* Master/Slave mode (1-master) */
                    624: #define SH7750_BCR1_A0MPX     0x20000000       /* Area 0 Memory Type (0-SRAM,1-MPX) */
                    625: #define SH7750_BCR1_IPUP      0x02000000       /* Input Pin Pull-up Control:
                    626:                                                   0 - pull-up resistor is on for
                    627:                                                   control input pins
                    628:                                                   1 - pull-up resistor is off */
                    629: #define SH7750_BCR1_OPUP      0x01000000       /* Output Pin Pull-up Control:
                    630:                                                   0 - pull-up resistor is on for
                    631:                                                   control output pins
                    632:                                                   1 - pull-up resistor is off */
                    633: #define SH7750_BCR1_A1MBC     0x00200000       /* Area 1 SRAM Byte Control Mode:
                    634:                                                   0 - Area 1 SRAM is set to
                    635:                                                   normal mode
                    636:                                                   1 - Area 1 SRAM is set to byte
                    637:                                                   control mode */
                    638: #define SH7750_BCR1_A4MBC     0x00100000       /* Area 4 SRAM Byte Control Mode:
                    639:                                                   0 - Area 4 SRAM is set to
                    640:                                                   normal mode
                    641:                                                   1 - Area 4 SRAM is set to byte
                    642:                                                   control mode */
                    643: #define SH7750_BCR1_BREQEN    0x00080000       /* BREQ Enable:
                    644:                                                   0 - External requests are  not
                    645:                                                   accepted
                    646:                                                   1 - External requests are 
                    647:                                                   accepted */
                    648: #define SH7750_BCR1_PSHR      0x00040000       /* Partial Sharing Bit:
                    649:                                                   0 - Master Mode
                    650:                                                   1 - Partial-sharing Mode */
                    651: #define SH7750_BCR1_MEMMPX    0x00020000       /* Area 1 to 6 MPX Interface:
                    652:                                                   0 - SRAM/burst ROM interface
                    653:                                                   1 - MPX interface */
                    654: #define SH7750_BCR1_HIZMEM    0x00008000       /* High Impendance Control. Specifies
                    655:                                                   the state of A[25:0], BS\, CSn\,
                    656:                                                   RD/WR\, CE2A\, CE2B\ in standby
                    657:                                                   mode and when bus is released:
                    658:                                                   0 - signals go to High-Z mode
                    659:                                                   1 - signals driven */
                    660: #define SH7750_BCR1_HIZCNT    0x00004000       /* High Impendance Control. Specifies
                    661:                                                   the state of the RAS\, RAS2\, WEn\,
                    662:                                                   CASn\, DQMn, RD\, CASS\, FRAME\,
                    663:                                                   RD2\ signals in standby mode and
                    664:                                                   when bus is released:
                    665:                                                   0 - signals go to High-Z mode
                    666:                                                   1 - signals driven */
                    667: #define SH7750_BCR1_A0BST     0x00003800       /* Area 0 Burst ROM Control */
                    668: #define SH7750_BCR1_A0BST_SRAM    0x0000       /*   Area 0 accessed as SRAM i/f */
                    669: #define SH7750_BCR1_A0BST_ROM4    0x0800       /*   Area 0 accessed as burst ROM
                    670:                                                   interface, 4 cosequtive access */
                    671: #define SH7750_BCR1_A0BST_ROM8    0x1000       /*   Area 0 accessed as burst ROM
                    672:                                                   interface, 8 cosequtive access */
                    673: #define SH7750_BCR1_A0BST_ROM16   0x1800       /*   Area 0 accessed as burst ROM
                    674:                                                   interface, 16 cosequtive access */
                    675: #define SH7750_BCR1_A0BST_ROM32   0x2000       /*   Area 0 accessed as burst ROM
                    676:                                                   interface, 32 cosequtive access */
                    677: 
                    678: #define SH7750_BCR1_A5BST     0x00000700       /* Area 5 Burst ROM Control */
                    679: #define SH7750_BCR1_A5BST_SRAM    0x0000       /*   Area 5 accessed as SRAM i/f */
                    680: #define SH7750_BCR1_A5BST_ROM4    0x0100       /*   Area 5 accessed as burst ROM
                    681:                                                   interface, 4 cosequtive access */
                    682: #define SH7750_BCR1_A5BST_ROM8    0x0200       /*   Area 5 accessed as burst ROM
                    683:                                                   interface, 8 cosequtive access */
                    684: #define SH7750_BCR1_A5BST_ROM16   0x0300       /*   Area 5 accessed as burst ROM
                    685:                                                   interface, 16 cosequtive access */
                    686: #define SH7750_BCR1_A5BST_ROM32   0x0400       /*   Area 5 accessed as burst ROM
                    687:                                                   interface, 32 cosequtive access */
                    688: 
                    689: #define SH7750_BCR1_A6BST     0x000000E0       /* Area 6 Burst ROM Control */
                    690: #define SH7750_BCR1_A6BST_SRAM    0x0000       /*   Area 6 accessed as SRAM i/f */
                    691: #define SH7750_BCR1_A6BST_ROM4    0x0020       /*   Area 6 accessed as burst ROM
                    692:                                                   interface, 4 cosequtive access */
                    693: #define SH7750_BCR1_A6BST_ROM8    0x0040       /*   Area 6 accessed as burst ROM
                    694:                                                   interface, 8 cosequtive access */
                    695: #define SH7750_BCR1_A6BST_ROM16   0x0060       /*   Area 6 accessed as burst ROM
                    696:                                                   interface, 16 cosequtive access */
                    697: #define SH7750_BCR1_A6BST_ROM32   0x0080       /*   Area 6 accessed as burst ROM
                    698:                                                   interface, 32 cosequtive access */
                    699: 
                    700: #define SH7750_BCR1_DRAMTP        0x001C       /* Area 2 and 3 Memory Type */
                    701: #define SH7750_BCR1_DRAMTP_2SRAM_3SRAM   0x0000        /* Area 2 and 3 are SRAM or MPX
                    702:                                                   interface. */
                    703: #define SH7750_BCR1_DRAMTP_2SRAM_3SDRAM  0x0008        /* Area 2 - SRAM/MPX, Area 3 -
                    704:                                                   synchronous DRAM */
                    705: #define SH7750_BCR1_DRAMTP_2SDRAM_3SDRAM 0x000C        /* Area 2 and 3 are synchronous
                    706:                                                   DRAM interface */
                    707: #define SH7750_BCR1_DRAMTP_2SRAM_3DRAM   0x0010        /* Area 2 - SRAM/MPX, Area 3 -
                    708:                                                   DRAM interface */
                    709: #define SH7750_BCR1_DRAMTP_2DRAM_3DRAM   0x0014        /* Area 2 and 3 are DRAM
                    710:                                                   interface */
                    711: 
                    712: #define SH7750_BCR1_A56PCM    0x00000001       /* Area 5 and 6 Bus Type:
                    713:                                                   0 - SRAM interface
                    714:                                                   1 - PCMCIA interface */
                    715: 
                    716: /* Bus Control Register 2 (half) - BCR2 */
                    717: #define SH7750_BCR2_REGOFS    0x800004 /* offset */
                    718: #define SH7750_BCR2           SH7750_P4_REG32(SH7750_BCR2_REGOFS)
                    719: #define SH7750_BCR2_A7        SH7750_A7_REG32(SH7750_BCR2_REGOFS)
                    720: 
                    721: #define SH7750_BCR2_A0SZ      0xC000   /* Area 0 Bus Width */
                    722: #define SH7750_BCR2_A0SZ_S    14
                    723: #define SH7750_BCR2_A6SZ      0x3000   /* Area 6 Bus Width */
                    724: #define SH7750_BCR2_A6SZ_S    12
                    725: #define SH7750_BCR2_A5SZ      0x0C00   /* Area 5 Bus Width */
                    726: #define SH7750_BCR2_A5SZ_S    10
                    727: #define SH7750_BCR2_A4SZ      0x0300   /* Area 4 Bus Width */
                    728: #define SH7750_BCR2_A4SZ_S    8
                    729: #define SH7750_BCR2_A3SZ      0x00C0   /* Area 3 Bus Width */
                    730: #define SH7750_BCR2_A3SZ_S    6
                    731: #define SH7750_BCR2_A2SZ      0x0030   /* Area 2 Bus Width */
                    732: #define SH7750_BCR2_A2SZ_S    4
                    733: #define SH7750_BCR2_A1SZ      0x000C   /* Area 1 Bus Width */
                    734: #define SH7750_BCR2_A1SZ_S    2
                    735: #define SH7750_BCR2_SZ_64     0        /* 64 bits */
                    736: #define SH7750_BCR2_SZ_8      1        /* 8 bits */
                    737: #define SH7750_BCR2_SZ_16     2        /* 16 bits */
                    738: #define SH7750_BCR2_SZ_32     3        /* 32 bits */
                    739: #define SH7750_BCR2_PORTEN    0x0001   /* Port Function Enable :
                    740:                                           0 - D51-D32 are not used as a port
                    741:                                           1 - D51-D32 are used as a port */
                    742: 
                    743: /* Wait Control Register 1 - WCR1 */
                    744: #define SH7750_WCR1_REGOFS    0x800008 /* offset */
                    745: #define SH7750_WCR1           SH7750_P4_REG32(SH7750_WCR1_REGOFS)
                    746: #define SH7750_WCR1_A7        SH7750_A7_REG32(SH7750_WCR1_REGOFS)
                    747: #define SH7750_WCR1_DMAIW     0x70000000       /* DACK Device Inter-Cycle Idle
                    748:                                                   specification */
                    749: #define SH7750_WCR1_DMAIW_S   28
                    750: #define SH7750_WCR1_A6IW      0x07000000       /* Area 6 Inter-Cycle Idle spec. */
                    751: #define SH7750_WCR1_A6IW_S    24
                    752: #define SH7750_WCR1_A5IW      0x00700000       /* Area 5 Inter-Cycle Idle spec. */
                    753: #define SH7750_WCR1_A5IW_S    20
                    754: #define SH7750_WCR1_A4IW      0x00070000       /* Area 4 Inter-Cycle Idle spec. */
                    755: #define SH7750_WCR1_A4IW_S    16
                    756: #define SH7750_WCR1_A3IW      0x00007000       /* Area 3 Inter-Cycle Idle spec. */
                    757: #define SH7750_WCR1_A3IW_S    12
                    758: #define SH7750_WCR1_A2IW      0x00000700       /* Area 2 Inter-Cycle Idle spec. */
                    759: #define SH7750_WCR1_A2IW_S    8
                    760: #define SH7750_WCR1_A1IW      0x00000070       /* Area 1 Inter-Cycle Idle spec. */
                    761: #define SH7750_WCR1_A1IW_S    4
                    762: #define SH7750_WCR1_A0IW      0x00000007       /* Area 0 Inter-Cycle Idle spec. */
                    763: #define SH7750_WCR1_A0IW_S    0
                    764: 
                    765: /* Wait Control Register 2 - WCR2 */
                    766: #define SH7750_WCR2_REGOFS    0x80000C /* offset */
                    767: #define SH7750_WCR2           SH7750_P4_REG32(SH7750_WCR2_REGOFS)
                    768: #define SH7750_WCR2_A7        SH7750_A7_REG32(SH7750_WCR2_REGOFS)
                    769: 
                    770: #define SH7750_WCR2_A6W       0xE0000000       /* Area 6 Wait Control */
                    771: #define SH7750_WCR2_A6W_S     29
                    772: #define SH7750_WCR2_A6B       0x1C000000       /* Area 6 Burst Pitch */
                    773: #define SH7750_WCR2_A6B_S     26
                    774: #define SH7750_WCR2_A5W       0x03800000       /* Area 5 Wait Control */
                    775: #define SH7750_WCR2_A5W_S     23
                    776: #define SH7750_WCR2_A5B       0x00700000       /* Area 5 Burst Pitch */
                    777: #define SH7750_WCR2_A5B_S     20
                    778: #define SH7750_WCR2_A4W       0x000E0000       /* Area 4 Wait Control */
                    779: #define SH7750_WCR2_A4W_S     17
                    780: #define SH7750_WCR2_A3W       0x0000E000       /* Area 3 Wait Control */
                    781: #define SH7750_WCR2_A3W_S     13
                    782: #define SH7750_WCR2_A2W       0x00000E00       /* Area 2 Wait Control */
                    783: #define SH7750_WCR2_A2W_S     9
                    784: #define SH7750_WCR2_A1W       0x000001C0       /* Area 1 Wait Control */
                    785: #define SH7750_WCR2_A1W_S     6
                    786: #define SH7750_WCR2_A0W       0x00000038       /* Area 0 Wait Control */
                    787: #define SH7750_WCR2_A0W_S     3
                    788: #define SH7750_WCR2_A0B       0x00000007       /* Area 0 Burst Pitch */
                    789: #define SH7750_WCR2_A0B_S     0
                    790: 
                    791: #define SH7750_WCR2_WS0       0        /* 0 wait states inserted */
                    792: #define SH7750_WCR2_WS1       1        /* 1 wait states inserted */
                    793: #define SH7750_WCR2_WS2       2        /* 2 wait states inserted */
                    794: #define SH7750_WCR2_WS3       3        /* 3 wait states inserted */
                    795: #define SH7750_WCR2_WS6       4        /* 6 wait states inserted */
                    796: #define SH7750_WCR2_WS9       5        /* 9 wait states inserted */
                    797: #define SH7750_WCR2_WS12      6        /* 12 wait states inserted */
                    798: #define SH7750_WCR2_WS15      7        /* 15 wait states inserted */
                    799: 
                    800: #define SH7750_WCR2_BPWS0     0        /* 0 wait states inserted from 2nd access */
                    801: #define SH7750_WCR2_BPWS1     1        /* 1 wait states inserted from 2nd access */
                    802: #define SH7750_WCR2_BPWS2     2        /* 2 wait states inserted from 2nd access */
                    803: #define SH7750_WCR2_BPWS3     3        /* 3 wait states inserted from 2nd access */
                    804: #define SH7750_WCR2_BPWS4     4        /* 4 wait states inserted from 2nd access */
                    805: #define SH7750_WCR2_BPWS5     5        /* 5 wait states inserted from 2nd access */
                    806: #define SH7750_WCR2_BPWS6     6        /* 6 wait states inserted from 2nd access */
                    807: #define SH7750_WCR2_BPWS7     7        /* 7 wait states inserted from 2nd access */
                    808: 
                    809: /* DRAM CAS\ Assertion Delay (area 3,2) */
                    810: #define SH7750_WCR2_DRAM_CAS_ASW1   0  /* 1 cycle */
                    811: #define SH7750_WCR2_DRAM_CAS_ASW2   1  /* 2 cycles */
                    812: #define SH7750_WCR2_DRAM_CAS_ASW3   2  /* 3 cycles */
                    813: #define SH7750_WCR2_DRAM_CAS_ASW4   3  /* 4 cycles */
                    814: #define SH7750_WCR2_DRAM_CAS_ASW7   4  /* 7 cycles */
                    815: #define SH7750_WCR2_DRAM_CAS_ASW10  5  /* 10 cycles */
                    816: #define SH7750_WCR2_DRAM_CAS_ASW13  6  /* 13 cycles */
                    817: #define SH7750_WCR2_DRAM_CAS_ASW16  7  /* 16 cycles */
                    818: 
                    819: /* SDRAM CAS\ Latency Cycles */
                    820: #define SH7750_WCR2_SDRAM_CAS_LAT1  1  /* 1 cycle */
                    821: #define SH7750_WCR2_SDRAM_CAS_LAT2  2  /* 2 cycles */
                    822: #define SH7750_WCR2_SDRAM_CAS_LAT3  3  /* 3 cycles */
                    823: #define SH7750_WCR2_SDRAM_CAS_LAT4  4  /* 4 cycles */
                    824: #define SH7750_WCR2_SDRAM_CAS_LAT5  5  /* 5 cycles */
                    825: 
                    826: /* Wait Control Register 3 - WCR3 */
                    827: #define SH7750_WCR3_REGOFS    0x800010 /* offset */
                    828: #define SH7750_WCR3           SH7750_P4_REG32(SH7750_WCR3_REGOFS)
                    829: #define SH7750_WCR3_A7        SH7750_A7_REG32(SH7750_WCR3_REGOFS)
                    830: 
                    831: #define SH7750_WCR3_A6S       0x04000000       /* Area 6 Write Strobe Setup time */
                    832: #define SH7750_WCR3_A6H       0x03000000       /* Area 6 Data Hold Time */
                    833: #define SH7750_WCR3_A6H_S     24
                    834: #define SH7750_WCR3_A5S       0x00400000       /* Area 5 Write Strobe Setup time */
                    835: #define SH7750_WCR3_A5H       0x00300000       /* Area 5 Data Hold Time */
                    836: #define SH7750_WCR3_A5H_S     20
                    837: #define SH7750_WCR3_A4S       0x00040000       /* Area 4 Write Strobe Setup time */
                    838: #define SH7750_WCR3_A4H       0x00030000       /* Area 4 Data Hold Time */
                    839: #define SH7750_WCR3_A4H_S     16
                    840: #define SH7750_WCR3_A3S       0x00004000       /* Area 3 Write Strobe Setup time */
                    841: #define SH7750_WCR3_A3H       0x00003000       /* Area 3 Data Hold Time */
                    842: #define SH7750_WCR3_A3H_S     12
                    843: #define SH7750_WCR3_A2S       0x00000400       /* Area 2 Write Strobe Setup time */
                    844: #define SH7750_WCR3_A2H       0x00000300       /* Area 2 Data Hold Time */
                    845: #define SH7750_WCR3_A2H_S     8
                    846: #define SH7750_WCR3_A1S       0x00000040       /* Area 1 Write Strobe Setup time */
                    847: #define SH7750_WCR3_A1H       0x00000030       /* Area 1 Data Hold Time */
                    848: #define SH7750_WCR3_A1H_S     4
                    849: #define SH7750_WCR3_A0S       0x00000004       /* Area 0 Write Strobe Setup time */
                    850: #define SH7750_WCR3_A0H       0x00000003       /* Area 0 Data Hold Time */
                    851: #define SH7750_WCR3_A0H_S     0
                    852: 
                    853: #define SH7750_WCR3_DHWS_0    0        /* 0 wait states data hold time */
                    854: #define SH7750_WCR3_DHWS_1    1        /* 1 wait states data hold time */
                    855: #define SH7750_WCR3_DHWS_2    2        /* 2 wait states data hold time */
                    856: #define SH7750_WCR3_DHWS_3    3        /* 3 wait states data hold time */
                    857: 
                    858: #define SH7750_MCR_REGOFS     0x800014 /* offset */
                    859: #define SH7750_MCR            SH7750_P4_REG32(SH7750_MCR_REGOFS)
                    860: #define SH7750_MCR_A7         SH7750_A7_REG32(SH7750_MCR_REGOFS)
                    861: 
                    862: #define SH7750_MCR_RASD       0x80000000       /* RAS Down mode */
                    863: #define SH7750_MCR_MRSET      0x40000000       /* SDRAM Mode Register Set */
                    864: #define SH7750_MCR_PALL       0x00000000       /* SDRAM Precharge All cmd. Mode */
                    865: #define SH7750_MCR_TRC        0x38000000       /* RAS Precharge Time at End of
                    866:                                                   Refresh: */
                    867: #define SH7750_MCR_TRC_0      0x00000000       /*    0 */
                    868: #define SH7750_MCR_TRC_3      0x08000000       /*    3 */
                    869: #define SH7750_MCR_TRC_6      0x10000000       /*    6 */
                    870: #define SH7750_MCR_TRC_9      0x18000000       /*    9 */
                    871: #define SH7750_MCR_TRC_12     0x20000000       /*    12 */
                    872: #define SH7750_MCR_TRC_15     0x28000000       /*    15 */
                    873: #define SH7750_MCR_TRC_18     0x30000000       /*    18 */
                    874: #define SH7750_MCR_TRC_21     0x38000000       /*    21 */
                    875: 
                    876: #define SH7750_MCR_TCAS       0x00800000       /* CAS Negation Period */
                    877: #define SH7750_MCR_TCAS_1     0x00000000       /*    1 */
                    878: #define SH7750_MCR_TCAS_2     0x00800000       /*    2 */
                    879: 
                    880: #define SH7750_MCR_TPC        0x00380000       /* DRAM: RAS Precharge Period 
                    881:                                                   SDRAM: minimum number of cycles
                    882:                                                   until the next bank active cmd
                    883:                                                   is output after precharging */
                    884: #define SH7750_MCR_TPC_S      19
                    885: #define SH7750_MCR_TPC_SDRAM_1 0x00000000      /* 1 cycle */
                    886: #define SH7750_MCR_TPC_SDRAM_2 0x00080000      /* 2 cycles */
                    887: #define SH7750_MCR_TPC_SDRAM_3 0x00100000      /* 3 cycles */
                    888: #define SH7750_MCR_TPC_SDRAM_4 0x00180000      /* 4 cycles */
                    889: #define SH7750_MCR_TPC_SDRAM_5 0x00200000      /* 5 cycles */
                    890: #define SH7750_MCR_TPC_SDRAM_6 0x00280000      /* 6 cycles */
                    891: #define SH7750_MCR_TPC_SDRAM_7 0x00300000      /* 7 cycles */
                    892: #define SH7750_MCR_TPC_SDRAM_8 0x00380000      /* 8 cycles */
                    893: 
                    894: #define SH7750_MCR_RCD        0x00030000       /* DRAM: RAS-CAS Assertion Delay time
                    895:                                                   SDRAM: bank active-read/write cmd
                    896:                                                   delay time */
                    897: #define SH7750_MCR_RCD_DRAM_2  0x00000000      /* DRAM delay 2 clocks */
                    898: #define SH7750_MCR_RCD_DRAM_3  0x00010000      /* DRAM delay 3 clocks */
                    899: #define SH7750_MCR_RCD_DRAM_4  0x00020000      /* DRAM delay 4 clocks */
                    900: #define SH7750_MCR_RCD_DRAM_5  0x00030000      /* DRAM delay 5 clocks */
                    901: #define SH7750_MCR_RCD_SDRAM_2 0x00010000      /* DRAM delay 2 clocks */
                    902: #define SH7750_MCR_RCD_SDRAM_3 0x00020000      /* DRAM delay 3 clocks */
                    903: #define SH7750_MCR_RCD_SDRAM_4 0x00030000      /* DRAM delay 4 clocks */
                    904: 
                    905: #define SH7750_MCR_TRWL       0x0000E000       /* SDRAM Write Precharge Delay */
                    906: #define SH7750_MCR_TRWL_1     0x00000000       /*    1 */
                    907: #define SH7750_MCR_TRWL_2     0x00002000       /*    2 */
                    908: #define SH7750_MCR_TRWL_3     0x00004000       /*    3 */
                    909: #define SH7750_MCR_TRWL_4     0x00006000       /*    4 */
                    910: #define SH7750_MCR_TRWL_5     0x00008000       /*    5 */
                    911: 
                    912: #define SH7750_MCR_TRAS       0x00001C00       /* DRAM: CAS-Before-RAS Refresh RAS
                    913:                                                   asserting period
                    914:                                                   SDRAM: Command interval after
                    915:                                                   synchronous DRAM refresh */
                    916: #define SH7750_MCR_TRAS_DRAM_2         0x00000000      /* 2 */
                    917: #define SH7750_MCR_TRAS_DRAM_3         0x00000400      /* 3 */
                    918: #define SH7750_MCR_TRAS_DRAM_4         0x00000800      /* 4 */
                    919: #define SH7750_MCR_TRAS_DRAM_5         0x00000C00      /* 5 */
                    920: #define SH7750_MCR_TRAS_DRAM_6         0x00001000      /* 6 */
                    921: #define SH7750_MCR_TRAS_DRAM_7         0x00001400      /* 7 */
                    922: #define SH7750_MCR_TRAS_DRAM_8         0x00001800      /* 8 */
                    923: #define SH7750_MCR_TRAS_DRAM_9         0x00001C00      /* 9 */
                    924: 
                    925: #define SH7750_MCR_TRAS_SDRAM_TRC_4    0x00000000      /* 4 + TRC */
                    926: #define SH7750_MCR_TRAS_SDRAM_TRC_5    0x00000400      /* 5 + TRC */
                    927: #define SH7750_MCR_TRAS_SDRAM_TRC_6    0x00000800      /* 6 + TRC */
                    928: #define SH7750_MCR_TRAS_SDRAM_TRC_7    0x00000C00      /* 7 + TRC */
                    929: #define SH7750_MCR_TRAS_SDRAM_TRC_8    0x00001000      /* 8 + TRC */
                    930: #define SH7750_MCR_TRAS_SDRAM_TRC_9    0x00001400      /* 9 + TRC */
                    931: #define SH7750_MCR_TRAS_SDRAM_TRC_10   0x00001800      /* 10 + TRC */
                    932: #define SH7750_MCR_TRAS_SDRAM_TRC_11   0x00001C00      /* 11 + TRC */
                    933: 
                    934: #define SH7750_MCR_BE         0x00000200       /* Burst Enable */
                    935: #define SH7750_MCR_SZ         0x00000180       /* Memory Data Size */
                    936: #define SH7750_MCR_SZ_64      0x00000000       /*    64 bits */
                    937: #define SH7750_MCR_SZ_16      0x00000100       /*    16 bits */
                    938: #define SH7750_MCR_SZ_32      0x00000180       /*    32 bits */
                    939: 
                    940: #define SH7750_MCR_AMX        0x00000078       /* Address Multiplexing */
                    941: #define SH7750_MCR_AMX_S      3
                    942: #define SH7750_MCR_AMX_DRAM_8BIT_COL    0x00000000     /* 8-bit column addr */
                    943: #define SH7750_MCR_AMX_DRAM_9BIT_COL    0x00000008     /* 9-bit column addr */
                    944: #define SH7750_MCR_AMX_DRAM_10BIT_COL   0x00000010     /* 10-bit column addr */
                    945: #define SH7750_MCR_AMX_DRAM_11BIT_COL   0x00000018     /* 11-bit column addr */
                    946: #define SH7750_MCR_AMX_DRAM_12BIT_COL   0x00000020     /* 12-bit column addr */
                    947: /* See SH7750 Hardware Manual for SDRAM address multiplexor selection */
                    948: 
                    949: #define SH7750_MCR_RFSH       0x00000004       /* Refresh Control */
                    950: #define SH7750_MCR_RMODE      0x00000002       /* Refresh Mode: */
                    951: #define SH7750_MCR_RMODE_NORMAL 0x00000000     /* Normal Refresh Mode */
                    952: #define SH7750_MCR_RMODE_SELF   0x00000002     /* Self-Refresh Mode */
                    953: #define SH7750_MCR_RMODE_EDO    0x00000001     /* EDO Mode */
                    954: 
                    955: /* SDRAM Mode Set address */
                    956: #define SH7750_SDRAM_MODE_A2_BASE  0xFF900000
                    957: #define SH7750_SDRAM_MODE_A3_BASE  0xFF940000
                    958: #define SH7750_SDRAM_MODE_A2_32BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 2))
                    959: #define SH7750_SDRAM_MODE_A3_32BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 2))
                    960: #define SH7750_SDRAM_MODE_A2_64BIT(x) (SH7750_SDRAM_MODE_A2_BASE + ((x) << 3))
                    961: #define SH7750_SDRAM_MODE_A3_64BIT(x) (SH7750_SDRAM_MODE_A3_BASE + ((x) << 3))
                    962: 
                    963: 
                    964: /* PCMCIA Control Register (half) - PCR */
                    965: #define SH7750_PCR_REGOFS     0x800018 /* offset */
                    966: #define SH7750_PCR            SH7750_P4_REG32(SH7750_PCR_REGOFS)
                    967: #define SH7750_PCR_A7         SH7750_A7_REG32(SH7750_PCR_REGOFS)
                    968: 
                    969: #define SH7750_PCR_A5PCW      0xC000   /* Area 5 PCMCIA Wait - Number of wait
                    970:                                           states to be added to the number of
                    971:                                           waits specified by WCR2 in a low-speed
                    972:                                           PCMCIA wait cycle */
                    973: #define SH7750_PCR_A5PCW_0    0x0000   /*    0 waits inserted */
                    974: #define SH7750_PCR_A5PCW_15   0x4000   /*    15 waits inserted */
                    975: #define SH7750_PCR_A5PCW_30   0x8000   /*    30 waits inserted */
                    976: #define SH7750_PCR_A5PCW_50   0xC000   /*    50 waits inserted */
                    977: 
                    978: #define SH7750_PCR_A6PCW      0x3000   /* Area 6 PCMCIA Wait - Number of wait
                    979:                                           states to be added to the number of
                    980:                                           waits specified by WCR2 in a low-speed
                    981:                                           PCMCIA wait cycle */
                    982: #define SH7750_PCR_A6PCW_0    0x0000   /*    0 waits inserted */
                    983: #define SH7750_PCR_A6PCW_15   0x1000   /*    15 waits inserted */
                    984: #define SH7750_PCR_A6PCW_30   0x2000   /*    30 waits inserted */
                    985: #define SH7750_PCR_A6PCW_50   0x3000   /*    50 waits inserted */
                    986: 
                    987: #define SH7750_PCR_A5TED      0x0E00   /* Area 5 Address-OE\/WE\ Assertion Delay,
                    988:                                           delay time from address output to
                    989:                                           OE\/WE\ assertion on the connected
                    990:                                           PCMCIA interface */
                    991: #define SH7750_PCR_A5TED_S    9
                    992: #define SH7750_PCR_A6TED      0x01C0   /* Area 6 Address-OE\/WE\ Assertion Delay */
                    993: #define SH7750_PCR_A6TED_S    6
                    994: 
                    995: #define SH7750_PCR_TED_0WS    0        /* 0 Waits inserted */
                    996: #define SH7750_PCR_TED_1WS    1        /* 1 Waits inserted */
                    997: #define SH7750_PCR_TED_2WS    2        /* 2 Waits inserted */
                    998: #define SH7750_PCR_TED_3WS    3        /* 3 Waits inserted */
                    999: #define SH7750_PCR_TED_6WS    4        /* 6 Waits inserted */
                   1000: #define SH7750_PCR_TED_9WS    5        /* 9 Waits inserted */
                   1001: #define SH7750_PCR_TED_12WS   6        /* 12 Waits inserted */
                   1002: #define SH7750_PCR_TED_15WS   7        /* 15 Waits inserted */
                   1003: 
                   1004: #define SH7750_PCR_A5TEH      0x0038   /* Area 5 OE\/WE\ Negation Address delay,
                   1005:                                           address hold delay time from OE\/WE\
                   1006:                                           negation in a write on the connected
                   1007:                                           PCMCIA interface */
                   1008: #define SH7750_PCR_A5TEH_S    3
                   1009: 
                   1010: #define SH7750_PCR_A6TEH      0x0007   /* Area 6 OE\/WE\ Negation Address delay */
                   1011: #define SH7750_PCR_A6TEH_S    0
                   1012: 
                   1013: #define SH7750_PCR_TEH_0WS    0        /* 0 Waits inserted */
                   1014: #define SH7750_PCR_TEH_1WS    1        /* 1 Waits inserted */
                   1015: #define SH7750_PCR_TEH_2WS    2        /* 2 Waits inserted */
                   1016: #define SH7750_PCR_TEH_3WS    3        /* 3 Waits inserted */
                   1017: #define SH7750_PCR_TEH_6WS    4        /* 6 Waits inserted */
                   1018: #define SH7750_PCR_TEH_9WS    5        /* 9 Waits inserted */
                   1019: #define SH7750_PCR_TEH_12WS   6        /* 12 Waits inserted */
                   1020: #define SH7750_PCR_TEH_15WS   7        /* 15 Waits inserted */
                   1021: 
                   1022: /* Refresh Timer Control/Status Register (half) - RTSCR */
                   1023: #define SH7750_RTCSR_REGOFS   0x80001C /* offset */
                   1024: #define SH7750_RTCSR          SH7750_P4_REG32(SH7750_RTCSR_REGOFS)
                   1025: #define SH7750_RTCSR_A7       SH7750_A7_REG32(SH7750_RTCSR_REGOFS)
                   1026: 
                   1027: #define SH7750_RTCSR_KEY      0xA500   /* RTCSR write key */
                   1028: #define SH7750_RTCSR_CMF      0x0080   /* Compare-Match Flag (indicates a
                   1029:                                           match between the refresh timer
                   1030:                                           counter and refresh time constant) */
                   1031: #define SH7750_RTCSR_CMIE     0x0040   /* Compare-Match Interrupt Enable */
                   1032: #define SH7750_RTCSR_CKS      0x0038   /* Refresh Counter Clock Selects */
                   1033: #define SH7750_RTCSR_CKS_DIS          0x0000   /* Clock Input Disabled */
                   1034: #define SH7750_RTCSR_CKS_CKIO_DIV4    0x0008   /* Bus Clock / 4 */
                   1035: #define SH7750_RTCSR_CKS_CKIO_DIV16   0x0010   /* Bus Clock / 16 */
                   1036: #define SH7750_RTCSR_CKS_CKIO_DIV64   0x0018   /* Bus Clock / 64 */
                   1037: #define SH7750_RTCSR_CKS_CKIO_DIV256  0x0020   /* Bus Clock / 256 */
                   1038: #define SH7750_RTCSR_CKS_CKIO_DIV1024 0x0028   /* Bus Clock / 1024 */
                   1039: #define SH7750_RTCSR_CKS_CKIO_DIV2048 0x0030   /* Bus Clock / 2048 */
                   1040: #define SH7750_RTCSR_CKS_CKIO_DIV4096 0x0038   /* Bus Clock / 4096 */
                   1041: 
                   1042: #define SH7750_RTCSR_OVF      0x0004   /* Refresh Count Overflow Flag */
                   1043: #define SH7750_RTCSR_OVIE     0x0002   /* Refresh Count Overflow Interrupt
                   1044:                                           Enable */
                   1045: #define SH7750_RTCSR_LMTS     0x0001   /* Refresh Count Overflow Limit Select */
                   1046: #define SH7750_RTCSR_LMTS_1024 0x0000  /* Count Limit is 1024 */
                   1047: #define SH7750_RTCSR_LMTS_512  0x0001  /* Count Limit is 512 */
                   1048: 
                   1049: /* Refresh Timer Counter (half) - RTCNT */
                   1050: #define SH7750_RTCNT_REGOFS   0x800020 /* offset */
                   1051: #define SH7750_RTCNT          SH7750_P4_REG32(SH7750_RTCNT_REGOFS)
                   1052: #define SH7750_RTCNT_A7       SH7750_A7_REG32(SH7750_RTCNT_REGOFS)
                   1053: 
                   1054: #define SH7750_RTCNT_KEY      0xA500   /* RTCNT write key */
                   1055: 
                   1056: /* Refresh Time Constant Register (half) - RTCOR */
                   1057: #define SH7750_RTCOR_REGOFS   0x800024 /* offset */
                   1058: #define SH7750_RTCOR          SH7750_P4_REG32(SH7750_RTCOR_REGOFS)
                   1059: #define SH7750_RTCOR_A7       SH7750_A7_REG32(SH7750_RTCOR_REGOFS)
                   1060: 
                   1061: #define SH7750_RTCOR_KEY      0xA500   /* RTCOR write key */
                   1062: 
                   1063: /* Refresh Count Register (half) - RFCR */
                   1064: #define SH7750_RFCR_REGOFS    0x800028 /* offset */
                   1065: #define SH7750_RFCR           SH7750_P4_REG32(SH7750_RFCR_REGOFS)
                   1066: #define SH7750_RFCR_A7        SH7750_A7_REG32(SH7750_RFCR_REGOFS)
                   1067: 
                   1068: #define SH7750_RFCR_KEY       0xA400   /* RFCR write key */
                   1069: 
                   1070: /*
                   1071:  * Direct Memory Access Controller (DMAC)
                   1072:  */
                   1073: 
                   1074: /* DMA Source Address Register - SAR0, SAR1, SAR2, SAR3 */
                   1075: #define SH7750_SAR_REGOFS(n)  (0xA00000 + ((n)*16))    /* offset */
                   1076: #define SH7750_SAR(n)         SH7750_P4_REG32(SH7750_SAR_REGOFS(n))
                   1077: #define SH7750_SAR_A7(n)      SH7750_A7_REG32(SH7750_SAR_REGOFS(n))
                   1078: #define SH7750_SAR0           SH7750_SAR(0)
                   1079: #define SH7750_SAR1           SH7750_SAR(1)
                   1080: #define SH7750_SAR2           SH7750_SAR(2)
                   1081: #define SH7750_SAR3           SH7750_SAR(3)
                   1082: #define SH7750_SAR0_A7        SH7750_SAR_A7(0)
                   1083: #define SH7750_SAR1_A7        SH7750_SAR_A7(1)
                   1084: #define SH7750_SAR2_A7        SH7750_SAR_A7(2)
                   1085: #define SH7750_SAR3_A7        SH7750_SAR_A7(3)
                   1086: 
                   1087: /* DMA Destination Address Register - DAR0, DAR1, DAR2, DAR3 */
                   1088: #define SH7750_DAR_REGOFS(n)  (0xA00004 + ((n)*16))    /* offset */
                   1089: #define SH7750_DAR(n)         SH7750_P4_REG32(SH7750_DAR_REGOFS(n))
                   1090: #define SH7750_DAR_A7(n)      SH7750_A7_REG32(SH7750_DAR_REGOFS(n))
                   1091: #define SH7750_DAR0           SH7750_DAR(0)
                   1092: #define SH7750_DAR1           SH7750_DAR(1)
                   1093: #define SH7750_DAR2           SH7750_DAR(2)
                   1094: #define SH7750_DAR3           SH7750_DAR(3)
                   1095: #define SH7750_DAR0_A7        SH7750_DAR_A7(0)
                   1096: #define SH7750_DAR1_A7        SH7750_DAR_A7(1)
                   1097: #define SH7750_DAR2_A7        SH7750_DAR_A7(2)
                   1098: #define SH7750_DAR3_A7        SH7750_DAR_A7(3)
                   1099: 
                   1100: /* DMA Transfer Count Register - DMATCR0, DMATCR1, DMATCR2, DMATCR3 */
                   1101: #define SH7750_DMATCR_REGOFS(n)  (0xA00008 + ((n)*16)) /* offset */
                   1102: #define SH7750_DMATCR(n)      SH7750_P4_REG32(SH7750_DMATCR_REGOFS(n))
                   1103: #define SH7750_DMATCR_A7(n)   SH7750_A7_REG32(SH7750_DMATCR_REGOFS(n))
                   1104: #define SH7750_DMATCR0_P4     SH7750_DMATCR(0)
                   1105: #define SH7750_DMATCR1_P4     SH7750_DMATCR(1)
                   1106: #define SH7750_DMATCR2_P4     SH7750_DMATCR(2)
                   1107: #define SH7750_DMATCR3_P4     SH7750_DMATCR(3)
                   1108: #define SH7750_DMATCR0_A7     SH7750_DMATCR_A7(0)
                   1109: #define SH7750_DMATCR1_A7     SH7750_DMATCR_A7(1)
                   1110: #define SH7750_DMATCR2_A7     SH7750_DMATCR_A7(2)
                   1111: #define SH7750_DMATCR3_A7     SH7750_DMATCR_A7(3)
                   1112: 
                   1113: /* DMA Channel Control Register - CHCR0, CHCR1, CHCR2, CHCR3 */
                   1114: #define SH7750_CHCR_REGOFS(n)  (0xA0000C + ((n)*16))   /* offset */
                   1115: #define SH7750_CHCR(n)        SH7750_P4_REG32(SH7750_CHCR_REGOFS(n))
                   1116: #define SH7750_CHCR_A7(n)     SH7750_A7_REG32(SH7750_CHCR_REGOFS(n))
                   1117: #define SH7750_CHCR0          SH7750_CHCR(0)
                   1118: #define SH7750_CHCR1          SH7750_CHCR(1)
                   1119: #define SH7750_CHCR2          SH7750_CHCR(2)
                   1120: #define SH7750_CHCR3          SH7750_CHCR(3)
                   1121: #define SH7750_CHCR0_A7       SH7750_CHCR_A7(0)
                   1122: #define SH7750_CHCR1_A7       SH7750_CHCR_A7(1)
                   1123: #define SH7750_CHCR2_A7       SH7750_CHCR_A7(2)
                   1124: #define SH7750_CHCR3_A7       SH7750_CHCR_A7(3)
                   1125: 
                   1126: #define SH7750_CHCR_SSA       0xE0000000       /* Source Address Space Attribute */
                   1127: #define SH7750_CHCR_SSA_PCMCIA  0x00000000     /* Reserved in PCMCIA access */
                   1128: #define SH7750_CHCR_SSA_DYNBSZ  0x20000000     /* Dynamic Bus Sizing I/O space */
                   1129: #define SH7750_CHCR_SSA_IO8     0x40000000     /* 8-bit I/O space */
                   1130: #define SH7750_CHCR_SSA_IO16    0x60000000     /* 16-bit I/O space */
                   1131: #define SH7750_CHCR_SSA_CMEM8   0x80000000     /* 8-bit common memory space */
                   1132: #define SH7750_CHCR_SSA_CMEM16  0xA0000000     /* 16-bit common memory space */
                   1133: #define SH7750_CHCR_SSA_AMEM8   0xC0000000     /* 8-bit attribute memory space */
                   1134: #define SH7750_CHCR_SSA_AMEM16  0xE0000000     /* 16-bit attribute memory space */
                   1135: 
                   1136: #define SH7750_CHCR_STC       0x10000000       /* Source Address Wait Control Select,
                   1137:                                                   specifies CS5 or CS6 space wait
                   1138:                                                   control for PCMCIA access */
                   1139: 
                   1140: #define SH7750_CHCR_DSA       0x0E000000       /* Source Address Space Attribute */
                   1141: #define SH7750_CHCR_DSA_PCMCIA  0x00000000     /* Reserved in PCMCIA access */
                   1142: #define SH7750_CHCR_DSA_DYNBSZ  0x02000000     /* Dynamic Bus Sizing I/O space */
                   1143: #define SH7750_CHCR_DSA_IO8     0x04000000     /* 8-bit I/O space */
                   1144: #define SH7750_CHCR_DSA_IO16    0x06000000     /* 16-bit I/O space */
                   1145: #define SH7750_CHCR_DSA_CMEM8   0x08000000     /* 8-bit common memory space */
                   1146: #define SH7750_CHCR_DSA_CMEM16  0x0A000000     /* 16-bit common memory space */
                   1147: #define SH7750_CHCR_DSA_AMEM8   0x0C000000     /* 8-bit attribute memory space */
                   1148: #define SH7750_CHCR_DSA_AMEM16  0x0E000000     /* 16-bit attribute memory space */
                   1149: 
                   1150: #define SH7750_CHCR_DTC       0x01000000       /* Destination Address Wait Control
                   1151:                                                   Select, specifies CS5 or CS6 
                   1152:                                                   space wait control for PCMCIA
                   1153:                                                   access */
                   1154: 
                   1155: #define SH7750_CHCR_DS        0x00080000       /* DREQ\ Select : */
                   1156: #define SH7750_CHCR_DS_LOWLVL 0x00000000       /*     Low Level Detection */
                   1157: #define SH7750_CHCR_DS_FALL   0x00080000       /*     Falling Edge Detection */
                   1158: 
                   1159: #define SH7750_CHCR_RL        0x00040000       /* Request Check Level: */
                   1160: #define SH7750_CHCR_RL_ACTH   0x00000000       /*     DRAK is an active high out */
                   1161: #define SH7750_CHCR_RL_ACTL   0x00040000       /*     DRAK is an active low out */
                   1162: 
                   1163: #define SH7750_CHCR_AM        0x00020000       /* Acknowledge Mode: */
                   1164: #define SH7750_CHCR_AM_RD     0x00000000       /*     DACK is output in read cycle */
                   1165: #define SH7750_CHCR_AM_WR     0x00020000       /*     DACK is output in write cycle */
                   1166: 
                   1167: #define SH7750_CHCR_AL        0x00010000       /* Acknowledge Level: */
                   1168: #define SH7750_CHCR_AL_ACTH   0x00000000       /*     DACK is an active high out */
                   1169: #define SH7750_CHCR_AL_ACTL   0x00010000       /*     DACK is an active low out */
                   1170: 
                   1171: #define SH7750_CHCR_DM        0x0000C000       /* Destination Address Mode: */
                   1172: #define SH7750_CHCR_DM_FIX    0x00000000       /*     Destination Addr Fixed */
                   1173: #define SH7750_CHCR_DM_INC    0x00004000       /*     Destination Addr Incremented */
                   1174: #define SH7750_CHCR_DM_DEC    0x00008000       /*     Destination Addr Decremented */
                   1175: 
                   1176: #define SH7750_CHCR_SM        0x00003000       /* Source Address Mode: */
                   1177: #define SH7750_CHCR_SM_FIX    0x00000000       /*     Source Addr Fixed */
                   1178: #define SH7750_CHCR_SM_INC    0x00001000       /*     Source Addr Incremented */
                   1179: #define SH7750_CHCR_SM_DEC    0x00002000       /*     Source Addr Decremented */
                   1180: 
                   1181: #define SH7750_CHCR_RS        0x00000F00       /* Request Source Select: */
                   1182: #define SH7750_CHCR_RS_ER_DA_EA_TO_EA   0x000  /* External Request, Dual Address
                   1183:                                                   Mode (External Addr Space->
                   1184:                                                   External Addr Space) */
                   1185: #define SH7750_CHCR_RS_ER_SA_EA_TO_ED   0x200  /* External Request, Single
                   1186:                                                   Address Mode (External Addr
                   1187:                                                   Space -> External Device) */
                   1188: #define SH7750_CHCR_RS_ER_SA_ED_TO_EA   0x300  /* External Request, Single
                   1189:                                                   Address Mode, (External 
                   1190:                                                   Device -> External Addr 
                   1191:                                                   Space) */
                   1192: #define SH7750_CHCR_RS_AR_EA_TO_EA      0x400  /* Auto-Request (External Addr
                   1193:                                                   Space -> External Addr Space) */
                   1194: 
                   1195: #define SH7750_CHCR_RS_AR_EA_TO_OCP     0x500  /* Auto-Request (External Addr
                   1196:                                                   Space -> On-chip Peripheral
                   1197:                                                   Module) */
                   1198: #define SH7750_CHCR_RS_AR_OCP_TO_EA     0x600  /* Auto-Request (On-chip 
                   1199:                                                   Peripheral Module ->
                   1200:                                                   External Addr Space */
                   1201: #define SH7750_CHCR_RS_SCITX_EA_TO_SC   0x800  /* SCI Transmit-Data-Empty intr
                   1202:                                                   transfer request (external
                   1203:                                                   address space -> SCTDR1) */
                   1204: #define SH7750_CHCR_RS_SCIRX_SC_TO_EA   0x900  /* SCI Receive-Data-Full intr
                   1205:                                                   transfer request (SCRDR1 ->
                   1206:                                                   External Addr Space) */
                   1207: #define SH7750_CHCR_RS_SCIFTX_EA_TO_SC  0xA00  /* SCIF Transmit-Data-Empty intr
                   1208:                                                   transfer request (external
                   1209:                                                   address space -> SCFTDR1) */
                   1210: #define SH7750_CHCR_RS_SCIFRX_SC_TO_EA  0xB00  /* SCIF Receive-Data-Full intr
                   1211:                                                   transfer request (SCFRDR2 ->
                   1212:                                                   External Addr Space) */
                   1213: #define SH7750_CHCR_RS_TMU2_EA_TO_EA    0xC00  /* TMU Channel 2 (input capture
                   1214:                                                   interrupt), (external address
                   1215:                                                   space -> external address
                   1216:                                                   space) */
                   1217: #define SH7750_CHCR_RS_TMU2_EA_TO_OCP   0xD00  /* TMU Channel 2 (input capture
                   1218:                                                   interrupt), (external address
                   1219:                                                   space -> on-chip peripheral
                   1220:                                                   module) */
                   1221: #define SH7750_CHCR_RS_TMU2_OCP_TO_EA   0xE00  /* TMU Channel 2 (input capture
                   1222:                                                   interrupt), (on-chip
                   1223:                                                   peripheral module -> external
                   1224:                                                   address space) */
                   1225: 
                   1226: #define SH7750_CHCR_TM        0x00000080       /* Transmit mode: */
                   1227: #define SH7750_CHCR_TM_CSTEAL 0x00000000       /*     Cycle Steal Mode */
                   1228: #define SH7750_CHCR_TM_BURST  0x00000080       /*     Burst Mode */
                   1229: 
                   1230: #define SH7750_CHCR_TS        0x00000070       /* Transmit Size: */
                   1231: #define SH7750_CHCR_TS_QUAD   0x00000000       /*     Quadword Size (64 bits) */
                   1232: #define SH7750_CHCR_TS_BYTE   0x00000010       /*     Byte Size (8 bit) */
                   1233: #define SH7750_CHCR_TS_WORD   0x00000020       /*     Word Size (16 bit) */
                   1234: #define SH7750_CHCR_TS_LONG   0x00000030       /*     Longword Size (32 bit) */
                   1235: #define SH7750_CHCR_TS_BLOCK  0x00000040       /*     32-byte block transfer */
                   1236: 
                   1237: #define SH7750_CHCR_IE        0x00000004       /* Interrupt Enable */
                   1238: #define SH7750_CHCR_TE        0x00000002       /* Transfer End */
                   1239: #define SH7750_CHCR_DE        0x00000001       /* DMAC Enable */
                   1240: 
                   1241: /* DMA Operation Register - DMAOR */
                   1242: #define SH7750_DMAOR_REGOFS   0xA00040 /* offset */
                   1243: #define SH7750_DMAOR          SH7750_P4_REG32(SH7750_DMAOR_REGOFS)
                   1244: #define SH7750_DMAOR_A7       SH7750_A7_REG32(SH7750_DMAOR_REGOFS)
                   1245: 
                   1246: #define SH7750_DMAOR_DDT      0x00008000       /* On-Demand Data Transfer Mode */
                   1247: 
                   1248: #define SH7750_DMAOR_PR       0x00000300       /* Priority Mode: */
                   1249: #define SH7750_DMAOR_PR_0123  0x00000000       /*     CH0 > CH1 > CH2 > CH3 */
                   1250: #define SH7750_DMAOR_PR_0231  0x00000100       /*     CH0 > CH2 > CH3 > CH1 */
                   1251: #define SH7750_DMAOR_PR_2013  0x00000200       /*     CH2 > CH0 > CH1 > CH3 */
                   1252: #define SH7750_DMAOR_PR_RR    0x00000300       /*     Round-robin mode */
                   1253: 
                   1254: #define SH7750_DMAOR_COD      0x00000010       /* Check Overrun for DREQ\ */
                   1255: #define SH7750_DMAOR_AE       0x00000004       /* Address Error flag */
                   1256: #define SH7750_DMAOR_NMIF     0x00000002       /* NMI Flag */
                   1257: #define SH7750_DMAOR_DME      0x00000001       /* DMAC Master Enable */
                   1258: 
                   1259: /*
                   1260:  * Serial Communication Interface - SCI
                   1261:  * Serial Communication Interface with FIFO - SCIF
                   1262:  */
                   1263: /* SCI Receive Data Register (byte, read-only) - SCRDR1, SCFRDR2 */
                   1264: #define SH7750_SCRDR_REGOFS(n) ((n) == 1 ? 0xE00014 : 0xE80014)        /* offset */
                   1265: #define SH7750_SCRDR(n)       SH7750_P4_REG32(SH7750_SCRDR_REGOFS(n))
                   1266: #define SH7750_SCRDR1         SH7750_SCRDR(1)
                   1267: #define SH7750_SCRDR2         SH7750_SCRDR(2)
                   1268: #define SH7750_SCRDR_A7(n)    SH7750_A7_REG32(SH7750_SCRDR_REGOFS(n))
                   1269: #define SH7750_SCRDR1_A7      SH7750_SCRDR_A7(1)
                   1270: #define SH7750_SCRDR2_A7      SH7750_SCRDR_A7(2)
                   1271: 
                   1272: /* SCI Transmit Data Register (byte) - SCTDR1, SCFTDR2 */
                   1273: #define SH7750_SCTDR_REGOFS(n) ((n) == 1 ? 0xE0000C : 0xE8000C)        /* offset */
                   1274: #define SH7750_SCTDR(n)       SH7750_P4_REG32(SH7750_SCTDR_REGOFS(n))
                   1275: #define SH7750_SCTDR1         SH7750_SCTDR(1)
                   1276: #define SH7750_SCTDR2         SH7750_SCTDR(2)
                   1277: #define SH7750_SCTDR_A7(n)    SH7750_A7_REG32(SH7750_SCTDR_REGOFS(n))
                   1278: #define SH7750_SCTDR1_A7      SH7750_SCTDR_A7(1)
                   1279: #define SH7750_SCTDR2_A7      SH7750_SCTDR_A7(2)
                   1280: 
                   1281: /* SCI Serial Mode Register - SCSMR1(byte), SCSMR2(half) */
                   1282: #define SH7750_SCSMR_REGOFS(n) ((n) == 1 ? 0xE00000 : 0xE80000)        /* offset */
                   1283: #define SH7750_SCSMR(n)       SH7750_P4_REG32(SH7750_SCSMR_REGOFS(n))
                   1284: #define SH7750_SCSMR1         SH7750_SCSMR(1)
                   1285: #define SH7750_SCSMR2         SH7750_SCSMR(2)
                   1286: #define SH7750_SCSMR_A7(n)    SH7750_A7_REG32(SH7750_SCSMR_REGOFS(n))
                   1287: #define SH7750_SCSMR1_A7      SH7750_SCSMR_A7(1)
                   1288: #define SH7750_SCSMR2_A7      SH7750_SCSMR_A7(2)
                   1289: 
                   1290: #define SH7750_SCSMR1_CA       0x80    /* Communication Mode (C/A\): */
                   1291: #define SH7750_SCSMR1_CA_ASYNC 0x00    /*     Asynchronous Mode */
                   1292: #define SH7750_SCSMR1_CA_SYNC  0x80    /*     Synchronous Mode */
                   1293: #define SH7750_SCSMR_CHR       0x40    /* Character Length: */
                   1294: #define SH7750_SCSMR_CHR_8     0x00    /*     8-bit data */
                   1295: #define SH7750_SCSMR_CHR_7     0x40    /*     7-bit data */
                   1296: #define SH7750_SCSMR_PE        0x20    /* Parity Enable */
                   1297: #define SH7750_SCSMR_PM        0x10    /* Parity Mode: */
                   1298: #define SH7750_SCSMR_PM_EVEN   0x00    /*     Even Parity */
                   1299: #define SH7750_SCSMR_PM_ODD    0x10    /*     Odd Parity */
                   1300: #define SH7750_SCSMR_STOP      0x08    /* Stop Bit Length: */
                   1301: #define SH7750_SCSMR_STOP_1    0x00    /*     1 stop bit */
                   1302: #define SH7750_SCSMR_STOP_2    0x08    /*     2 stop bit */
                   1303: #define SH7750_SCSMR1_MP       0x04    /* Multiprocessor Mode */
                   1304: #define SH7750_SCSMR_CKS       0x03    /* Clock Select */
                   1305: #define SH7750_SCSMR_CKS_S     0
                   1306: #define SH7750_SCSMR_CKS_DIV1  0x00    /*     Periph clock */
                   1307: #define SH7750_SCSMR_CKS_DIV4  0x01    /*     Periph clock / 4 */
                   1308: #define SH7750_SCSMR_CKS_DIV16 0x02    /*     Periph clock / 16 */
                   1309: #define SH7750_SCSMR_CKS_DIV64 0x03    /*     Periph clock / 64 */
                   1310: 
                   1311: /* SCI Serial Control Register - SCSCR1(byte), SCSCR2(half) */
                   1312: #define SH7750_SCSCR_REGOFS(n) ((n) == 1 ? 0xE00008 : 0xE80008)        /* offset */
                   1313: #define SH7750_SCSCR(n)       SH7750_P4_REG32(SH7750_SCSCR_REGOFS(n))
                   1314: #define SH7750_SCSCR1         SH7750_SCSCR(1)
                   1315: #define SH7750_SCSCR2         SH7750_SCSCR(2)
                   1316: #define SH7750_SCSCR_A7(n)    SH7750_A7_REG32(SH7750_SCSCR_REGOFS(n))
                   1317: #define SH7750_SCSCR1_A7      SH7750_SCSCR_A7(1)
                   1318: #define SH7750_SCSCR2_A7      SH7750_SCSCR_A7(2)
                   1319: 
                   1320: #define SH7750_SCSCR_TIE      0x80     /* Transmit Interrupt Enable */
                   1321: #define SH7750_SCSCR_RIE      0x40     /* Receive Interrupt Enable */
                   1322: #define SH7750_SCSCR_TE       0x20     /* Transmit Enable */
                   1323: #define SH7750_SCSCR_RE       0x10     /* Receive Enable */
                   1324: #define SH7750_SCSCR1_MPIE    0x08     /* Multiprocessor Interrupt Enable */
                   1325: #define SH7750_SCSCR2_REIE    0x08     /* Receive Error Interrupt Enable */
                   1326: #define SH7750_SCSCR1_TEIE    0x04     /* Transmit End Interrupt Enable */
                   1327: #define SH7750_SCSCR1_CKE     0x03     /* Clock Enable: */
                   1328: #define SH7750_SCSCR_CKE_INTCLK            0x00        /* Use Internal Clock */
                   1329: #define SH7750_SCSCR_CKE_EXTCLK            0x02        /* Use External Clock from SCK */
                   1330: #define SH7750_SCSCR1_CKE_ASYNC_SCK_CLKOUT 0x01        /* Use SCK as a clock output
                   1331:                                                   in asynchronous mode */
                   1332: 
                   1333: /* SCI Serial Status Register - SCSSR1(byte), SCSFR2(half) */
                   1334: #define SH7750_SCSSR_REGOFS(n) ((n) == 1 ? 0xE00010 : 0xE80010)        /* offset */
                   1335: #define SH7750_SCSSR(n)       SH7750_P4_REG32(SH7750_SCSSR_REGOFS(n))
                   1336: #define SH7750_SCSSR1         SH7750_SCSSR(1)
                   1337: #define SH7750_SCSFR2         SH7750_SCSSR(2)
                   1338: #define SH7750_SCSSR_A7(n)    SH7750_A7_REG32(SH7750_SCSSR_REGOFS(n))
                   1339: #define SH7750_SCSSR1_A7      SH7750_SCSSR_A7(1)
                   1340: #define SH7750_SCSFR2_A7      SH7750_SCSSR_A7(2)
                   1341: 
                   1342: #define SH7750_SCSSR1_TDRE    0x80     /* Transmit Data Register Empty */
                   1343: #define SH7750_SCSSR1_RDRF    0x40     /* Receive Data Register Full */
                   1344: #define SH7750_SCSSR1_ORER    0x20     /* Overrun Error */
                   1345: #define SH7750_SCSSR1_FER     0x10     /* Framing Error */
                   1346: #define SH7750_SCSSR1_PER     0x08     /* Parity Error */
                   1347: #define SH7750_SCSSR1_TEND    0x04     /* Transmit End */
                   1348: #define SH7750_SCSSR1_MPB     0x02     /* Multiprocessor Bit */
                   1349: #define SH7750_SCSSR1_MPBT    0x01     /* Multiprocessor Bit Transfer */
                   1350: 
                   1351: #define SH7750_SCFSR2_PERN    0xF000   /* Number of Parity Errors */
                   1352: #define SH7750_SCFSR2_PERN_S  12
                   1353: #define SH7750_SCFSR2_FERN    0x0F00   /* Number of Framing Errors */
                   1354: #define SH7750_SCFSR2_FERN_S  8
                   1355: #define SH7750_SCFSR2_ER      0x0080   /* Receive Error */
                   1356: #define SH7750_SCFSR2_TEND    0x0040   /* Transmit End */
                   1357: #define SH7750_SCFSR2_TDFE    0x0020   /* Transmit FIFO Data Empty */
                   1358: #define SH7750_SCFSR2_BRK     0x0010   /* Break Detect */
                   1359: #define SH7750_SCFSR2_FER     0x0008   /* Framing Error */
                   1360: #define SH7750_SCFSR2_PER     0x0004   /* Parity Error */
                   1361: #define SH7750_SCFSR2_RDF     0x0002   /* Receive FIFO Data Full */
                   1362: #define SH7750_SCFSR2_DR      0x0001   /* Receive Data Ready */
                   1363: 
                   1364: /* SCI Serial Port Register - SCSPTR1(byte) */
                   1365: #define SH7750_SCSPTR1_REGOFS 0xE0001C /* offset */
                   1366: #define SH7750_SCSPTR1        SH7750_P4_REG32(SH7750_SCSPTR1_REGOFS)
                   1367: #define SH7750_SCSPTR1_A7     SH7750_A7_REG32(SH7750_SCSPTR1_REGOFS)
                   1368: 
                   1369: #define SH7750_SCSPTR1_EIO    0x80     /* Error Interrupt Only */
                   1370: #define SH7750_SCSPTR1_SPB1IO 0x08     /* 1: Output SPB1DT bit to SCK pin */
                   1371: #define SH7750_SCSPTR1_SPB1DT 0x04     /* Serial Port Clock Port Data */
                   1372: #define SH7750_SCSPTR1_SPB0IO 0x02     /* 1: Output SPB0DT bit to TxD pin */
                   1373: #define SH7750_SCSPTR1_SPB0DT 0x01     /* Serial Port Break Data */
                   1374: 
                   1375: /* SCIF Serial Port Register - SCSPTR2(half) */
                   1376: #define SH7750_SCSPTR2_REGOFS 0xE80020 /* offset */
                   1377: #define SH7750_SCSPTR2        SH7750_P4_REG32(SH7750_SCSPTR2_REGOFS)
                   1378: #define SH7750_SCSPTR2_A7     SH7750_A7_REG32(SH7750_SCSPTR2_REGOFS)
                   1379: 
                   1380: #define SH7750_SCSPTR2_RTSIO  0x80     /* 1: Output RTSDT bit to RTS2\ pin */
                   1381: #define SH7750_SCSPTR2_RTSDT  0x40     /* RTS Port Data */
                   1382: #define SH7750_SCSPTR2_CTSIO  0x20     /* 1: Output CTSDT bit to CTS2\ pin */
                   1383: #define SH7750_SCSPTR2_CTSDT  0x10     /* CTS Port Data */
                   1384: #define SH7750_SCSPTR2_SPB2IO 0x02     /* 1: Output SPBDT bit to TxD2 pin */
                   1385: #define SH7750_SCSPTR2_SPB2DT 0x01     /* Serial Port Break Data */
                   1386: 
                   1387: /* SCI Bit Rate Register - SCBRR1(byte), SCBRR2(byte) */
                   1388: #define SH7750_SCBRR_REGOFS(n) ((n) == 1 ? 0xE00004 : 0xE80004)        /* offset */
                   1389: #define SH7750_SCBRR(n)       SH7750_P4_REG32(SH7750_SCBRR_REGOFS(n))
                   1390: #define SH7750_SCBRR1         SH7750_SCBRR_P4(1)
                   1391: #define SH7750_SCBRR2         SH7750_SCBRR_P4(2)
                   1392: #define SH7750_SCBRR_A7(n)    SH7750_A7_REG32(SH7750_SCBRR_REGOFS(n))
                   1393: #define SH7750_SCBRR1_A7      SH7750_SCBRR_A7(1)
                   1394: #define SH7750_SCBRR2_A7      SH7750_SCBRR_A7(2)
                   1395: 
                   1396: /* SCIF FIFO Control Register - SCFCR2(half) */
                   1397: #define SH7750_SCFCR2_REGOFS  0xE80018 /* offset */
                   1398: #define SH7750_SCFCR2         SH7750_P4_REG32(SH7750_SCFCR2_REGOFS)
                   1399: #define SH7750_SCFCR2_A7      SH7750_A7_REG32(SH7750_SCFCR2_REGOFS)
                   1400: 
                   1401: #define SH7750_SCFCR2_RSTRG   0x700    /* RTS2\ Output Active Trigger; RTS2\
                   1402:                                           signal goes to high level when the
                   1403:                                           number of received data stored in
                   1404:                                           FIFO exceeds the trigger number */
                   1405: #define SH7750_SCFCR2_RSTRG_15 0x000   /* 15 bytes */
                   1406: #define SH7750_SCFCR2_RSTRG_1  0x000   /* 1 byte */
                   1407: #define SH7750_SCFCR2_RSTRG_4  0x000   /* 4 bytes */
                   1408: #define SH7750_SCFCR2_RSTRG_6  0x000   /* 6 bytes */
                   1409: #define SH7750_SCFCR2_RSTRG_8  0x000   /* 8 bytes */
                   1410: #define SH7750_SCFCR2_RSTRG_10 0x000   /* 10 bytes */
                   1411: #define SH7750_SCFCR2_RSTRG_14 0x000   /* 14 bytes */
                   1412: 
                   1413: #define SH7750_SCFCR2_RTRG    0x0C0    /* Receive FIFO Data Number Trigger,
                   1414:                                           Receive Data Full (RDF) Flag sets
                   1415:                                           when number of receive data bytes is
                   1416:                                           equal or greater than the trigger
                   1417:                                           number */
                   1418: #define SH7750_SCFCR2_RTRG_1  0x000    /* 1 byte */
                   1419: #define SH7750_SCFCR2_RTRG_4  0x040    /* 4 bytes */
                   1420: #define SH7750_SCFCR2_RTRG_8  0x080    /* 8 bytes */
                   1421: #define SH7750_SCFCR2_RTRG_14 0x0C0    /* 14 bytes */
                   1422: 
                   1423: #define SH7750_SCFCR2_TTRG    0x030    /* Transmit FIFO Data Number Trigger,
                   1424:                                           Transmit FIFO Data Register Empty (TDFE)
                   1425:                                           flag sets when the number of remaining
                   1426:                                           transmit data bytes is equal or less
                   1427:                                           than the trigger number */
                   1428: #define SH7750_SCFCR2_TTRG_8  0x000    /* 8 bytes */
                   1429: #define SH7750_SCFCR2_TTRG_4  0x010    /* 4 bytes */
                   1430: #define SH7750_SCFCR2_TTRG_2  0x020    /* 2 bytes */
                   1431: #define SH7750_SCFCR2_TTRG_1  0x030    /* 1 byte */
                   1432: 
                   1433: #define SH7750_SCFCR2_MCE     0x008    /* Modem Control Enable */
                   1434: #define SH7750_SCFCR2_TFRST   0x004    /* Transmit FIFO Data Register Reset,
                   1435:                                           invalidates the transmit data in the
                   1436:                                           transmit FIFO */
                   1437: #define SH7750_SCFCR2_RFRST   0x002    /* Receive FIFO Data Register Reset,
                   1438:                                           invalidates the receive data in the
                   1439:                                           receive FIFO data register and resets
                   1440:                                           it to the empty state */
                   1441: #define SH7750_SCFCR2_LOOP    0x001    /* Loopback Test */
                   1442: 
                   1443: /* SCIF FIFO Data Count Register - SCFDR2(half, read-only) */
                   1444: #define SH7750_SCFDR2_REGOFS  0xE8001C /* offset */
                   1445: #define SH7750_SCFDR2         SH7750_P4_REG32(SH7750_SCFDR2_REGOFS)
                   1446: #define SH7750_SCFDR2_A7      SH7750_A7_REG32(SH7750_SCFDR2_REGOFS)
                   1447: 
                   1448: #define SH7750_SCFDR2_T       0x1F00   /* Number of untransmitted data bytes
                   1449:                                           in transmit FIFO */
                   1450: #define SH7750_SCFDR2_T_S     8
                   1451: #define SH7750_SCFDR2_R       0x001F   /* Number of received data bytes in
                   1452:                                           receive FIFO */
                   1453: #define SH7750_SCFDR2_R_S     0
                   1454: 
                   1455: /* SCIF Line Status Register - SCLSR2(half, read-only) */
                   1456: #define SH7750_SCLSR2_REGOFS  0xE80024 /* offset */
                   1457: #define SH7750_SCLSR2         SH7750_P4_REG32(SH7750_SCLSR2_REGOFS)
                   1458: #define SH7750_SCLSR2_A7      SH7750_A7_REG32(SH7750_SCLSR2_REGOFS)
                   1459: 
                   1460: #define SH7750_SCLSR2_ORER    0x0001   /* Overrun Error */
                   1461: 
                   1462: /*
                   1463:  * SCI-based Smart Card Interface
                   1464:  */
                   1465: /* Smart Card Mode Register - SCSCMR1(byte) */
                   1466: #define SH7750_SCSCMR1_REGOFS 0xE00018 /* offset */
                   1467: #define SH7750_SCSCMR1        SH7750_P4_REG32(SH7750_SCSCMR1_REGOFS)
                   1468: #define SH7750_SCSCMR1_A7     SH7750_A7_REG32(SH7750_SCSCMR1_REGOFS)
                   1469: 
                   1470: #define SH7750_SCSCMR1_SDIR   0x08     /* Smart Card Data Transfer Direction: */
                   1471: #define SH7750_SCSCMR1_SDIR_LSBF 0x00  /* LSB-first */
                   1472: #define SH7750_SCSCMR1_SDIR_MSBF 0x08  /* MSB-first */
                   1473: 
                   1474: #define SH7750_SCSCMR1_SINV   0x04     /* Smart Card Data Inversion */
                   1475: #define SH7750_SCSCMR1_SMIF   0x01     /* Smart Card Interface Mode Select */
                   1476: 
                   1477: /* Smart-card specific bits in other registers */
                   1478: /* SCSMR1: */
                   1479: #define SH7750_SCSMR1_GSM     0x80     /* GSM mode select */
                   1480: 
                   1481: /* SCSSR1: */
                   1482: #define SH7750_SCSSR1_ERS     0x10     /* Error Signal Status */
                   1483: 
                   1484: /*
                   1485:  * I/O Ports
                   1486:  */
                   1487: /* Port Control Register A - PCTRA */
                   1488: #define SH7750_PCTRA_REGOFS   0x80002C /* offset */
                   1489: #define SH7750_PCTRA          SH7750_P4_REG32(SH7750_PCTRA_REGOFS)
                   1490: #define SH7750_PCTRA_A7       SH7750_A7_REG32(SH7750_PCTRA_REGOFS)
                   1491: 
                   1492: #define SH7750_PCTRA_PBPUP(n) 0        /* Bit n is pulled up */
                   1493: #define SH7750_PCTRA_PBNPUP(n) (1 << ((n)*2+1))        /* Bit n is not pulled up */
                   1494: #define SH7750_PCTRA_PBINP(n) 0        /* Bit n is an input */
                   1495: #define SH7750_PCTRA_PBOUT(n) (1 << ((n)*2))   /* Bit n is an output */
                   1496: 
                   1497: /* Port Data Register A - PDTRA(half) */
                   1498: #define SH7750_PDTRA_REGOFS   0x800030 /* offset */
                   1499: #define SH7750_PDTRA          SH7750_P4_REG32(SH7750_PDTRA_REGOFS)
                   1500: #define SH7750_PDTRA_A7       SH7750_A7_REG32(SH7750_PDTRA_REGOFS)
                   1501: 
                   1502: #define SH7750_PDTRA_BIT(n) (1 << (n))
                   1503: 
                   1504: /* Port Control Register B - PCTRB */
                   1505: #define SH7750_PCTRB_REGOFS   0x800040 /* offset */
                   1506: #define SH7750_PCTRB          SH7750_P4_REG32(SH7750_PCTRB_REGOFS)
                   1507: #define SH7750_PCTRB_A7       SH7750_A7_REG32(SH7750_PCTRB_REGOFS)
                   1508: 
                   1509: #define SH7750_PCTRB_PBPUP(n) 0        /* Bit n is pulled up */
                   1510: #define SH7750_PCTRB_PBNPUP(n) (1 << ((n-16)*2+1))     /* Bit n is not pulled up */
                   1511: #define SH7750_PCTRB_PBINP(n) 0        /* Bit n is an input */
                   1512: #define SH7750_PCTRB_PBOUT(n) (1 << ((n-16)*2))        /* Bit n is an output */
                   1513: 
                   1514: /* Port Data Register B - PDTRB(half) */
                   1515: #define SH7750_PDTRB_REGOFS   0x800044 /* offset */
                   1516: #define SH7750_PDTRB          SH7750_P4_REG32(SH7750_PDTRB_REGOFS)
                   1517: #define SH7750_PDTRB_A7       SH7750_A7_REG32(SH7750_PDTRB_REGOFS)
                   1518: 
                   1519: #define SH7750_PDTRB_BIT(n) (1 << ((n)-16))
                   1520: 
                   1521: /* GPIO Interrupt Control Register - GPIOIC(half) */
                   1522: #define SH7750_GPIOIC_REGOFS  0x800048 /* offset */
                   1523: #define SH7750_GPIOIC         SH7750_P4_REG32(SH7750_GPIOIC_REGOFS)
                   1524: #define SH7750_GPIOIC_A7      SH7750_A7_REG32(SH7750_GPIOIC_REGOFS)
                   1525: 
                   1526: #define SH7750_GPIOIC_PTIREN(n) (1 << (n))     /* Port n is used as a GPIO int */
                   1527: 
                   1528: /*
                   1529:  * Interrupt Controller - INTC
                   1530:  */
                   1531: /* Interrupt Control Register - ICR (half) */
                   1532: #define SH7750_ICR_REGOFS     0xD00000 /* offset */
                   1533: #define SH7750_ICR            SH7750_P4_REG32(SH7750_ICR_REGOFS)
                   1534: #define SH7750_ICR_A7         SH7750_A7_REG32(SH7750_ICR_REGOFS)
                   1535: 
                   1536: #define SH7750_ICR_NMIL       0x8000   /* NMI Input Level */
                   1537: #define SH7750_ICR_MAI        0x4000   /* NMI Interrupt Mask */
                   1538: 
                   1539: #define SH7750_ICR_NMIB       0x0200   /* NMI Block Mode: */
                   1540: #define SH7750_ICR_NMIB_BLK   0x0000   /*   NMI requests held pending while
                   1541:                                           SR.BL bit is set to 1 */
                   1542: #define SH7750_ICR_NMIB_NBLK  0x0200   /*   NMI requests detected when SR.BL bit
                   1543:                                           set to 1 */
                   1544: 
                   1545: #define SH7750_ICR_NMIE       0x0100   /* NMI Edge Select: */
                   1546: #define SH7750_ICR_NMIE_FALL  0x0000   /*   Interrupt request detected on falling
                   1547:                                           edge of NMI input */
                   1548: #define SH7750_ICR_NMIE_RISE  0x0100   /*   Interrupt request detected on rising
                   1549:                                           edge of NMI input */
                   1550: 
                   1551: #define SH7750_ICR_IRLM       0x0080   /* IRL Pin Mode: */
                   1552: #define SH7750_ICR_IRLM_ENC   0x0000   /*   IRL\ pins used as a level-encoded
                   1553:                                           interrupt requests */
                   1554: #define SH7750_ICR_IRLM_RAW   0x0080   /*   IRL\ pins used as a four independent
                   1555:                                           interrupt requests */
                   1556: 
                   1557: /* Interrupt Priority Register A - IPRA (half) */
                   1558: #define SH7750_IPRA_REGOFS    0xD00004 /* offset */
                   1559: #define SH7750_IPRA           SH7750_P4_REG32(SH7750_IPRA_REGOFS)
                   1560: #define SH7750_IPRA_A7        SH7750_A7_REG32(SH7750_IPRA_REGOFS)
                   1561: 
                   1562: #define SH7750_IPRA_TMU0      0xF000   /* TMU0 interrupt priority */
                   1563: #define SH7750_IPRA_TMU0_S    12
                   1564: #define SH7750_IPRA_TMU1      0x0F00   /* TMU1 interrupt priority */
                   1565: #define SH7750_IPRA_TMU1_S    8
                   1566: #define SH7750_IPRA_TMU2      0x00F0   /* TMU2 interrupt priority */
                   1567: #define SH7750_IPRA_TMU2_S    4
                   1568: #define SH7750_IPRA_RTC       0x000F   /* RTC interrupt priority */
                   1569: #define SH7750_IPRA_RTC_S     0
                   1570: 
                   1571: /* Interrupt Priority Register B - IPRB (half) */
                   1572: #define SH7750_IPRB_REGOFS    0xD00008 /* offset */
                   1573: #define SH7750_IPRB           SH7750_P4_REG32(SH7750_IPRB_REGOFS)
                   1574: #define SH7750_IPRB_A7        SH7750_A7_REG32(SH7750_IPRB_REGOFS)
                   1575: 
                   1576: #define SH7750_IPRB_WDT       0xF000   /* WDT interrupt priority */
                   1577: #define SH7750_IPRB_WDT_S     12
                   1578: #define SH7750_IPRB_REF       0x0F00   /* Memory Refresh unit interrupt
                   1579:                                           priority */
                   1580: #define SH7750_IPRB_REF_S     8
                   1581: #define SH7750_IPRB_SCI1      0x00F0   /* SCI1 interrupt priority */
                   1582: #define SH7750_IPRB_SCI1_S    4
                   1583: 
                   1584: /* Interrupt Priority Register ˇ - IPRˇ (half) */
                   1585: #define SH7750_IPRC_REGOFS    0xD00004 /* offset */
                   1586: #define SH7750_IPRC           SH7750_P4_REG32(SH7750_IPRC_REGOFS)
                   1587: #define SH7750_IPRC_A7        SH7750_A7_REG32(SH7750_IPRC_REGOFS)
                   1588: 
                   1589: #define SH7750_IPRC_GPIO      0xF000   /* GPIO interrupt priority */
                   1590: #define SH7750_IPRC_GPIO_S    12
                   1591: #define SH7750_IPRC_DMAC      0x0F00   /* DMAC interrupt priority */
                   1592: #define SH7750_IPRC_DMAC_S    8
                   1593: #define SH7750_IPRC_SCIF      0x00F0   /* SCIF interrupt priority */
                   1594: #define SH7750_IPRC_SCIF_S    4
                   1595: #define SH7750_IPRC_HUDI      0x000F   /* H-UDI interrupt priority */
                   1596: #define SH7750_IPRC_HUDI_S    0
                   1597: 
                   1598: 
                   1599: /* 
                   1600:  * User Break Controller registers
                   1601:  */
                   1602: #define SH7750_BARA           0x200000 /* Break address regiser A */
                   1603: #define SH7750_BAMRA          0x200004 /* Break address mask regiser A */
                   1604: #define SH7750_BBRA           0x200008 /* Break bus cycle regiser A */
                   1605: #define SH7750_BARB           0x20000c /* Break address regiser B */
                   1606: #define SH7750_BAMRB          0x200010 /* Break address mask regiser B */
                   1607: #define SH7750_BBRB           0x200014 /* Break bus cycle regiser B */
                   1608: #define SH7750_BASRB          0x000018 /* Break ASID regiser B */
                   1609: #define SH7750_BDRB           0x200018 /* Break data regiser B */
                   1610: #define SH7750_BDMRB          0x20001c /* Break data mask regiser B */
                   1611: #define SH7750_BRCR           0x200020 /* Break control register */
                   1612: 
                   1613: #define SH7750_BRCR_UDBE        0x0001 /* User break debug enable bit */
                   1614: 
                   1615: /*
                   1616:  * Missing in RTEMS, added for QEMU
                   1617:  */
                   1618: #define SH7750_BCR3_A7       0x1f800050
                   1619: #define SH7750_BCR4_A7       0x1e0a00f0
                   1620: #define SH7750_PRECHARGE0_A7 0x1f900088
                   1621: #define SH7750_PRECHARGE1_A7 0x1f940088
                   1622: 
                   1623: #endif

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