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1.1 root 1: /*
2: * QEMU Sparc SLAVIO interrupt controller emulation
1.1.1.4 root 3: *
1.1 root 4: * Copyright (c) 2003-2005 Fabrice Bellard
1.1.1.4 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.6 root 24:
1.1.1.4 root 25: #include "sun4m.h"
1.1.1.6 root 26: #include "monitor.h"
27: #include "sysbus.h"
1.1.1.9 root 28: #include "trace.h"
1.1.1.4 root 29:
1.1 root 30: //#define DEBUG_IRQ_COUNT
31:
32: /*
33: * Registers of interrupt controller in sun4m.
34: *
35: * This is the interrupt controller part of chip STP2001 (Slave I/O), also
36: * produced as NCR89C105. See
37: * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
38: *
39: * There is a system master controller and one for each cpu.
1.1.1.4 root 40: *
1.1 root 41: */
42:
43: #define MAX_CPUS 16
1.1.1.4 root 44: #define MAX_PILS 16
1.1 root 45:
1.1.1.6 root 46: struct SLAVIO_INTCTLState;
47:
48: typedef struct SLAVIO_CPUINTCTLState {
49: struct SLAVIO_INTCTLState *master;
1.1.1.10! root 50: uint32_t intreg_pending;
1.1.1.6 root 51: uint32_t cpu;
1.1.1.7 root 52: uint32_t irl_out;
1.1.1.6 root 53: } SLAVIO_CPUINTCTLState;
1.1.1.5 root 54:
1.1 root 55: typedef struct SLAVIO_INTCTLState {
1.1.1.6 root 56: SysBusDevice busdev;
1.1 root 57: #ifdef DEBUG_IRQ_COUNT
58: uint64_t irq_count[32];
59: #endif
1.1.1.6 root 60: qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
61: SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
1.1.1.10! root 62: uint32_t intregm_pending;
! 63: uint32_t intregm_disabled;
! 64: uint32_t target_cpu;
1.1 root 65: } SLAVIO_INTCTLState;
66:
67: #define INTCTL_MAXADDR 0xf
1.1.1.4 root 68: #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
1.1.1.5 root 69: #define INTCTLM_SIZE 0x14
1.1.1.4 root 70: #define MASTER_IRQ_MASK ~0x0fa2007f
71: #define MASTER_DISABLE 0x80000000
72: #define CPU_SOFTIRQ_MASK 0xfffe0000
1.1.1.7 root 73: #define CPU_IRQ_INT15_IN (1 << 15)
74: #define CPU_IRQ_TIMER_IN (1 << 14)
1.1.1.4 root 75:
1.1.1.6 root 76: static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
1.1 root 77:
78: // per-cpu interrupt controller
79: static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
80: {
1.1.1.5 root 81: SLAVIO_CPUINTCTLState *s = opaque;
1.1.1.4 root 82: uint32_t saddr, ret;
1.1 root 83:
1.1.1.5 root 84: saddr = addr >> 2;
1.1 root 85: switch (saddr) {
86: case 0:
1.1.1.5 root 87: ret = s->intreg_pending;
1.1.1.4 root 88: break;
1.1 root 89: default:
1.1.1.4 root 90: ret = 0;
91: break;
1.1 root 92: }
1.1.1.9 root 93: trace_slavio_intctl_mem_readl(s->cpu, addr, ret);
1.1.1.4 root 94:
95: return ret;
1.1 root 96: }
97:
1.1.1.5 root 98: static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
99: uint32_t val)
1.1 root 100: {
1.1.1.5 root 101: SLAVIO_CPUINTCTLState *s = opaque;
1.1 root 102: uint32_t saddr;
103:
1.1.1.5 root 104: saddr = addr >> 2;
1.1.1.9 root 105: trace_slavio_intctl_mem_writel(s->cpu, addr, val);
1.1 root 106: switch (saddr) {
107: case 1: // clear pending softints
1.1.1.7 root 108: val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN;
1.1.1.5 root 109: s->intreg_pending &= ~val;
1.1.1.6 root 110: slavio_check_interrupts(s->master, 1);
1.1.1.9 root 111: trace_slavio_intctl_mem_writel_clear(s->cpu, val, s->intreg_pending);
1.1.1.4 root 112: break;
1.1 root 113: case 2: // set softint
1.1.1.4 root 114: val &= CPU_SOFTIRQ_MASK;
1.1.1.5 root 115: s->intreg_pending |= val;
1.1.1.6 root 116: slavio_check_interrupts(s->master, 1);
1.1.1.9 root 117: trace_slavio_intctl_mem_writel_set(s->cpu, val, s->intreg_pending);
1.1.1.4 root 118: break;
1.1 root 119: default:
1.1.1.4 root 120: break;
1.1 root 121: }
122: }
123:
1.1.1.7 root 124: static CPUReadMemoryFunc * const slavio_intctl_mem_read[3] = {
1.1.1.4 root 125: NULL,
126: NULL,
1.1 root 127: slavio_intctl_mem_readl,
128: };
129:
1.1.1.7 root 130: static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = {
1.1.1.4 root 131: NULL,
132: NULL,
1.1 root 133: slavio_intctl_mem_writel,
134: };
135:
136: // master system interrupt controller
137: static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
138: {
139: SLAVIO_INTCTLState *s = opaque;
1.1.1.4 root 140: uint32_t saddr, ret;
1.1 root 141:
1.1.1.5 root 142: saddr = addr >> 2;
1.1 root 143: switch (saddr) {
144: case 0:
1.1.1.4 root 145: ret = s->intregm_pending & ~MASTER_DISABLE;
146: break;
1.1 root 147: case 1:
1.1.1.4 root 148: ret = s->intregm_disabled & MASTER_IRQ_MASK;
149: break;
1.1 root 150: case 4:
1.1.1.4 root 151: ret = s->target_cpu;
152: break;
1.1 root 153: default:
1.1.1.4 root 154: ret = 0;
155: break;
1.1 root 156: }
1.1.1.9 root 157: trace_slavio_intctlm_mem_readl(addr, ret);
1.1.1.4 root 158:
159: return ret;
1.1 root 160: }
161:
1.1.1.5 root 162: static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
163: uint32_t val)
1.1 root 164: {
165: SLAVIO_INTCTLState *s = opaque;
166: uint32_t saddr;
167:
1.1.1.5 root 168: saddr = addr >> 2;
1.1.1.9 root 169: trace_slavio_intctlm_mem_writel(addr, val);
1.1 root 170: switch (saddr) {
171: case 2: // clear (enable)
1.1.1.4 root 172: // Force clear unused bits
173: val &= MASTER_IRQ_MASK;
174: s->intregm_disabled &= ~val;
1.1.1.9 root 175: trace_slavio_intctlm_mem_writel_enable(val, s->intregm_disabled);
1.1.1.6 root 176: slavio_check_interrupts(s, 1);
1.1.1.4 root 177: break;
1.1.1.8 root 178: case 3: // set (disable; doesn't affect pending)
1.1.1.4 root 179: // Force clear unused bits
180: val &= MASTER_IRQ_MASK;
181: s->intregm_disabled |= val;
1.1.1.6 root 182: slavio_check_interrupts(s, 1);
1.1.1.9 root 183: trace_slavio_intctlm_mem_writel_disable(val, s->intregm_disabled);
1.1.1.4 root 184: break;
1.1 root 185: case 4:
1.1.1.4 root 186: s->target_cpu = val & (MAX_CPUS - 1);
1.1.1.6 root 187: slavio_check_interrupts(s, 1);
1.1.1.9 root 188: trace_slavio_intctlm_mem_writel_target(s->target_cpu);
1.1.1.4 root 189: break;
1.1 root 190: default:
1.1.1.4 root 191: break;
1.1 root 192: }
193: }
194:
1.1.1.7 root 195: static CPUReadMemoryFunc * const slavio_intctlm_mem_read[3] = {
1.1.1.4 root 196: NULL,
197: NULL,
1.1 root 198: slavio_intctlm_mem_readl,
199: };
200:
1.1.1.7 root 201: static CPUWriteMemoryFunc * const slavio_intctlm_mem_write[3] = {
1.1.1.4 root 202: NULL,
203: NULL,
1.1 root 204: slavio_intctlm_mem_writel,
205: };
206:
1.1.1.7 root 207: void slavio_pic_info(Monitor *mon, DeviceState *dev)
1.1 root 208: {
1.1.1.7 root 209: SysBusDevice *sd;
210: SLAVIO_INTCTLState *s;
1.1 root 211: int i;
212:
1.1.1.7 root 213: sd = sysbus_from_qdev(dev);
214: s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
1.1 root 215: for (i = 0; i < MAX_CPUS; i++) {
1.1.1.6 root 216: monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
217: s->slaves[i].intreg_pending);
1.1 root 218: }
1.1.1.6 root 219: monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
220: s->intregm_pending, s->intregm_disabled);
1.1 root 221: }
222:
1.1.1.7 root 223: void slavio_irq_info(Monitor *mon, DeviceState *dev)
1.1 root 224: {
225: #ifndef DEBUG_IRQ_COUNT
1.1.1.6 root 226: monitor_printf(mon, "irq statistic code not compiled.\n");
1.1 root 227: #else
1.1.1.7 root 228: SysBusDevice *sd;
229: SLAVIO_INTCTLState *s;
1.1 root 230: int i;
231: int64_t count;
232:
1.1.1.7 root 233: sd = sysbus_from_qdev(dev);
234: s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
1.1.1.6 root 235: monitor_printf(mon, "IRQ statistics:\n");
1.1 root 236: for (i = 0; i < 32; i++) {
237: count = s->irq_count[i];
238: if (count > 0)
1.1.1.6 root 239: monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
1.1 root 240: }
241: #endif
242: }
243:
1.1.1.7 root 244: static const uint32_t intbit_to_level[] = {
245: 2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12,
246: 6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0,
247: };
248:
1.1.1.6 root 249: static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
1.1 root 250: {
1.1.1.4 root 251: uint32_t pending = s->intregm_pending, pil_pending;
252: unsigned int i, j;
1.1 root 253:
254: pending &= ~s->intregm_disabled;
255:
1.1.1.9 root 256: trace_slavio_check_interrupts(pending, s->intregm_disabled);
1.1.1.2 root 257: for (i = 0; i < MAX_CPUS; i++) {
1.1.1.4 root 258: pil_pending = 0;
1.1.1.7 root 259:
260: /* If we are the current interrupt target, get hard interrupts */
1.1.1.4 root 261: if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
262: (i == s->target_cpu)) {
263: for (j = 0; j < 32; j++) {
1.1.1.7 root 264: if ((pending & (1 << j)) && intbit_to_level[j]) {
265: pil_pending |= 1 << intbit_to_level[j];
266: }
1.1.1.2 root 267: }
268: }
1.1.1.7 root 269:
270: /* Calculate current pending hard interrupts for display */
271: s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN |
272: CPU_IRQ_TIMER_IN;
273: if (i == s->target_cpu) {
274: for (j = 0; j < 32; j++) {
275: if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) {
276: s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
277: }
278: }
279: }
280:
1.1.1.8 root 281: /* Level 15 and CPU timer interrupts are only masked when
282: the MASTER_DISABLE bit is set */
283: if (!(s->intregm_disabled & MASTER_DISABLE)) {
284: pil_pending |= s->slaves[i].intreg_pending &
285: (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
286: }
1.1.1.7 root 287:
288: /* Add soft interrupts */
1.1.1.6 root 289: pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
1.1.1.4 root 290:
1.1.1.6 root 291: if (set_irqs) {
1.1.1.9 root 292: /* Since there is not really an interrupt 0 (and pil_pending
293: * and irl_out bit zero are thus always zero) there is no need
294: * to do anything with cpu_irqs[i][0] and it is OK not to do
295: * the j=0 iteration of this loop.
296: */
297: for (j = MAX_PILS-1; j > 0; j--) {
1.1.1.6 root 298: if (pil_pending & (1 << j)) {
1.1.1.7 root 299: if (!(s->slaves[i].irl_out & (1 << j))) {
1.1.1.6 root 300: qemu_irq_raise(s->cpu_irqs[i][j]);
301: }
302: } else {
1.1.1.7 root 303: if (s->slaves[i].irl_out & (1 << j)) {
1.1.1.6 root 304: qemu_irq_lower(s->cpu_irqs[i][j]);
305: }
306: }
1.1.1.2 root 307: }
308: }
1.1.1.7 root 309: s->slaves[i].irl_out = pil_pending;
1.1.1.2 root 310: }
1.1 root 311: }
312:
313: /*
314: * "irq" here is the bit number in the system interrupt register to
315: * separate serial and keyboard interrupts sharing a level.
316: */
1.1.1.4 root 317: static void slavio_set_irq(void *opaque, int irq, int level)
1.1 root 318: {
319: SLAVIO_INTCTLState *s = opaque;
1.1.1.4 root 320: uint32_t mask = 1 << irq;
1.1.1.7 root 321: uint32_t pil = intbit_to_level[irq];
322: unsigned int i;
1.1 root 323:
1.1.1.9 root 324: trace_slavio_set_irq(s->target_cpu, irq, pil, level);
1.1.1.4 root 325: if (pil > 0) {
326: if (level) {
327: #ifdef DEBUG_IRQ_COUNT
328: s->irq_count[pil]++;
329: #endif
330: s->intregm_pending |= mask;
1.1.1.7 root 331: if (pil == 15) {
332: for (i = 0; i < MAX_CPUS; i++) {
333: s->slaves[i].intreg_pending |= 1 << pil;
334: }
335: }
1.1.1.4 root 336: } else {
337: s->intregm_pending &= ~mask;
1.1.1.7 root 338: if (pil == 15) {
339: for (i = 0; i < MAX_CPUS; i++) {
340: s->slaves[i].intreg_pending &= ~(1 << pil);
341: }
342: }
1.1.1.4 root 343: }
1.1.1.6 root 344: slavio_check_interrupts(s, 1);
1.1 root 345: }
346: }
347:
1.1.1.4 root 348: static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
1.1.1.2 root 349: {
350: SLAVIO_INTCTLState *s = opaque;
351:
1.1.1.9 root 352: trace_slavio_set_timer_irq_cpu(cpu, level);
1.1.1.4 root 353:
354: if (level) {
1.1.1.7 root 355: s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN;
1.1.1.4 root 356: } else {
1.1.1.7 root 357: s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN;
1.1.1.2 root 358: }
1.1.1.4 root 359:
1.1.1.6 root 360: slavio_check_interrupts(s, 1);
361: }
362:
363: static void slavio_set_irq_all(void *opaque, int irq, int level)
364: {
365: if (irq < 32) {
366: slavio_set_irq(opaque, irq, level);
367: } else {
368: slavio_set_timer_irq_cpu(opaque, irq - 32, level);
369: }
1.1.1.2 root 370: }
371:
1.1.1.7 root 372: static int vmstate_intctl_post_load(void *opaque, int version_id)
1.1 root 373: {
374: SLAVIO_INTCTLState *s = opaque;
1.1.1.4 root 375:
1.1.1.7 root 376: slavio_check_interrupts(s, 0);
377: return 0;
1.1 root 378: }
379:
1.1.1.7 root 380: static const VMStateDescription vmstate_intctl_cpu = {
381: .name ="slavio_intctl_cpu",
382: .version_id = 1,
383: .minimum_version_id = 1,
384: .minimum_version_id_old = 1,
385: .fields = (VMStateField []) {
386: VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState),
387: VMSTATE_END_OF_LIST()
388: }
389: };
1.1 root 390:
1.1.1.7 root 391: static const VMStateDescription vmstate_intctl = {
392: .name ="slavio_intctl",
393: .version_id = 1,
394: .minimum_version_id = 1,
395: .minimum_version_id_old = 1,
396: .post_load = vmstate_intctl_post_load,
397: .fields = (VMStateField []) {
398: VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
399: vmstate_intctl_cpu, SLAVIO_CPUINTCTLState),
400: VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState),
401: VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState),
402: VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState),
403: VMSTATE_END_OF_LIST()
1.1 root 404: }
1.1.1.7 root 405: };
1.1 root 406:
1.1.1.7 root 407: static void slavio_intctl_reset(DeviceState *d)
1.1 root 408: {
1.1.1.7 root 409: SLAVIO_INTCTLState *s = container_of(d, SLAVIO_INTCTLState, busdev.qdev);
1.1 root 410: int i;
411:
412: for (i = 0; i < MAX_CPUS; i++) {
1.1.1.6 root 413: s->slaves[i].intreg_pending = 0;
1.1.1.7 root 414: s->slaves[i].irl_out = 0;
1.1 root 415: }
1.1.1.4 root 416: s->intregm_disabled = ~MASTER_IRQ_MASK;
1.1 root 417: s->intregm_pending = 0;
418: s->target_cpu = 0;
1.1.1.6 root 419: slavio_check_interrupts(s, 0);
1.1 root 420: }
421:
1.1.1.7 root 422: static int slavio_intctl_init1(SysBusDevice *dev)
1.1 root 423: {
1.1.1.6 root 424: SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
425: int io_memory;
426: unsigned int i, j;
1.1 root 427:
1.1.1.6 root 428: qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
429: io_memory = cpu_register_io_memory(slavio_intctlm_mem_read,
1.1.1.9 root 430: slavio_intctlm_mem_write, s,
431: DEVICE_NATIVE_ENDIAN);
1.1.1.6 root 432: sysbus_init_mmio(dev, INTCTLM_SIZE, io_memory);
1.1 root 433:
434: for (i = 0; i < MAX_CPUS; i++) {
1.1.1.6 root 435: for (j = 0; j < MAX_PILS; j++) {
436: sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
437: }
438: io_memory = cpu_register_io_memory(slavio_intctl_mem_read,
439: slavio_intctl_mem_write,
1.1.1.9 root 440: &s->slaves[i],
441: DEVICE_NATIVE_ENDIAN);
1.1.1.6 root 442: sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
443: s->slaves[i].cpu = i;
444: s->slaves[i].master = s;
445: }
446:
1.1.1.7 root 447: return 0;
1.1.1.6 root 448: }
1.1 root 449:
1.1.1.6 root 450: static SysBusDeviceInfo slavio_intctl_info = {
451: .init = slavio_intctl_init1,
452: .qdev.name = "slavio_intctl",
453: .qdev.size = sizeof(SLAVIO_INTCTLState),
1.1.1.7 root 454: .qdev.vmsd = &vmstate_intctl,
455: .qdev.reset = slavio_intctl_reset,
1.1.1.6 root 456: };
1.1.1.4 root 457:
1.1.1.6 root 458: static void slavio_intctl_register_devices(void)
459: {
460: sysbus_register_withprop(&slavio_intctl_info);
1.1 root 461: }
1.1.1.6 root 462:
463: device_init(slavio_intctl_register_devices)
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