![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to slavio_intctl.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / hw|
Return to slavio_intctl.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu / hw |
1.1 root 1: /*
2: * QEMU Sparc SLAVIO interrupt controller emulation
1.1.1.4 root 3: *
1.1 root 4: * Copyright (c) 2003-2005 Fabrice Bellard
1.1.1.4 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.6 root 24:
1.1.1.4 root 25: #include "sun4m.h"
1.1.1.6 root 26: #include "monitor.h"
27: #include "sysbus.h"
1.1.1.9 root 28: #include "trace.h"
1.1.1.4 root 29:
1.1 root 30: //#define DEBUG_IRQ_COUNT
31:
32: /*
33: * Registers of interrupt controller in sun4m.
34: *
35: * This is the interrupt controller part of chip STP2001 (Slave I/O), also
36: * produced as NCR89C105. See
37: * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
38: *
39: * There is a system master controller and one for each cpu.
1.1.1.4 root 40: *
1.1 root 41: */
42:
43: #define MAX_CPUS 16
1.1.1.4 root 44: #define MAX_PILS 16
1.1 root 45:
1.1.1.6 root 46: struct SLAVIO_INTCTLState;
47:
48: typedef struct SLAVIO_CPUINTCTLState {
1.1.1.11! root 49: MemoryRegion iomem;
1.1.1.6 root 50: struct SLAVIO_INTCTLState *master;
1.1.1.10 root 51: uint32_t intreg_pending;
1.1.1.6 root 52: uint32_t cpu;
1.1.1.7 root 53: uint32_t irl_out;
1.1.1.6 root 54: } SLAVIO_CPUINTCTLState;
1.1.1.5 root 55:
1.1 root 56: typedef struct SLAVIO_INTCTLState {
1.1.1.6 root 57: SysBusDevice busdev;
1.1.1.11! root 58: MemoryRegion iomem;
1.1 root 59: #ifdef DEBUG_IRQ_COUNT
60: uint64_t irq_count[32];
61: #endif
1.1.1.6 root 62: qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
63: SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
1.1.1.10 root 64: uint32_t intregm_pending;
65: uint32_t intregm_disabled;
66: uint32_t target_cpu;
1.1 root 67: } SLAVIO_INTCTLState;
68:
69: #define INTCTL_MAXADDR 0xf
1.1.1.4 root 70: #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
1.1.1.5 root 71: #define INTCTLM_SIZE 0x14
1.1.1.4 root 72: #define MASTER_IRQ_MASK ~0x0fa2007f
73: #define MASTER_DISABLE 0x80000000
74: #define CPU_SOFTIRQ_MASK 0xfffe0000
1.1.1.7 root 75: #define CPU_IRQ_INT15_IN (1 << 15)
76: #define CPU_IRQ_TIMER_IN (1 << 14)
1.1.1.4 root 77:
1.1.1.6 root 78: static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
1.1 root 79:
80: // per-cpu interrupt controller
1.1.1.11! root 81: static uint64_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr,
! 82: unsigned size)
1.1 root 83: {
1.1.1.5 root 84: SLAVIO_CPUINTCTLState *s = opaque;
1.1.1.4 root 85: uint32_t saddr, ret;
1.1 root 86:
1.1.1.5 root 87: saddr = addr >> 2;
1.1 root 88: switch (saddr) {
89: case 0:
1.1.1.5 root 90: ret = s->intreg_pending;
1.1.1.4 root 91: break;
1.1 root 92: default:
1.1.1.4 root 93: ret = 0;
94: break;
1.1 root 95: }
1.1.1.9 root 96: trace_slavio_intctl_mem_readl(s->cpu, addr, ret);
1.1.1.4 root 97:
98: return ret;
1.1 root 99: }
100:
1.1.1.5 root 101: static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
1.1.1.11! root 102: uint64_t val, unsigned size)
1.1 root 103: {
1.1.1.5 root 104: SLAVIO_CPUINTCTLState *s = opaque;
1.1 root 105: uint32_t saddr;
106:
1.1.1.5 root 107: saddr = addr >> 2;
1.1.1.9 root 108: trace_slavio_intctl_mem_writel(s->cpu, addr, val);
1.1 root 109: switch (saddr) {
110: case 1: // clear pending softints
1.1.1.7 root 111: val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN;
1.1.1.5 root 112: s->intreg_pending &= ~val;
1.1.1.6 root 113: slavio_check_interrupts(s->master, 1);
1.1.1.9 root 114: trace_slavio_intctl_mem_writel_clear(s->cpu, val, s->intreg_pending);
1.1.1.4 root 115: break;
1.1 root 116: case 2: // set softint
1.1.1.4 root 117: val &= CPU_SOFTIRQ_MASK;
1.1.1.5 root 118: s->intreg_pending |= val;
1.1.1.6 root 119: slavio_check_interrupts(s->master, 1);
1.1.1.9 root 120: trace_slavio_intctl_mem_writel_set(s->cpu, val, s->intreg_pending);
1.1.1.4 root 121: break;
1.1 root 122: default:
1.1.1.4 root 123: break;
1.1 root 124: }
125: }
126:
1.1.1.11! root 127: static const MemoryRegionOps slavio_intctl_mem_ops = {
! 128: .read = slavio_intctl_mem_readl,
! 129: .write = slavio_intctl_mem_writel,
! 130: .endianness = DEVICE_NATIVE_ENDIAN,
! 131: .valid = {
! 132: .min_access_size = 4,
! 133: .max_access_size = 4,
! 134: },
1.1 root 135: };
136:
137: // master system interrupt controller
1.1.1.11! root 138: static uint64_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr,
! 139: unsigned size)
1.1 root 140: {
141: SLAVIO_INTCTLState *s = opaque;
1.1.1.4 root 142: uint32_t saddr, ret;
1.1 root 143:
1.1.1.5 root 144: saddr = addr >> 2;
1.1 root 145: switch (saddr) {
146: case 0:
1.1.1.4 root 147: ret = s->intregm_pending & ~MASTER_DISABLE;
148: break;
1.1 root 149: case 1:
1.1.1.4 root 150: ret = s->intregm_disabled & MASTER_IRQ_MASK;
151: break;
1.1 root 152: case 4:
1.1.1.4 root 153: ret = s->target_cpu;
154: break;
1.1 root 155: default:
1.1.1.4 root 156: ret = 0;
157: break;
1.1 root 158: }
1.1.1.9 root 159: trace_slavio_intctlm_mem_readl(addr, ret);
1.1.1.4 root 160:
161: return ret;
1.1 root 162: }
163:
1.1.1.5 root 164: static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
1.1.1.11! root 165: uint64_t val, unsigned size)
1.1 root 166: {
167: SLAVIO_INTCTLState *s = opaque;
168: uint32_t saddr;
169:
1.1.1.5 root 170: saddr = addr >> 2;
1.1.1.9 root 171: trace_slavio_intctlm_mem_writel(addr, val);
1.1 root 172: switch (saddr) {
173: case 2: // clear (enable)
1.1.1.4 root 174: // Force clear unused bits
175: val &= MASTER_IRQ_MASK;
176: s->intregm_disabled &= ~val;
1.1.1.9 root 177: trace_slavio_intctlm_mem_writel_enable(val, s->intregm_disabled);
1.1.1.6 root 178: slavio_check_interrupts(s, 1);
1.1.1.4 root 179: break;
1.1.1.8 root 180: case 3: // set (disable; doesn't affect pending)
1.1.1.4 root 181: // Force clear unused bits
182: val &= MASTER_IRQ_MASK;
183: s->intregm_disabled |= val;
1.1.1.6 root 184: slavio_check_interrupts(s, 1);
1.1.1.9 root 185: trace_slavio_intctlm_mem_writel_disable(val, s->intregm_disabled);
1.1.1.4 root 186: break;
1.1 root 187: case 4:
1.1.1.4 root 188: s->target_cpu = val & (MAX_CPUS - 1);
1.1.1.6 root 189: slavio_check_interrupts(s, 1);
1.1.1.9 root 190: trace_slavio_intctlm_mem_writel_target(s->target_cpu);
1.1.1.4 root 191: break;
1.1 root 192: default:
1.1.1.4 root 193: break;
1.1 root 194: }
195: }
196:
1.1.1.11! root 197: static const MemoryRegionOps slavio_intctlm_mem_ops = {
! 198: .read = slavio_intctlm_mem_readl,
! 199: .write = slavio_intctlm_mem_writel,
! 200: .endianness = DEVICE_NATIVE_ENDIAN,
! 201: .valid = {
! 202: .min_access_size = 4,
! 203: .max_access_size = 4,
! 204: },
1.1 root 205: };
206:
1.1.1.7 root 207: void slavio_pic_info(Monitor *mon, DeviceState *dev)
1.1 root 208: {
1.1.1.7 root 209: SysBusDevice *sd;
210: SLAVIO_INTCTLState *s;
1.1 root 211: int i;
212:
1.1.1.7 root 213: sd = sysbus_from_qdev(dev);
214: s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
1.1 root 215: for (i = 0; i < MAX_CPUS; i++) {
1.1.1.6 root 216: monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
217: s->slaves[i].intreg_pending);
1.1 root 218: }
1.1.1.6 root 219: monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
220: s->intregm_pending, s->intregm_disabled);
1.1 root 221: }
222:
1.1.1.7 root 223: void slavio_irq_info(Monitor *mon, DeviceState *dev)
1.1 root 224: {
225: #ifndef DEBUG_IRQ_COUNT
1.1.1.6 root 226: monitor_printf(mon, "irq statistic code not compiled.\n");
1.1 root 227: #else
1.1.1.7 root 228: SysBusDevice *sd;
229: SLAVIO_INTCTLState *s;
1.1 root 230: int i;
231: int64_t count;
232:
1.1.1.7 root 233: sd = sysbus_from_qdev(dev);
234: s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
1.1.1.6 root 235: monitor_printf(mon, "IRQ statistics:\n");
1.1 root 236: for (i = 0; i < 32; i++) {
237: count = s->irq_count[i];
238: if (count > 0)
1.1.1.6 root 239: monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
1.1 root 240: }
241: #endif
242: }
243:
1.1.1.7 root 244: static const uint32_t intbit_to_level[] = {
245: 2, 3, 5, 7, 9, 11, 13, 2, 3, 5, 7, 9, 11, 13, 12, 12,
246: 6, 13, 4, 10, 8, 9, 11, 0, 0, 0, 0, 15, 15, 15, 15, 0,
247: };
248:
1.1.1.6 root 249: static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
1.1 root 250: {
1.1.1.4 root 251: uint32_t pending = s->intregm_pending, pil_pending;
252: unsigned int i, j;
1.1 root 253:
254: pending &= ~s->intregm_disabled;
255:
1.1.1.9 root 256: trace_slavio_check_interrupts(pending, s->intregm_disabled);
1.1.1.2 root 257: for (i = 0; i < MAX_CPUS; i++) {
1.1.1.4 root 258: pil_pending = 0;
1.1.1.7 root 259:
260: /* If we are the current interrupt target, get hard interrupts */
1.1.1.4 root 261: if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
262: (i == s->target_cpu)) {
263: for (j = 0; j < 32; j++) {
1.1.1.7 root 264: if ((pending & (1 << j)) && intbit_to_level[j]) {
265: pil_pending |= 1 << intbit_to_level[j];
266: }
1.1.1.2 root 267: }
268: }
1.1.1.7 root 269:
270: /* Calculate current pending hard interrupts for display */
271: s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN |
272: CPU_IRQ_TIMER_IN;
273: if (i == s->target_cpu) {
274: for (j = 0; j < 32; j++) {
275: if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) {
276: s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
277: }
278: }
279: }
280:
1.1.1.8 root 281: /* Level 15 and CPU timer interrupts are only masked when
282: the MASTER_DISABLE bit is set */
283: if (!(s->intregm_disabled & MASTER_DISABLE)) {
284: pil_pending |= s->slaves[i].intreg_pending &
285: (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
286: }
1.1.1.7 root 287:
288: /* Add soft interrupts */
1.1.1.6 root 289: pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
1.1.1.4 root 290:
1.1.1.6 root 291: if (set_irqs) {
1.1.1.9 root 292: /* Since there is not really an interrupt 0 (and pil_pending
293: * and irl_out bit zero are thus always zero) there is no need
294: * to do anything with cpu_irqs[i][0] and it is OK not to do
295: * the j=0 iteration of this loop.
296: */
297: for (j = MAX_PILS-1; j > 0; j--) {
1.1.1.6 root 298: if (pil_pending & (1 << j)) {
1.1.1.7 root 299: if (!(s->slaves[i].irl_out & (1 << j))) {
1.1.1.6 root 300: qemu_irq_raise(s->cpu_irqs[i][j]);
301: }
302: } else {
1.1.1.7 root 303: if (s->slaves[i].irl_out & (1 << j)) {
1.1.1.6 root 304: qemu_irq_lower(s->cpu_irqs[i][j]);
305: }
306: }
1.1.1.2 root 307: }
308: }
1.1.1.7 root 309: s->slaves[i].irl_out = pil_pending;
1.1.1.2 root 310: }
1.1 root 311: }
312:
313: /*
314: * "irq" here is the bit number in the system interrupt register to
315: * separate serial and keyboard interrupts sharing a level.
316: */
1.1.1.4 root 317: static void slavio_set_irq(void *opaque, int irq, int level)
1.1 root 318: {
319: SLAVIO_INTCTLState *s = opaque;
1.1.1.4 root 320: uint32_t mask = 1 << irq;
1.1.1.7 root 321: uint32_t pil = intbit_to_level[irq];
322: unsigned int i;
1.1 root 323:
1.1.1.9 root 324: trace_slavio_set_irq(s->target_cpu, irq, pil, level);
1.1.1.4 root 325: if (pil > 0) {
326: if (level) {
327: #ifdef DEBUG_IRQ_COUNT
328: s->irq_count[pil]++;
329: #endif
330: s->intregm_pending |= mask;
1.1.1.7 root 331: if (pil == 15) {
332: for (i = 0; i < MAX_CPUS; i++) {
333: s->slaves[i].intreg_pending |= 1 << pil;
334: }
335: }
1.1.1.4 root 336: } else {
337: s->intregm_pending &= ~mask;
1.1.1.7 root 338: if (pil == 15) {
339: for (i = 0; i < MAX_CPUS; i++) {
340: s->slaves[i].intreg_pending &= ~(1 << pil);
341: }
342: }
1.1.1.4 root 343: }
1.1.1.6 root 344: slavio_check_interrupts(s, 1);
1.1 root 345: }
346: }
347:
1.1.1.4 root 348: static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
1.1.1.2 root 349: {
350: SLAVIO_INTCTLState *s = opaque;
351:
1.1.1.9 root 352: trace_slavio_set_timer_irq_cpu(cpu, level);
1.1.1.4 root 353:
354: if (level) {
1.1.1.7 root 355: s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN;
1.1.1.4 root 356: } else {
1.1.1.7 root 357: s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN;
1.1.1.2 root 358: }
1.1.1.4 root 359:
1.1.1.6 root 360: slavio_check_interrupts(s, 1);
361: }
362:
363: static void slavio_set_irq_all(void *opaque, int irq, int level)
364: {
365: if (irq < 32) {
366: slavio_set_irq(opaque, irq, level);
367: } else {
368: slavio_set_timer_irq_cpu(opaque, irq - 32, level);
369: }
1.1.1.2 root 370: }
371:
1.1.1.7 root 372: static int vmstate_intctl_post_load(void *opaque, int version_id)
1.1 root 373: {
374: SLAVIO_INTCTLState *s = opaque;
1.1.1.4 root 375:
1.1.1.7 root 376: slavio_check_interrupts(s, 0);
377: return 0;
1.1 root 378: }
379:
1.1.1.7 root 380: static const VMStateDescription vmstate_intctl_cpu = {
381: .name ="slavio_intctl_cpu",
382: .version_id = 1,
383: .minimum_version_id = 1,
384: .minimum_version_id_old = 1,
385: .fields = (VMStateField []) {
386: VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState),
387: VMSTATE_END_OF_LIST()
388: }
389: };
1.1 root 390:
1.1.1.7 root 391: static const VMStateDescription vmstate_intctl = {
392: .name ="slavio_intctl",
393: .version_id = 1,
394: .minimum_version_id = 1,
395: .minimum_version_id_old = 1,
396: .post_load = vmstate_intctl_post_load,
397: .fields = (VMStateField []) {
398: VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
399: vmstate_intctl_cpu, SLAVIO_CPUINTCTLState),
400: VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState),
401: VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState),
402: VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState),
403: VMSTATE_END_OF_LIST()
1.1 root 404: }
1.1.1.7 root 405: };
1.1 root 406:
1.1.1.7 root 407: static void slavio_intctl_reset(DeviceState *d)
1.1 root 408: {
1.1.1.7 root 409: SLAVIO_INTCTLState *s = container_of(d, SLAVIO_INTCTLState, busdev.qdev);
1.1 root 410: int i;
411:
412: for (i = 0; i < MAX_CPUS; i++) {
1.1.1.6 root 413: s->slaves[i].intreg_pending = 0;
1.1.1.7 root 414: s->slaves[i].irl_out = 0;
1.1 root 415: }
1.1.1.4 root 416: s->intregm_disabled = ~MASTER_IRQ_MASK;
1.1 root 417: s->intregm_pending = 0;
418: s->target_cpu = 0;
1.1.1.6 root 419: slavio_check_interrupts(s, 0);
1.1 root 420: }
421:
1.1.1.7 root 422: static int slavio_intctl_init1(SysBusDevice *dev)
1.1 root 423: {
1.1.1.6 root 424: SLAVIO_INTCTLState *s = FROM_SYSBUS(SLAVIO_INTCTLState, dev);
425: unsigned int i, j;
1.1.1.11! root 426: char slave_name[45];
1.1 root 427:
1.1.1.6 root 428: qdev_init_gpio_in(&dev->qdev, slavio_set_irq_all, 32 + MAX_CPUS);
1.1.1.11! root 429: memory_region_init_io(&s->iomem, &slavio_intctlm_mem_ops, s,
! 430: "master-interrupt-controller", INTCTLM_SIZE);
! 431: sysbus_init_mmio(dev, &s->iomem);
1.1 root 432:
433: for (i = 0; i < MAX_CPUS; i++) {
1.1.1.11! root 434: snprintf(slave_name, sizeof(slave_name),
! 435: "slave-interrupt-controller-%i", i);
1.1.1.6 root 436: for (j = 0; j < MAX_PILS; j++) {
437: sysbus_init_irq(dev, &s->cpu_irqs[i][j]);
438: }
1.1.1.11! root 439: memory_region_init_io(&s->slaves[i].iomem, &slavio_intctl_mem_ops,
! 440: &s->slaves[i], slave_name, INTCTL_SIZE);
! 441: sysbus_init_mmio(dev, &s->slaves[i].iomem);
1.1.1.6 root 442: s->slaves[i].cpu = i;
443: s->slaves[i].master = s;
444: }
445:
1.1.1.7 root 446: return 0;
1.1.1.6 root 447: }
1.1 root 448:
1.1.1.11! root 449: static void slavio_intctl_class_init(ObjectClass *klass, void *data)
! 450: {
! 451: DeviceClass *dc = DEVICE_CLASS(klass);
! 452: SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
! 453:
! 454: k->init = slavio_intctl_init1;
! 455: dc->reset = slavio_intctl_reset;
! 456: dc->vmsd = &vmstate_intctl;
! 457: }
! 458:
! 459: static TypeInfo slavio_intctl_info = {
! 460: .name = "slavio_intctl",
! 461: .parent = TYPE_SYS_BUS_DEVICE,
! 462: .instance_size = sizeof(SLAVIO_INTCTLState),
! 463: .class_init = slavio_intctl_class_init,
1.1.1.6 root 464: };
1.1.1.4 root 465:
1.1.1.11! root 466: static void slavio_intctl_register_types(void)
1.1.1.6 root 467: {
1.1.1.11! root 468: type_register_static(&slavio_intctl_info);
1.1 root 469: }
1.1.1.6 root 470:
1.1.1.11! root 471: type_init(slavio_intctl_register_types)
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.