Annotation of qemu/hw/slavio_intctl.c, revision 1.1.1.5

1.1       root        1: /*
                      2:  * QEMU Sparc SLAVIO interrupt controller emulation
1.1.1.4   root        3:  *
1.1       root        4:  * Copyright (c) 2003-2005 Fabrice Bellard
1.1.1.4   root        5:  *
1.1       root        6:  * Permission is hereby granted, free of charge, to any person obtaining a copy
                      7:  * of this software and associated documentation files (the "Software"), to deal
                      8:  * in the Software without restriction, including without limitation the rights
                      9:  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
                     10:  * copies of the Software, and to permit persons to whom the Software is
                     11:  * furnished to do so, subject to the following conditions:
                     12:  *
                     13:  * The above copyright notice and this permission notice shall be included in
                     14:  * all copies or substantial portions of the Software.
                     15:  *
                     16:  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
                     17:  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
                     18:  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
                     19:  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
                     20:  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
                     21:  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
                     22:  * THE SOFTWARE.
                     23:  */
1.1.1.4   root       24: #include "hw.h"
                     25: #include "sun4m.h"
                     26: #include "console.h"
                     27: 
1.1       root       28: //#define DEBUG_IRQ_COUNT
                     29: //#define DEBUG_IRQ
                     30: 
                     31: #ifdef DEBUG_IRQ
                     32: #define DPRINTF(fmt, args...) \
                     33: do { printf("IRQ: " fmt , ##args); } while (0)
                     34: #else
                     35: #define DPRINTF(fmt, args...)
                     36: #endif
                     37: 
                     38: /*
                     39:  * Registers of interrupt controller in sun4m.
                     40:  *
                     41:  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
                     42:  * produced as NCR89C105. See
                     43:  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
                     44:  *
                     45:  * There is a system master controller and one for each cpu.
1.1.1.4   root       46:  *
1.1       root       47:  */
                     48: 
                     49: #define MAX_CPUS 16
1.1.1.4   root       50: #define MAX_PILS 16
1.1       root       51: 
1.1.1.5 ! root       52: struct SLAVIO_CPUINTCTLState;
        !            53: 
1.1       root       54: typedef struct SLAVIO_INTCTLState {
                     55:     uint32_t intregm_pending;
                     56:     uint32_t intregm_disabled;
                     57:     uint32_t target_cpu;
                     58: #ifdef DEBUG_IRQ_COUNT
                     59:     uint64_t irq_count[32];
                     60: #endif
1.1.1.4   root       61:     qemu_irq *cpu_irqs[MAX_CPUS];
                     62:     const uint32_t *intbit_to_level;
                     63:     uint32_t cputimer_lbit, cputimer_mbit;
                     64:     uint32_t pil_out[MAX_CPUS];
1.1.1.5 ! root       65:     struct SLAVIO_CPUINTCTLState *slaves[MAX_CPUS];
1.1       root       66: } SLAVIO_INTCTLState;
                     67: 
1.1.1.5 ! root       68: typedef struct SLAVIO_CPUINTCTLState {
        !            69:     uint32_t intreg_pending;
        !            70:     SLAVIO_INTCTLState *master;
        !            71:     uint32_t cpu;
        !            72: } SLAVIO_CPUINTCTLState;
        !            73: 
1.1       root       74: #define INTCTL_MAXADDR 0xf
1.1.1.4   root       75: #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
1.1.1.5 ! root       76: #define INTCTLM_SIZE 0x14
1.1.1.4   root       77: #define MASTER_IRQ_MASK ~0x0fa2007f
                     78: #define MASTER_DISABLE 0x80000000
                     79: #define CPU_SOFTIRQ_MASK 0xfffe0000
                     80: #define CPU_HARDIRQ_MASK 0x0000fffe
                     81: #define CPU_IRQ_INT15_IN 0x0004000
                     82: #define CPU_IRQ_INT15_MASK 0x80000000
                     83: 
1.1.1.5 ! root       84: static void slavio_check_interrupts(SLAVIO_INTCTLState *s);
1.1       root       85: 
                     86: // per-cpu interrupt controller
                     87: static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
                     88: {
1.1.1.5 ! root       89:     SLAVIO_CPUINTCTLState *s = opaque;
1.1.1.4   root       90:     uint32_t saddr, ret;
1.1       root       91: 
1.1.1.5 ! root       92:     saddr = addr >> 2;
1.1       root       93:     switch (saddr) {
                     94:     case 0:
1.1.1.5 ! root       95:         ret = s->intreg_pending;
1.1.1.4   root       96:         break;
1.1       root       97:     default:
1.1.1.4   root       98:         ret = 0;
                     99:         break;
1.1       root      100:     }
1.1.1.5 ! root      101:     DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
1.1.1.4   root      102: 
                    103:     return ret;
1.1       root      104: }
                    105: 
1.1.1.5 ! root      106: static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
        !           107:                                      uint32_t val)
1.1       root      108: {
1.1.1.5 ! root      109:     SLAVIO_CPUINTCTLState *s = opaque;
1.1       root      110:     uint32_t saddr;
                    111: 
1.1.1.5 ! root      112:     saddr = addr >> 2;
        !           113:     DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
1.1       root      114:     switch (saddr) {
                    115:     case 1: // clear pending softints
1.1.1.4   root      116:         if (val & CPU_IRQ_INT15_IN)
                    117:             val |= CPU_IRQ_INT15_MASK;
                    118:         val &= CPU_SOFTIRQ_MASK;
1.1.1.5 ! root      119:         s->intreg_pending &= ~val;
        !           120:         slavio_check_interrupts(s->master);
        !           121:         DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
        !           122:                 s->intreg_pending);
1.1.1.4   root      123:         break;
1.1       root      124:     case 2: // set softint
1.1.1.4   root      125:         val &= CPU_SOFTIRQ_MASK;
1.1.1.5 ! root      126:         s->intreg_pending |= val;
        !           127:         slavio_check_interrupts(s->master);
        !           128:         DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
        !           129:                 s->intreg_pending);
1.1.1.4   root      130:         break;
1.1       root      131:     default:
1.1.1.4   root      132:         break;
1.1       root      133:     }
                    134: }
                    135: 
                    136: static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
1.1.1.4   root      137:     NULL,
                    138:     NULL,
1.1       root      139:     slavio_intctl_mem_readl,
                    140: };
                    141: 
                    142: static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
1.1.1.4   root      143:     NULL,
                    144:     NULL,
1.1       root      145:     slavio_intctl_mem_writel,
                    146: };
                    147: 
                    148: // master system interrupt controller
                    149: static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
                    150: {
                    151:     SLAVIO_INTCTLState *s = opaque;
1.1.1.4   root      152:     uint32_t saddr, ret;
1.1       root      153: 
1.1.1.5 ! root      154:     saddr = addr >> 2;
1.1       root      155:     switch (saddr) {
                    156:     case 0:
1.1.1.4   root      157:         ret = s->intregm_pending & ~MASTER_DISABLE;
                    158:         break;
1.1       root      159:     case 1:
1.1.1.4   root      160:         ret = s->intregm_disabled & MASTER_IRQ_MASK;
                    161:         break;
1.1       root      162:     case 4:
1.1.1.4   root      163:         ret = s->target_cpu;
                    164:         break;
1.1       root      165:     default:
1.1.1.4   root      166:         ret = 0;
                    167:         break;
1.1       root      168:     }
1.1.1.4   root      169:     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
                    170: 
                    171:     return ret;
1.1       root      172: }
                    173: 
1.1.1.5 ! root      174: static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
        !           175:                                       uint32_t val)
1.1       root      176: {
                    177:     SLAVIO_INTCTLState *s = opaque;
                    178:     uint32_t saddr;
                    179: 
1.1.1.5 ! root      180:     saddr = addr >> 2;
1.1.1.4   root      181:     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
1.1       root      182:     switch (saddr) {
                    183:     case 2: // clear (enable)
1.1.1.4   root      184:         // Force clear unused bits
                    185:         val &= MASTER_IRQ_MASK;
                    186:         s->intregm_disabled &= ~val;
1.1.1.5 ! root      187:         DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
        !           188:                 s->intregm_disabled);
1.1.1.4   root      189:         slavio_check_interrupts(s);
                    190:         break;
1.1       root      191:     case 3: // set (disable, clear pending)
1.1.1.4   root      192:         // Force clear unused bits
                    193:         val &= MASTER_IRQ_MASK;
                    194:         s->intregm_disabled |= val;
                    195:         s->intregm_pending &= ~val;
                    196:         slavio_check_interrupts(s);
1.1.1.5 ! root      197:         DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
        !           198:                 s->intregm_disabled);
1.1.1.4   root      199:         break;
1.1       root      200:     case 4:
1.1.1.4   root      201:         s->target_cpu = val & (MAX_CPUS - 1);
                    202:         slavio_check_interrupts(s);
                    203:         DPRINTF("Set master irq cpu %d\n", s->target_cpu);
                    204:         break;
1.1       root      205:     default:
1.1.1.4   root      206:         break;
1.1       root      207:     }
                    208: }
                    209: 
                    210: static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
1.1.1.4   root      211:     NULL,
                    212:     NULL,
1.1       root      213:     slavio_intctlm_mem_readl,
                    214: };
                    215: 
                    216: static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
1.1.1.4   root      217:     NULL,
                    218:     NULL,
1.1       root      219:     slavio_intctlm_mem_writel,
                    220: };
                    221: 
                    222: void slavio_pic_info(void *opaque)
                    223: {
                    224:     SLAVIO_INTCTLState *s = opaque;
                    225:     int i;
                    226: 
                    227:     for (i = 0; i < MAX_CPUS; i++) {
1.1.1.5 ! root      228:         term_printf("per-cpu %d: pending 0x%08x\n", i,
        !           229:                     s->slaves[i]->intreg_pending);
1.1       root      230:     }
1.1.1.5 ! root      231:     term_printf("master: pending 0x%08x, disabled 0x%08x\n",
        !           232:                 s->intregm_pending, s->intregm_disabled);
1.1       root      233: }
                    234: 
                    235: void slavio_irq_info(void *opaque)
                    236: {
                    237: #ifndef DEBUG_IRQ_COUNT
                    238:     term_printf("irq statistic code not compiled.\n");
                    239: #else
                    240:     SLAVIO_INTCTLState *s = opaque;
                    241:     int i;
                    242:     int64_t count;
                    243: 
                    244:     term_printf("IRQ statistics:\n");
                    245:     for (i = 0; i < 32; i++) {
                    246:         count = s->irq_count[i];
                    247:         if (count > 0)
1.1.1.3   root      248:             term_printf("%2d: %" PRId64 "\n", i, count);
1.1       root      249:     }
                    250: #endif
                    251: }
                    252: 
1.1.1.5 ! root      253: static void slavio_check_interrupts(SLAVIO_INTCTLState *s)
1.1       root      254: {
1.1.1.4   root      255:     uint32_t pending = s->intregm_pending, pil_pending;
                    256:     unsigned int i, j;
1.1       root      257: 
                    258:     pending &= ~s->intregm_disabled;
                    259: 
1.1.1.4   root      260:     DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
1.1.1.2   root      261:     for (i = 0; i < MAX_CPUS; i++) {
1.1.1.4   root      262:         pil_pending = 0;
                    263:         if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
                    264:             (i == s->target_cpu)) {
                    265:             for (j = 0; j < 32; j++) {
                    266:                 if (pending & (1 << j))
                    267:                     pil_pending |= 1 << s->intbit_to_level[j];
1.1.1.2   root      268:             }
                    269:         }
1.1.1.5 ! root      270:         pil_pending |= (s->slaves[i]->intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
1.1.1.4   root      271: 
                    272:         for (j = 0; j < MAX_PILS; j++) {
                    273:             if (pil_pending & (1 << j)) {
                    274:                 if (!(s->pil_out[i] & (1 << j)))
                    275:                     qemu_irq_raise(s->cpu_irqs[i][j]);
                    276:             } else {
                    277:                 if (s->pil_out[i] & (1 << j))
                    278:                     qemu_irq_lower(s->cpu_irqs[i][j]);
1.1.1.2   root      279:             }
                    280:         }
1.1.1.4   root      281:         s->pil_out[i] = pil_pending;
1.1.1.2   root      282:     }
1.1       root      283: }
                    284: 
                    285: /*
                    286:  * "irq" here is the bit number in the system interrupt register to
                    287:  * separate serial and keyboard interrupts sharing a level.
                    288:  */
1.1.1.4   root      289: static void slavio_set_irq(void *opaque, int irq, int level)
1.1       root      290: {
                    291:     SLAVIO_INTCTLState *s = opaque;
1.1.1.4   root      292:     uint32_t mask = 1 << irq;
                    293:     uint32_t pil = s->intbit_to_level[irq];
1.1       root      294: 
1.1.1.4   root      295:     DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
                    296:             level);
                    297:     if (pil > 0) {
                    298:         if (level) {
                    299: #ifdef DEBUG_IRQ_COUNT
                    300:             s->irq_count[pil]++;
                    301: #endif
                    302:             s->intregm_pending |= mask;
1.1.1.5 ! root      303:             s->slaves[s->target_cpu]->intreg_pending |= 1 << pil;
1.1.1.4   root      304:         } else {
                    305:             s->intregm_pending &= ~mask;
1.1.1.5 ! root      306:             s->slaves[s->target_cpu]->intreg_pending &= ~(1 << pil);
1.1.1.4   root      307:         }
                    308:         slavio_check_interrupts(s);
1.1       root      309:     }
                    310: }
                    311: 
1.1.1.4   root      312: static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
1.1.1.2   root      313: {
                    314:     SLAVIO_INTCTLState *s = opaque;
                    315: 
1.1.1.4   root      316:     DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
                    317: 
                    318:     if (level) {
                    319:         s->intregm_pending |= s->cputimer_mbit;
1.1.1.5 ! root      320:         s->slaves[cpu]->intreg_pending |= s->cputimer_lbit;
1.1.1.4   root      321:     } else {
                    322:         s->intregm_pending &= ~s->cputimer_mbit;
1.1.1.5 ! root      323:         s->slaves[cpu]->intreg_pending &= ~s->cputimer_lbit;
1.1.1.2   root      324:     }
1.1.1.4   root      325: 
1.1.1.2   root      326:     slavio_check_interrupts(s);
                    327: }
                    328: 
1.1       root      329: static void slavio_intctl_save(QEMUFile *f, void *opaque)
                    330: {
                    331:     SLAVIO_INTCTLState *s = opaque;
                    332:     int i;
1.1.1.4   root      333: 
1.1       root      334:     for (i = 0; i < MAX_CPUS; i++) {
1.1.1.5 ! root      335:         qemu_put_be32s(f, &s->slaves[i]->intreg_pending);
1.1       root      336:     }
                    337:     qemu_put_be32s(f, &s->intregm_pending);
                    338:     qemu_put_be32s(f, &s->intregm_disabled);
                    339:     qemu_put_be32s(f, &s->target_cpu);
                    340: }
                    341: 
                    342: static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
                    343: {
                    344:     SLAVIO_INTCTLState *s = opaque;
                    345:     int i;
                    346: 
                    347:     if (version_id != 1)
                    348:         return -EINVAL;
                    349: 
                    350:     for (i = 0; i < MAX_CPUS; i++) {
1.1.1.5 ! root      351:         qemu_get_be32s(f, &s->slaves[i]->intreg_pending);
1.1       root      352:     }
                    353:     qemu_get_be32s(f, &s->intregm_pending);
                    354:     qemu_get_be32s(f, &s->intregm_disabled);
                    355:     qemu_get_be32s(f, &s->target_cpu);
1.1.1.4   root      356:     slavio_check_interrupts(s);
1.1       root      357:     return 0;
                    358: }
                    359: 
                    360: static void slavio_intctl_reset(void *opaque)
                    361: {
                    362:     SLAVIO_INTCTLState *s = opaque;
                    363:     int i;
                    364: 
                    365:     for (i = 0; i < MAX_CPUS; i++) {
1.1.1.5 ! root      366:         s->slaves[i]->intreg_pending = 0;
1.1       root      367:     }
1.1.1.4   root      368:     s->intregm_disabled = ~MASTER_IRQ_MASK;
1.1       root      369:     s->intregm_pending = 0;
                    370:     s->target_cpu = 0;
1.1.1.4   root      371:     slavio_check_interrupts(s);
1.1       root      372: }
                    373: 
1.1.1.4   root      374: void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
                    375:                          const uint32_t *intbit_to_level,
                    376:                          qemu_irq **irq, qemu_irq **cpu_irq,
                    377:                          qemu_irq **parent_irq, unsigned int cputimer)
1.1       root      378: {
                    379:     int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
                    380:     SLAVIO_INTCTLState *s;
1.1.1.5 ! root      381:     SLAVIO_CPUINTCTLState *slave;
1.1       root      382: 
                    383:     s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
                    384: 
1.1.1.4   root      385:     s->intbit_to_level = intbit_to_level;
1.1       root      386:     for (i = 0; i < MAX_CPUS; i++) {
1.1.1.5 ! root      387:         slave = qemu_mallocz(sizeof(SLAVIO_CPUINTCTLState));
        !           388: 
        !           389:         slave->cpu = i;
        !           390:         slave->master = s;
        !           391: 
        !           392:         slavio_intctl_io_memory = cpu_register_io_memory(0,
        !           393:                                                          slavio_intctl_mem_read,
        !           394:                                                          slavio_intctl_mem_write,
        !           395:                                                          slave);
1.1.1.4   root      396:         cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
                    397:                                      slavio_intctl_io_memory);
1.1.1.5 ! root      398: 
        !           399:         s->slaves[i] = slave;
1.1.1.4   root      400:         s->cpu_irqs[i] = parent_irq[i];
1.1       root      401:     }
                    402: 
1.1.1.5 ! root      403:     slavio_intctlm_io_memory = cpu_register_io_memory(0,
        !           404:                                                       slavio_intctlm_mem_read,
        !           405:                                                       slavio_intctlm_mem_write,
        !           406:                                                       s);
1.1.1.4   root      407:     cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
1.1       root      408: 
1.1.1.5 ! root      409:     register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
        !           410:                     slavio_intctl_load, s);
1.1       root      411:     qemu_register_reset(slavio_intctl_reset, s);
1.1.1.4   root      412:     *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
                    413: 
                    414:     *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
                    415:     s->cputimer_mbit = 1 << cputimer;
                    416:     s->cputimer_lbit = 1 << intbit_to_level[cputimer];
1.1       root      417:     slavio_intctl_reset(s);
                    418:     return s;
                    419: }

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