![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to slavio_timer.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / hw|
Return to slavio_timer.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu / hw |
1.1 root 1: /*
2: * QEMU Sparc SLAVIO timer controller emulation
3: *
4: * Copyright (c) 2003-2005 Fabrice Bellard
1.1.1.4 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.6 root 24:
1.1.1.4 root 25: #include "sun4m.h"
26: #include "qemu-timer.h"
1.1.1.6 root 27: #include "sysbus.h"
1.1 root 28:
29: //#define DEBUG_TIMER
30:
31: #ifdef DEBUG_TIMER
1.1.1.6 root 32: #define DPRINTF(fmt, ...) \
33: do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
1.1 root 34: #else
1.1.1.6 root 35: #define DPRINTF(fmt, ...) do {} while (0)
1.1 root 36: #endif
37:
38: /*
39: * Registers of hardware timer in sun4m.
40: *
41: * This is the timer/counter part of chip STP2001 (Slave I/O), also
42: * produced as NCR89C105. See
43: * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
1.1.1.4 root 44: *
1.1 root 45: * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
46: * are zero. Bit 31 is 1 when count has been reached.
47: *
1.1.1.2 root 48: * Per-CPU timers interrupt local CPU, system timer uses normal
49: * interrupt routing.
50: *
1.1 root 51: */
52:
1.1.1.4 root 53: #define MAX_CPUS 16
54:
1.1.1.7 root 55: typedef struct CPUTimerState {
1.1.1.4 root 56: qemu_irq irq;
57: ptimer_state *timer;
58: uint32_t count, counthigh, reached;
59: uint64_t limit;
60: // processor only
1.1.1.5 root 61: uint32_t running;
1.1.1.7 root 62: } CPUTimerState;
63:
64: typedef struct SLAVIO_TIMERState {
65: SysBusDevice busdev;
66: uint32_t num_cpus;
67: CPUTimerState cputimer[MAX_CPUS + 1];
68: uint32_t cputimer_mode;
1.1 root 69: } SLAVIO_TIMERState;
70:
1.1.1.7 root 71: typedef struct TimerContext {
72: SLAVIO_TIMERState *s;
73: unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
74: } TimerContext;
75:
1.1.1.4 root 76: #define SYS_TIMER_SIZE 0x14
77: #define CPU_TIMER_SIZE 0x10
78:
79: #define TIMER_LIMIT 0
80: #define TIMER_COUNTER 1
81: #define TIMER_COUNTER_NORST 2
82: #define TIMER_STATUS 3
83: #define TIMER_MODE 4
84:
85: #define TIMER_COUNT_MASK32 0xfffffe00
86: #define TIMER_LIMIT_MASK32 0x7fffffff
87: #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
88: #define TIMER_MAX_COUNT32 0x7ffffe00ULL
89: #define TIMER_REACHED 0x80000000
90: #define TIMER_PERIOD 500ULL // 500ns
1.1.1.8 ! root 91: #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
! 92: #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)
1.1.1.4 root 93:
1.1.1.7 root 94: static int slavio_timer_is_user(TimerContext *tc)
1.1.1.4 root 95: {
1.1.1.7 root 96: SLAVIO_TIMERState *s = tc->s;
97: unsigned int timer_index = tc->timer_index;
98:
99: return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
1.1.1.4 root 100: }
1.1 root 101:
102: // Update count, set irq, update expire_time
1.1.1.4 root 103: // Convert from ptimer countdown units
1.1.1.7 root 104: static void slavio_timer_get_out(CPUTimerState *t)
1.1 root 105: {
1.1.1.4 root 106: uint64_t count, limit;
1.1 root 107:
1.1.1.7 root 108: if (t->limit == 0) { /* free-run system or processor counter */
1.1.1.4 root 109: limit = TIMER_MAX_COUNT32;
1.1.1.7 root 110: } else {
111: limit = t->limit;
112: }
113: count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
1.1 root 114:
1.1.1.7 root 115: DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", t->limit, t->counthigh,
116: t->count);
117: t->count = count & TIMER_COUNT_MASK32;
118: t->counthigh = count >> 32;
1.1 root 119: }
120:
121: // timer callback
122: static void slavio_timer_irq(void *opaque)
123: {
1.1.1.7 root 124: TimerContext *tc = opaque;
125: SLAVIO_TIMERState *s = tc->s;
126: CPUTimerState *t = &s->cputimer[tc->timer_index];
127:
128: slavio_timer_get_out(t);
129: DPRINTF("callback: count %x%08x\n", t->counthigh, t->count);
1.1.1.8 ! root 130: /* if limit is 0 (free-run), there will be no match */
! 131: if (t->limit != 0) {
! 132: t->reached = TIMER_REACHED;
! 133: }
! 134: /* there is no interrupt if user timer or free-run */
! 135: if (!slavio_timer_is_user(tc) && t->limit != 0) {
1.1.1.7 root 136: qemu_irq_raise(t->irq);
137: }
1.1 root 138: }
139:
140: static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
141: {
1.1.1.7 root 142: TimerContext *tc = opaque;
143: SLAVIO_TIMERState *s = tc->s;
1.1.1.4 root 144: uint32_t saddr, ret;
1.1.1.7 root 145: unsigned int timer_index = tc->timer_index;
146: CPUTimerState *t = &s->cputimer[timer_index];
1.1 root 147:
1.1.1.5 root 148: saddr = addr >> 2;
1.1 root 149: switch (saddr) {
1.1.1.4 root 150: case TIMER_LIMIT:
151: // read limit (system counter mode) or read most signifying
152: // part of counter (user mode)
1.1.1.7 root 153: if (slavio_timer_is_user(tc)) {
1.1.1.4 root 154: // read user timer MSW
1.1.1.7 root 155: slavio_timer_get_out(t);
156: ret = t->counthigh | t->reached;
1.1.1.4 root 157: } else {
158: // read limit
159: // clear irq
1.1.1.7 root 160: qemu_irq_lower(t->irq);
161: t->reached = 0;
162: ret = t->limit & TIMER_LIMIT_MASK32;
1.1.1.4 root 163: }
164: break;
165: case TIMER_COUNTER:
166: // read counter and reached bit (system mode) or read lsbits
167: // of counter (user mode)
1.1.1.7 root 168: slavio_timer_get_out(t);
169: if (slavio_timer_is_user(tc)) { // read user timer LSW
170: ret = t->count & TIMER_MAX_COUNT64;
171: } else { // read limit
172: ret = (t->count & TIMER_MAX_COUNT32) |
173: t->reached;
174: }
1.1.1.4 root 175: break;
176: case TIMER_STATUS:
177: // only available in processor counter/timer
178: // read start/stop status
1.1.1.7 root 179: if (timer_index > 0) {
180: ret = t->running;
181: } else {
182: ret = 0;
183: }
1.1.1.4 root 184: break;
185: case TIMER_MODE:
186: // only available in system counter
187: // read user/system mode
1.1.1.7 root 188: ret = s->cputimer_mode;
1.1.1.4 root 189: break;
1.1 root 190: default:
1.1.1.4 root 191: DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
192: ret = 0;
193: break;
1.1 root 194: }
1.1.1.4 root 195: DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
196:
197: return ret;
1.1 root 198: }
199:
1.1.1.4 root 200: static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
201: uint32_t val)
1.1 root 202: {
1.1.1.7 root 203: TimerContext *tc = opaque;
204: SLAVIO_TIMERState *s = tc->s;
1.1 root 205: uint32_t saddr;
1.1.1.7 root 206: unsigned int timer_index = tc->timer_index;
207: CPUTimerState *t = &s->cputimer[timer_index];
1.1 root 208:
1.1.1.4 root 209: DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
1.1.1.5 root 210: saddr = addr >> 2;
1.1 root 211: switch (saddr) {
1.1.1.4 root 212: case TIMER_LIMIT:
1.1.1.7 root 213: if (slavio_timer_is_user(tc)) {
1.1.1.5 root 214: uint64_t count;
215:
1.1.1.4 root 216: // set user counter MSW, reset counter
1.1.1.7 root 217: t->limit = TIMER_MAX_COUNT64;
218: t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
219: t->reached = 0;
220: count = ((uint64_t)t->counthigh << 32) | t->count;
1.1.1.6 root 221: DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
1.1.1.7 root 222: timer_index, count);
223: ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
1.1.1.4 root 224: } else {
225: // set limit, reset counter
1.1.1.7 root 226: qemu_irq_lower(t->irq);
227: t->limit = val & TIMER_MAX_COUNT32;
228: if (t->timer) {
229: if (t->limit == 0) { /* free-run */
230: ptimer_set_limit(t->timer,
1.1.1.5 root 231: LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
1.1.1.7 root 232: } else {
233: ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
234: }
1.1.1.4 root 235: }
236: }
237: break;
238: case TIMER_COUNTER:
1.1.1.7 root 239: if (slavio_timer_is_user(tc)) {
1.1.1.5 root 240: uint64_t count;
241:
1.1.1.4 root 242: // set user counter LSW, reset counter
1.1.1.7 root 243: t->limit = TIMER_MAX_COUNT64;
244: t->count = val & TIMER_MAX_COUNT64;
245: t->reached = 0;
246: count = ((uint64_t)t->counthigh) << 32 | t->count;
1.1.1.6 root 247: DPRINTF("processor %d user timer set to %016" PRIx64 "\n",
1.1.1.7 root 248: timer_index, count);
249: ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
1.1.1.4 root 250: } else
251: DPRINTF("not user timer\n");
252: break;
253: case TIMER_COUNTER_NORST:
254: // set limit without resetting counter
1.1.1.7 root 255: t->limit = val & TIMER_MAX_COUNT32;
256: if (t->limit == 0) { /* free-run */
257: ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
258: } else {
259: ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
1.1.1.4 root 260: }
261: break;
262: case TIMER_STATUS:
1.1.1.7 root 263: if (slavio_timer_is_user(tc)) {
1.1.1.4 root 264: // start/stop user counter
1.1.1.7 root 265: if ((val & 1) && !t->running) {
266: DPRINTF("processor %d user timer started\n",
267: timer_index);
268: ptimer_run(t->timer, 0);
269: t->running = 1;
270: } else if (!(val & 1) && t->running) {
271: DPRINTF("processor %d user timer stopped\n",
272: timer_index);
273: ptimer_stop(t->timer);
274: t->running = 0;
1.1.1.4 root 275: }
276: }
277: break;
278: case TIMER_MODE:
1.1.1.7 root 279: if (timer_index == 0) {
1.1.1.4 root 280: unsigned int i;
281:
1.1.1.7 root 282: for (i = 0; i < s->num_cpus; i++) {
1.1.1.5 root 283: unsigned int processor = 1 << i;
1.1.1.7 root 284: CPUTimerState *curr_timer = &s->cputimer[i + 1];
1.1.1.5 root 285:
286: // check for a change in timer mode for this processor
1.1.1.7 root 287: if ((val & processor) != (s->cputimer_mode & processor)) {
1.1.1.5 root 288: if (val & processor) { // counter -> user timer
1.1.1.7 root 289: qemu_irq_lower(curr_timer->irq);
1.1.1.5 root 290: // counters are always running
1.1.1.7 root 291: ptimer_stop(curr_timer->timer);
292: curr_timer->running = 0;
1.1.1.5 root 293: // user timer limit is always the same
1.1.1.7 root 294: curr_timer->limit = TIMER_MAX_COUNT64;
295: ptimer_set_limit(curr_timer->timer,
296: LIMIT_TO_PERIODS(curr_timer->limit),
1.1.1.5 root 297: 1);
298: // set this processors user timer bit in config
299: // register
1.1.1.7 root 300: s->cputimer_mode |= processor;
1.1.1.5 root 301: DPRINTF("processor %d changed from counter to user "
1.1.1.7 root 302: "timer\n", timer_index);
1.1.1.5 root 303: } else { // user timer -> counter
304: // stop the user timer if it is running
1.1.1.7 root 305: if (curr_timer->running) {
306: ptimer_stop(curr_timer->timer);
307: }
1.1.1.5 root 308: // start the counter
1.1.1.7 root 309: ptimer_run(curr_timer->timer, 0);
310: curr_timer->running = 1;
1.1.1.5 root 311: // clear this processors user timer bit in config
312: // register
1.1.1.7 root 313: s->cputimer_mode &= ~processor;
1.1.1.5 root 314: DPRINTF("processor %d changed from user timer to "
1.1.1.7 root 315: "counter\n", timer_index);
1.1.1.5 root 316: }
1.1.1.4 root 317: }
318: }
1.1.1.7 root 319: } else {
1.1.1.4 root 320: DPRINTF("not system timer\n");
1.1.1.7 root 321: }
1.1.1.4 root 322: break;
1.1 root 323: default:
1.1.1.4 root 324: DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
325: break;
1.1 root 326: }
327: }
328:
1.1.1.7 root 329: static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = {
1.1.1.4 root 330: NULL,
331: NULL,
1.1 root 332: slavio_timer_mem_readl,
333: };
334:
1.1.1.7 root 335: static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = {
1.1.1.4 root 336: NULL,
337: NULL,
1.1 root 338: slavio_timer_mem_writel,
339: };
340:
1.1.1.7 root 341: static const VMStateDescription vmstate_timer = {
342: .name ="timer",
343: .version_id = 3,
344: .minimum_version_id = 3,
345: .minimum_version_id_old = 3,
346: .fields = (VMStateField []) {
347: VMSTATE_UINT64(limit, CPUTimerState),
348: VMSTATE_UINT32(count, CPUTimerState),
349: VMSTATE_UINT32(counthigh, CPUTimerState),
350: VMSTATE_UINT32(reached, CPUTimerState),
351: VMSTATE_UINT32(running, CPUTimerState),
352: VMSTATE_PTIMER(timer, CPUTimerState),
353: VMSTATE_END_OF_LIST()
354: }
355: };
1.1 root 356:
1.1.1.7 root 357: static const VMStateDescription vmstate_slavio_timer = {
358: .name ="slavio_timer",
359: .version_id = 3,
360: .minimum_version_id = 3,
361: .minimum_version_id_old = 3,
362: .fields = (VMStateField []) {
363: VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
364: vmstate_timer, CPUTimerState),
365: VMSTATE_END_OF_LIST()
1.1.1.4 root 366: }
1.1.1.7 root 367: };
1.1 root 368:
1.1.1.7 root 369: static void slavio_timer_reset(DeviceState *d)
1.1.1.6 root 370: {
1.1.1.7 root 371: SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev);
372: unsigned int i;
373: CPUTimerState *curr_timer;
1.1.1.6 root 374:
1.1.1.7 root 375: for (i = 0; i <= MAX_CPUS; i++) {
376: curr_timer = &s->cputimer[i];
377: curr_timer->limit = 0;
378: curr_timer->count = 0;
379: curr_timer->reached = 0;
1.1.1.8 ! root 380: if (i <= s->num_cpus) {
1.1.1.7 root 381: ptimer_set_limit(curr_timer->timer,
382: LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
383: ptimer_run(curr_timer->timer, 0);
1.1.1.8 ! root 384: curr_timer->running = 1;
1.1.1.7 root 385: }
386: }
387: s->cputimer_mode = 0;
1.1.1.6 root 388: }
389:
1.1.1.7 root 390: static int slavio_timer_init1(SysBusDevice *dev)
1.1 root 391: {
1.1.1.6 root 392: int io;
393: SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
1.1.1.4 root 394: QEMUBH *bh;
395: unsigned int i;
1.1.1.7 root 396: TimerContext *tc;
1.1.1.4 root 397:
1.1.1.7 root 398: for (i = 0; i <= MAX_CPUS; i++) {
399: tc = qemu_mallocz(sizeof(TimerContext));
400: tc->s = s;
401: tc->timer_index = i;
402:
403: bh = qemu_bh_new(slavio_timer_irq, tc);
404: s->cputimer[i].timer = ptimer_init(bh);
405: ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
406:
407: io = cpu_register_io_memory(slavio_timer_mem_read,
408: slavio_timer_mem_write, tc);
409: if (i == 0) {
410: sysbus_init_mmio(dev, SYS_TIMER_SIZE, io);
411: } else {
412: sysbus_init_mmio(dev, CPU_TIMER_SIZE, io);
413: }
1.1.1.4 root 414:
1.1.1.7 root 415: sysbus_init_irq(dev, &s->cputimer[i].irq);
1.1.1.6 root 416: }
1.1.1.7 root 417:
418: return 0;
1.1.1.6 root 419: }
420:
421: static SysBusDeviceInfo slavio_timer_info = {
422: .init = slavio_timer_init1,
423: .qdev.name = "slavio_timer",
424: .qdev.size = sizeof(SLAVIO_TIMERState),
1.1.1.7 root 425: .qdev.vmsd = &vmstate_slavio_timer,
426: .qdev.reset = slavio_timer_reset,
1.1.1.6 root 427: .qdev.props = (Property[]) {
1.1.1.7 root 428: DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0),
429: DEFINE_PROP_END_OF_LIST(),
1.1.1.4 root 430: }
1.1.1.6 root 431: };
432:
433: static void slavio_timer_register_devices(void)
434: {
435: sysbus_register_withprop(&slavio_timer_info);
1.1 root 436: }
1.1.1.6 root 437:
438: device_init(slavio_timer_register_devices)
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.