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1.1 root 1: /*
2: * QEMU Sparc Sun4c interrupt controller emulation
3: *
4: * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.4 root 24:
1.1 root 25: #include "hw.h"
26: #include "sun4m.h"
1.1.1.3 root 27: #include "monitor.h"
1.1.1.4 root 28: #include "sysbus.h"
29:
1.1 root 30: //#define DEBUG_IRQ_COUNT
31: //#define DEBUG_IRQ
32:
33: #ifdef DEBUG_IRQ
1.1.1.3 root 34: #define DPRINTF(fmt, ...) \
35: do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
1.1 root 36: #else
1.1.1.3 root 37: #define DPRINTF(fmt, ...)
1.1 root 38: #endif
39:
40: /*
41: * Registers of interrupt controller in sun4c.
42: *
43: */
44:
45: #define MAX_PILS 16
46:
47: typedef struct Sun4c_INTCTLState {
1.1.1.4 root 48: SysBusDevice busdev;
1.1 root 49: #ifdef DEBUG_IRQ_COUNT
50: uint64_t irq_count;
51: #endif
1.1.1.4 root 52: qemu_irq cpu_irqs[MAX_PILS];
1.1 root 53: const uint32_t *intbit_to_level;
54: uint32_t pil_out;
55: uint8_t reg;
56: uint8_t pending;
57: } Sun4c_INTCTLState;
58:
1.1.1.2 root 59: #define INTCTL_SIZE 1
1.1 root 60:
61: static void sun4c_check_interrupts(void *opaque);
62:
63: static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
64: {
65: Sun4c_INTCTLState *s = opaque;
66: uint32_t ret;
67:
68: ret = s->reg;
69: DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
70:
71: return ret;
72: }
73:
1.1.1.2 root 74: static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr,
75: uint32_t val)
1.1 root 76: {
77: Sun4c_INTCTLState *s = opaque;
78:
79: DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
80: val &= 0xbf;
81: s->reg = val;
82: sun4c_check_interrupts(s);
83: }
84:
1.1.1.4 root 85: static CPUReadMemoryFunc * const sun4c_intctl_mem_read[3] = {
1.1 root 86: sun4c_intctl_mem_readb,
87: NULL,
88: NULL,
89: };
90:
1.1.1.4 root 91: static CPUWriteMemoryFunc * const sun4c_intctl_mem_write[3] = {
1.1 root 92: sun4c_intctl_mem_writeb,
93: NULL,
94: NULL,
95: };
96:
1.1.1.3 root 97: void sun4c_pic_info(Monitor *mon, void *opaque)
1.1 root 98: {
99: Sun4c_INTCTLState *s = opaque;
100:
1.1.1.3 root 101: monitor_printf(mon, "master: pending 0x%2.2x, enabled 0x%2.2x\n",
102: s->pending, s->reg);
1.1 root 103: }
104:
1.1.1.3 root 105: void sun4c_irq_info(Monitor *mon, void *opaque)
1.1 root 106: {
107: #ifndef DEBUG_IRQ_COUNT
1.1.1.3 root 108: monitor_printf(mon, "irq statistic code not compiled.\n");
1.1 root 109: #else
110: Sun4c_INTCTLState *s = opaque;
111: int64_t count;
112:
1.1.1.3 root 113: monitor_printf(mon, "IRQ statistics:\n");
114: count = s->irq_count;
1.1 root 115: if (count > 0)
1.1.1.3 root 116: monitor_printf(mon, " %" PRId64 "\n", count);
1.1 root 117: #endif
118: }
119:
120: static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
121:
122: static void sun4c_check_interrupts(void *opaque)
123: {
124: Sun4c_INTCTLState *s = opaque;
125: uint32_t pil_pending;
126: unsigned int i;
127:
128: pil_pending = 0;
129: if (s->pending && !(s->reg & 0x80000000)) {
130: for (i = 0; i < 8; i++) {
131: if (s->pending & (1 << i))
132: pil_pending |= 1 << intbit_to_level[i];
133: }
134: }
135:
136: for (i = 0; i < MAX_PILS; i++) {
137: if (pil_pending & (1 << i)) {
138: if (!(s->pil_out & (1 << i)))
139: qemu_irq_raise(s->cpu_irqs[i]);
140: } else {
141: if (s->pil_out & (1 << i))
142: qemu_irq_lower(s->cpu_irqs[i]);
143: }
144: }
145: s->pil_out = pil_pending;
146: }
147:
148: /*
149: * "irq" here is the bit number in the system interrupt register
150: */
151: static void sun4c_set_irq(void *opaque, int irq, int level)
152: {
153: Sun4c_INTCTLState *s = opaque;
154: uint32_t mask = 1 << irq;
155: uint32_t pil = intbit_to_level[irq];
156:
157: DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
158: level);
159: if (pil > 0) {
160: if (level) {
161: #ifdef DEBUG_IRQ_COUNT
1.1.1.3 root 162: s->irq_count++;
1.1 root 163: #endif
164: s->pending |= mask;
165: } else {
166: s->pending &= ~mask;
167: }
168: sun4c_check_interrupts(s);
169: }
170: }
171:
1.1.1.4 root 172: static const VMStateDescription vmstate_sun4c_intctl = {
173: .name ="sun4c_intctl",
174: .version_id = 1,
175: .minimum_version_id = 1,
176: .minimum_version_id_old = 1,
177: .fields = (VMStateField []) {
178: VMSTATE_UINT8(reg, Sun4c_INTCTLState),
179: VMSTATE_UINT8(pending, Sun4c_INTCTLState),
180: VMSTATE_END_OF_LIST()
181: }
182: };
1.1 root 183:
1.1.1.4 root 184: static void sun4c_intctl_reset(DeviceState *d)
1.1 root 185: {
1.1.1.4 root 186: Sun4c_INTCTLState *s = container_of(d, Sun4c_INTCTLState, busdev.qdev);
1.1 root 187:
188: s->reg = 1;
189: s->pending = 0;
190: }
191:
1.1.1.4 root 192: static int sun4c_intctl_init1(SysBusDevice *dev)
1.1 root 193: {
1.1.1.4 root 194: Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);
195: int io_memory;
196: unsigned int i;
1.1 root 197:
1.1.1.4 root 198: io_memory = cpu_register_io_memory(sun4c_intctl_mem_read,
1.1.1.5 ! root 199: sun4c_intctl_mem_write, s,
! 200: DEVICE_NATIVE_ENDIAN);
1.1.1.4 root 201: sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
202: qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
1.1 root 203:
1.1.1.4 root 204: for (i = 0; i < MAX_PILS; i++) {
205: sysbus_init_irq(dev, &s->cpu_irqs[i]);
206: }
1.1 root 207:
1.1.1.4 root 208: return 0;
209: }
1.1 root 210:
1.1.1.4 root 211: static SysBusDeviceInfo sun4c_intctl_info = {
212: .init = sun4c_intctl_init1,
213: .qdev.name = "sun4c_intctl",
214: .qdev.size = sizeof(Sun4c_INTCTLState),
215: .qdev.vmsd = &vmstate_sun4c_intctl,
216: .qdev.reset = sun4c_intctl_reset,
217: };
1.1 root 218:
1.1.1.4 root 219: static void sun4c_intctl_register_devices(void)
220: {
221: sysbus_register_withprop(&sun4c_intctl_info);
1.1 root 222: }
1.1.1.4 root 223:
224: device_init(sun4c_intctl_register_devices)
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