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Annotation of qemu/hw/sun4m.c, revision 1.1

1.1     ! root        1: /*
        !             2:  * QEMU Sun4m System Emulator
        !             3:  * 
        !             4:  * Copyright (c) 2003-2005 Fabrice Bellard
        !             5:  * 
        !             6:  * Permission is hereby granted, free of charge, to any person obtaining a copy
        !             7:  * of this software and associated documentation files (the "Software"), to deal
        !             8:  * in the Software without restriction, including without limitation the rights
        !             9:  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
        !            10:  * copies of the Software, and to permit persons to whom the Software is
        !            11:  * furnished to do so, subject to the following conditions:
        !            12:  *
        !            13:  * The above copyright notice and this permission notice shall be included in
        !            14:  * all copies or substantial portions of the Software.
        !            15:  *
        !            16:  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
        !            17:  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
        !            18:  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
        !            19:  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
        !            20:  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
        !            21:  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
        !            22:  * THE SOFTWARE.
        !            23:  */
        !            24: #include "vl.h"
        !            25: #include "m48t08.h"
        !            26: 
        !            27: #define KERNEL_LOAD_ADDR     0x00004000
        !            28: #define CMDLINE_ADDR         0x007ff000
        !            29: #define INITRD_LOAD_ADDR     0x00800000
        !            30: #define PROM_ADDR           0xffd00000
        !            31: #define PROM_FILENAMEB      "proll.bin"
        !            32: #define PROM_FILENAMEE      "proll.elf"
        !            33: #define PHYS_JJ_EEPROM 0x71200000      /* m48t08 */
        !            34: #define PHYS_JJ_IDPROM_OFF     0x1FD8
        !            35: #define PHYS_JJ_EEPROM_SIZE    0x2000
        !            36: // IRQs are not PIL ones, but master interrupt controller register
        !            37: // bits
        !            38: #define PHYS_JJ_IOMMU  0x10000000      /* I/O MMU */
        !            39: #define PHYS_JJ_TCX_FB 0x50000000      /* TCX frame buffer */
        !            40: #define PHYS_JJ_SLAVIO 0x70000000      /* Slavio base */
        !            41: #define PHYS_JJ_ESPDMA  0x78400000      /* ESP DMA controller */
        !            42: #define PHYS_JJ_ESP     0x78800000      /* ESP SCSI */
        !            43: #define PHYS_JJ_ESP_IRQ    18
        !            44: #define PHYS_JJ_LEDMA   0x78400010      /* Lance DMA controller */
        !            45: #define PHYS_JJ_LE      0x78C00000      /* Lance ethernet */
        !            46: #define PHYS_JJ_LE_IRQ     16
        !            47: #define PHYS_JJ_CLOCK  0x71D00000      /* Per-CPU timer/counter, L14 */
        !            48: #define PHYS_JJ_CLOCK_IRQ  7
        !            49: #define PHYS_JJ_CLOCK1 0x71D10000      /* System timer/counter, L10 */
        !            50: #define PHYS_JJ_CLOCK1_IRQ 19
        !            51: #define PHYS_JJ_INTR0  0x71E00000      /* Per-CPU interrupt control registers */
        !            52: #define PHYS_JJ_INTR_G 0x71E10000      /* Master interrupt control registers */
        !            53: #define PHYS_JJ_MS_KBD 0x71000000      /* Mouse and keyboard */
        !            54: #define PHYS_JJ_MS_KBD_IRQ    14
        !            55: #define PHYS_JJ_SER    0x71100000      /* Serial */
        !            56: #define PHYS_JJ_SER_IRQ    15
        !            57: #define PHYS_JJ_FDC    0x71400000      /* Floppy */
        !            58: #define PHYS_JJ_FLOPPY_IRQ 22
        !            59: #define PHYS_JJ_ME_IRQ 30              /* Module error, power fail */
        !            60: 
        !            61: /* TSC handling */
        !            62: 
        !            63: uint64_t cpu_get_tsc()
        !            64: {
        !            65:     return qemu_get_clock(vm_clock);
        !            66: }
        !            67: 
        !            68: int DMA_get_channel_mode (int nchan)
        !            69: {
        !            70:     return 0;
        !            71: }
        !            72: int DMA_read_memory (int nchan, void *buf, int pos, int size)
        !            73: {
        !            74:     return 0;
        !            75: }
        !            76: int DMA_write_memory (int nchan, void *buf, int pos, int size)
        !            77: {
        !            78:     return 0;
        !            79: }
        !            80: void DMA_hold_DREQ (int nchan) {}
        !            81: void DMA_release_DREQ (int nchan) {}
        !            82: void DMA_schedule(int nchan) {}
        !            83: void DMA_run (void) {}
        !            84: void DMA_init (int high_page_enable) {}
        !            85: void DMA_register_channel (int nchan,
        !            86:                            DMA_transfer_handler transfer_handler,
        !            87:                            void *opaque)
        !            88: {
        !            89: }
        !            90: 
        !            91: static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value)
        !            92: {
        !            93:     m48t08_write(nvram, addr++, (value >> 8) & 0xff);
        !            94:     m48t08_write(nvram, addr++, value & 0xff);
        !            95: }
        !            96: 
        !            97: static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value)
        !            98: {
        !            99:     m48t08_write(nvram, addr++, value >> 24);
        !           100:     m48t08_write(nvram, addr++, (value >> 16) & 0xff);
        !           101:     m48t08_write(nvram, addr++, (value >> 8) & 0xff);
        !           102:     m48t08_write(nvram, addr++, value & 0xff);
        !           103: }
        !           104: 
        !           105: static void nvram_set_string (m48t08_t *nvram, uint32_t addr,
        !           106:                        const unsigned char *str, uint32_t max)
        !           107: {
        !           108:     unsigned int i;
        !           109: 
        !           110:     for (i = 0; i < max && str[i] != '\0'; i++) {
        !           111:         m48t08_write(nvram, addr + i, str[i]);
        !           112:     }
        !           113:     m48t08_write(nvram, addr + max - 1, '\0');
        !           114: }
        !           115: 
        !           116: static m48t08_t *nvram;
        !           117: 
        !           118: extern int nographic;
        !           119: 
        !           120: static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline,
        !           121:                       int boot_device, uint32_t RAM_size,
        !           122:                       uint32_t kernel_size,
        !           123:                       int width, int height, int depth)
        !           124: {
        !           125:     unsigned char tmp = 0;
        !           126:     int i, j;
        !           127: 
        !           128:     // Try to match PPC NVRAM
        !           129:     nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
        !           130:     nvram_set_lword(nvram,  0x10, 0x00000001); /* structure v1 */
        !           131:     // NVRAM_size, arch not applicable
        !           132:     m48t08_write(nvram, 0x2F, nographic & 0xff);
        !           133:     nvram_set_lword(nvram,  0x30, RAM_size);
        !           134:     m48t08_write(nvram, 0x34, boot_device & 0xff);
        !           135:     nvram_set_lword(nvram,  0x38, KERNEL_LOAD_ADDR);
        !           136:     nvram_set_lword(nvram,  0x3C, kernel_size);
        !           137:     if (cmdline) {
        !           138:        strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
        !           139:        nvram_set_lword(nvram,  0x40, CMDLINE_ADDR);
        !           140:         nvram_set_lword(nvram,  0x44, strlen(cmdline));
        !           141:     }
        !           142:     // initrd_image, initrd_size passed differently
        !           143:     nvram_set_word(nvram,   0x54, width);
        !           144:     nvram_set_word(nvram,   0x56, height);
        !           145:     nvram_set_word(nvram,   0x58, depth);
        !           146: 
        !           147:     // Sun4m specific use
        !           148:     i = 0x1fd8;
        !           149:     m48t08_write(nvram, i++, 0x01);
        !           150:     m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */
        !           151:     j = 0;
        !           152:     m48t08_write(nvram, i++, macaddr[j++]);
        !           153:     m48t08_write(nvram, i++, macaddr[j++]);
        !           154:     m48t08_write(nvram, i++, macaddr[j++]);
        !           155:     m48t08_write(nvram, i++, macaddr[j++]);
        !           156:     m48t08_write(nvram, i++, macaddr[j++]);
        !           157:     m48t08_write(nvram, i, macaddr[j]);
        !           158: 
        !           159:     /* Calculate checksum */
        !           160:     for (i = 0x1fd8; i < 0x1fe7; i++) {
        !           161:        tmp ^= m48t08_read(nvram, i);
        !           162:     }
        !           163:     m48t08_write(nvram, 0x1fe7, tmp);
        !           164: }
        !           165: 
        !           166: static void *slavio_intctl;
        !           167: 
        !           168: void pic_info()
        !           169: {
        !           170:     slavio_pic_info(slavio_intctl);
        !           171: }
        !           172: 
        !           173: void irq_info()
        !           174: {
        !           175:     slavio_irq_info(slavio_intctl);
        !           176: }
        !           177: 
        !           178: void pic_set_irq(int irq, int level)
        !           179: {
        !           180:     slavio_pic_set_irq(slavio_intctl, irq, level);
        !           181: }
        !           182: 
        !           183: static void *tcx;
        !           184: 
        !           185: void vga_update_display()
        !           186: {
        !           187:     tcx_update_display(tcx);
        !           188: }
        !           189: 
        !           190: void vga_invalidate_display()
        !           191: {
        !           192:     tcx_invalidate_display(tcx);
        !           193: }
        !           194: 
        !           195: void vga_screen_dump(const char *filename)
        !           196: {
        !           197:     tcx_screen_dump(tcx, filename);
        !           198: }
        !           199: 
        !           200: static void *iommu;
        !           201: 
        !           202: uint32_t iommu_translate(uint32_t addr)
        !           203: {
        !           204:     return iommu_translate_local(iommu, addr);
        !           205: }
        !           206: 
        !           207: static void *slavio_misc;
        !           208: 
        !           209: void qemu_system_powerdown(void)
        !           210: {
        !           211:     slavio_set_power_fail(slavio_misc, 1);
        !           212: }
        !           213: 
        !           214: /* Sun4m hardware initialisation */
        !           215: static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
        !           216:                        DisplayState *ds, const char **fd_filename, int snapshot,
        !           217:                        const char *kernel_filename, const char *kernel_cmdline,
        !           218:                        const char *initrd_filename)
        !           219: {
        !           220:     char buf[1024];
        !           221:     int ret, linux_boot;
        !           222:     unsigned int i;
        !           223:     long vram_size = 0x100000, prom_offset, initrd_size, kernel_size;
        !           224: 
        !           225:     linux_boot = (kernel_filename != NULL);
        !           226: 
        !           227:     /* allocate RAM */
        !           228:     cpu_register_physical_memory(0, ram_size, 0);
        !           229: 
        !           230:     iommu = iommu_init(PHYS_JJ_IOMMU);
        !           231:     slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
        !           232:     tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
        !           233:     lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
        !           234:     nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE);
        !           235:     slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ);
        !           236:     slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
        !           237:     // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
        !           238:     // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
        !           239:     slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]);
        !           240:     fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
        !           241:     esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA);
        !           242:     slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ);
        !           243: 
        !           244:     prom_offset = ram_size + vram_size;
        !           245: 
        !           246:     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);
        !           247:     ret = load_elf(buf, phys_ram_base + prom_offset);
        !           248:     if (ret < 0) {
        !           249:        snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
        !           250:        ret = load_image(buf, phys_ram_base + prom_offset);
        !           251:     }
        !           252:     if (ret < 0) {
        !           253:        fprintf(stderr, "qemu: could not load prom '%s'\n", 
        !           254:                buf);
        !           255:        exit(1);
        !           256:     }
        !           257:     cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, 
        !           258:                                  prom_offset | IO_MEM_ROM);
        !           259: 
        !           260:     kernel_size = 0;
        !           261:     if (linux_boot) {
        !           262:         kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
        !           263:         if (kernel_size < 0)
        !           264:            kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
        !           265:        if (kernel_size < 0)
        !           266:            kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
        !           267:         if (kernel_size < 0) {
        !           268:             fprintf(stderr, "qemu: could not load kernel '%s'\n", 
        !           269:                     kernel_filename);
        !           270:            exit(1);
        !           271:         }
        !           272: 
        !           273:         /* load initrd */
        !           274:         initrd_size = 0;
        !           275:         if (initrd_filename) {
        !           276:             initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
        !           277:             if (initrd_size < 0) {
        !           278:                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 
        !           279:                         initrd_filename);
        !           280:                 exit(1);
        !           281:             }
        !           282:         }
        !           283:         if (initrd_size > 0) {
        !           284:            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
        !           285:                if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
        !           286:                    == 0x48647253) { // HdrS
        !           287:                    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
        !           288:                    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
        !           289:                    break;
        !           290:                }
        !           291:            }
        !           292:         }
        !           293:     }
        !           294:     nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
        !           295: }
        !           296: 
        !           297: QEMUMachine sun4m_machine = {
        !           298:     "sun4m",
        !           299:     "Sun4m platform",
        !           300:     sun4m_init,
        !           301: };

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