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1.1 root 1: /*
1.1.1.6 root 2: * QEMU Sun4m & Sun4d & Sun4c System Emulator
3: *
1.1 root 4: * Copyright (c) 2003-2005 Fabrice Bellard
1.1.1.6 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.8 root 24: #include "sysbus.h"
1.1.1.6 root 25: #include "qemu-timer.h"
26: #include "sun4m.h"
27: #include "nvram.h"
28: #include "sparc32_dma.h"
29: #include "fdc.h"
30: #include "sysemu.h"
31: #include "net.h"
32: #include "boards.h"
33: #include "firmware_abi.h"
1.1.1.10 root 34: #include "esp.h"
1.1.1.7 root 35: #include "pc.h"
36: #include "isa.h"
37: #include "fw_cfg.h"
38: #include "escc.h"
1.1.1.11 root 39: #include "empty_slot.h"
1.1.1.10 root 40: #include "qdev-addr.h"
41: #include "loader.h"
42: #include "elf.h"
1.1.1.12! root 43: #include "blockdev.h"
! 44: #include "trace.h"
1.1.1.6 root 45:
46: /*
47: * Sun4m architecture was used in the following machines:
48: *
49: * SPARCserver 6xxMP/xx
1.1.1.7 root 50: * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51: * SPARCclassic X (4/10)
1.1.1.6 root 52: * SPARCstation LX/ZX (4/30)
53: * SPARCstation Voyager
54: * SPARCstation 10/xx, SPARCserver 10/xx
55: * SPARCstation 5, SPARCserver 5
56: * SPARCstation 20/xx, SPARCserver 20
57: * SPARCstation 4
58: *
59: * Sun4d architecture was used in the following machines:
60: *
61: * SPARCcenter 2000
62: * SPARCserver 1000
63: *
64: * Sun4c architecture was used in the following machines:
65: * SPARCstation 1/1+, SPARCserver 1/1+
66: * SPARCstation SLC
67: * SPARCstation IPC
68: * SPARCstation ELC
69: * SPARCstation IPX
70: *
71: * See for example: http://www.sunhelp.org/faq/sunref1.html
72: */
73:
1.1 root 74: #define KERNEL_LOAD_ADDR 0x00004000
75: #define CMDLINE_ADDR 0x007ff000
76: #define INITRD_LOAD_ADDR 0x00800000
1.1.1.7 root 77: #define PROM_SIZE_MAX (1024 * 1024)
1.1.1.6 root 78: #define PROM_VADDR 0xffd00000
79: #define PROM_FILENAME "openbios-sparc32"
1.1.1.7 root 80: #define CFG_ADDR 0xd00000510ULL
81: #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82:
1.1.1.2 root 83: #define MAX_CPUS 16
1.1.1.6 root 84: #define MAX_PILS 16
1.1.1.11 root 85: #define MAX_VSIMMS 4
1.1.1.6 root 86:
1.1.1.7 root 87: #define ESCC_CLOCK 4915200
88:
89: struct sun4m_hwdef {
1.1.1.11 root 90: target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
1.1.1.6 root 91: target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92: target_phys_addr_t serial_base, fd_base;
1.1.1.11 root 93: target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
1.1.1.7 root 94: target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
1.1.1.11 root 95: target_phys_addr_t bpp_base, dbri_base, sx_base;
96: struct {
97: target_phys_addr_t reg_base, vram_base;
98: } vsimm[MAX_VSIMMS];
1.1.1.6 root 99: target_phys_addr_t ecc_base;
100: uint32_t ecc_version;
1.1.1.7 root 101: uint8_t nvram_machine_id;
102: uint16_t machine_id;
1.1.1.6 root 103: uint32_t iommu_version;
104: uint64_t max_mem;
105: const char * const default_cpu_model;
106: };
107:
108: #define MAX_IOUNITS 5
109:
110: struct sun4d_hwdef {
111: target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112: target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113: target_phys_addr_t serial_base;
114: target_phys_addr_t espdma_base, esp_base;
115: target_phys_addr_t ledma_base, le_base;
116: target_phys_addr_t tcx_base;
117: target_phys_addr_t sbi_base;
1.1.1.7 root 118: uint8_t nvram_machine_id;
119: uint16_t machine_id;
1.1.1.6 root 120: uint32_t iounit_version;
121: uint64_t max_mem;
122: const char * const default_cpu_model;
123: };
1.1 root 124:
1.1.1.7 root 125: struct sun4c_hwdef {
126: target_phys_addr_t iommu_base, slavio_base;
127: target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128: target_phys_addr_t serial_base, fd_base;
129: target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130: target_phys_addr_t tcx_base, aux1_base;
131: uint8_t nvram_machine_id;
132: uint16_t machine_id;
133: uint32_t iommu_version;
134: uint64_t max_mem;
135: const char * const default_cpu_model;
136: };
1.1 root 137:
138: int DMA_get_channel_mode (int nchan)
139: {
140: return 0;
141: }
142: int DMA_read_memory (int nchan, void *buf, int pos, int size)
143: {
144: return 0;
145: }
146: int DMA_write_memory (int nchan, void *buf, int pos, int size)
147: {
148: return 0;
149: }
150: void DMA_hold_DREQ (int nchan) {}
151: void DMA_release_DREQ (int nchan) {}
152: void DMA_schedule(int nchan) {}
1.1.1.11 root 153:
154: void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155: {
156: }
157:
1.1 root 158: void DMA_register_channel (int nchan,
159: DMA_transfer_handler transfer_handler,
160: void *opaque)
161: {
162: }
163:
1.1.1.8 root 164: static int fw_cfg_boot_set(void *opaque, const char *boot_device)
1.1.1.7 root 165: {
1.1.1.8 root 166: fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
1.1.1.7 root 167: return 0;
168: }
1.1 root 169:
1.1.1.11 root 170: static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171: const char *cmdline, const char *boot_devices,
172: ram_addr_t RAM_size, uint32_t kernel_size,
1.1.1.6 root 173: int width, int height, int depth,
1.1.1.7 root 174: int nvram_machine_id, const char *arch)
1.1 root 175: {
1.1.1.6 root 176: unsigned int i;
177: uint32_t start, end;
178: uint8_t image[0x1ff0];
179: struct OpenBIOS_nvpart_v1 *part_header;
180:
181: memset(image, '\0', sizeof(image));
1.1 root 182:
1.1.1.8 root 183: start = 0;
1.1.1.6 root 184:
185: // OpenBIOS nvram variables
186: // Variable partition
187: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188: part_header->signature = OPENBIOS_PART_SYSTEM;
1.1.1.7 root 189: pstrcpy(part_header->name, sizeof(part_header->name), "system");
1.1.1.6 root 190:
191: end = start + sizeof(struct OpenBIOS_nvpart_v1);
192: for (i = 0; i < nb_prom_envs; i++)
193: end = OpenBIOS_set_var(image, end, prom_envs[i]);
194:
195: // End marker
196: image[end++] = '\0';
197:
198: end = start + ((end - start + 15) & ~15);
199: OpenBIOS_finish_partition(part_header, end - start);
200:
201: // free partition
202: start = end;
203: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204: part_header->signature = OPENBIOS_PART_FREE;
1.1.1.7 root 205: pstrcpy(part_header->name, sizeof(part_header->name), "free");
1.1.1.6 root 206:
207: end = 0x1fd0;
208: OpenBIOS_finish_partition(part_header, end - start);
209:
1.1.1.7 root 210: Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211: nvram_machine_id);
1.1.1.6 root 212:
213: for (i = 0; i < sizeof(image); i++)
214: m48t59_write(nvram, i, image[i]);
1.1 root 215: }
216:
1.1.1.10 root 217: static DeviceState *slavio_intctl;
1.1 root 218:
1.1.1.8 root 219: void pic_info(Monitor *mon)
1.1 root 220: {
1.1.1.6 root 221: if (slavio_intctl)
1.1.1.8 root 222: slavio_pic_info(mon, slavio_intctl);
1.1 root 223: }
224:
1.1.1.8 root 225: void irq_info(Monitor *mon)
1.1 root 226: {
1.1.1.6 root 227: if (slavio_intctl)
1.1.1.8 root 228: slavio_irq_info(mon, slavio_intctl);
1.1 root 229: }
230:
1.1.1.6 root 231: void cpu_check_irqs(CPUState *env)
1.1 root 232: {
1.1.1.6 root 233: if (env->pil_in && (env->interrupt_index == 0 ||
234: (env->interrupt_index & ~15) == TT_EXTINT)) {
235: unsigned int i;
236:
237: for (i = 15; i > 0; i--) {
238: if (env->pil_in & (1 << i)) {
239: int old_interrupt = env->interrupt_index;
240:
241: env->interrupt_index = TT_EXTINT | i;
1.1.1.7 root 242: if (old_interrupt != env->interrupt_index) {
1.1.1.12! root 243: trace_sun4m_cpu_interrupt(i);
1.1.1.6 root 244: cpu_interrupt(env, CPU_INTERRUPT_HARD);
1.1.1.7 root 245: }
1.1.1.6 root 246: break;
247: }
248: }
249: } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
1.1.1.12! root 250: trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
1.1.1.6 root 251: env->interrupt_index = 0;
252: cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253: }
1.1 root 254: }
255:
1.1.1.6 root 256: static void cpu_set_irq(void *opaque, int irq, int level)
1.1.1.4 root 257: {
1.1.1.6 root 258: CPUState *env = opaque;
259:
260: if (level) {
1.1.1.12! root 261: trace_sun4m_cpu_set_irq_raise(irq);
1.1.1.6 root 262: env->halted = 0;
263: env->pil_in |= 1 << irq;
264: cpu_check_irqs(env);
265: } else {
1.1.1.12! root 266: trace_sun4m_cpu_set_irq_lower(irq);
1.1.1.6 root 267: env->pil_in &= ~(1 << irq);
268: cpu_check_irqs(env);
269: }
1.1.1.4 root 270: }
271:
1.1.1.6 root 272: static void dummy_cpu_set_irq(void *opaque, int irq, int level)
1.1.1.2 root 273: {
274: }
275:
276: static void main_cpu_reset(void *opaque)
277: {
278: CPUState *env = opaque;
1.1.1.6 root 279:
1.1.1.2 root 280: cpu_reset(env);
1.1.1.6 root 281: env->halted = 0;
1.1.1.2 root 282: }
283:
1.1.1.6 root 284: static void secondary_cpu_reset(void *opaque)
1.1 root 285: {
1.1.1.6 root 286: CPUState *env = opaque;
287:
288: cpu_reset(env);
289: env->halted = 1;
290: }
291:
1.1.1.7 root 292: static void cpu_halt_signal(void *opaque, int irq, int level)
293: {
294: if (level && cpu_single_env)
295: cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
296: }
297:
1.1.1.11 root 298: static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
299: {
300: return addr - 0xf0000000ULL;
301: }
302:
1.1.1.6 root 303: static unsigned long sun4m_load_kernel(const char *kernel_filename,
1.1.1.7 root 304: const char *initrd_filename,
305: ram_addr_t RAM_size)
1.1.1.6 root 306: {
307: int linux_boot;
1.1 root 308: unsigned int i;
1.1.1.6 root 309: long initrd_size, kernel_size;
1.1.1.10 root 310: uint8_t *ptr;
1.1 root 311:
312: linux_boot = (kernel_filename != NULL);
313:
1.1.1.6 root 314: kernel_size = 0;
315: if (linux_boot) {
1.1.1.10 root 316: int bswap_needed;
317:
318: #ifdef BSWAP_NEEDED
319: bswap_needed = 1;
320: #else
321: bswap_needed = 0;
322: #endif
1.1.1.11 root 323: kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
324: NULL, NULL, NULL, 1, ELF_MACHINE, 0);
1.1.1.6 root 325: if (kernel_size < 0)
1.1.1.7 root 326: kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
1.1.1.10 root 327: RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
328: TARGET_PAGE_SIZE);
1.1.1.6 root 329: if (kernel_size < 0)
1.1.1.7 root 330: kernel_size = load_image_targphys(kernel_filename,
331: KERNEL_LOAD_ADDR,
332: RAM_size - KERNEL_LOAD_ADDR);
1.1.1.6 root 333: if (kernel_size < 0) {
334: fprintf(stderr, "qemu: could not load kernel '%s'\n",
335: kernel_filename);
336: exit(1);
337: }
338:
339: /* load initrd */
340: initrd_size = 0;
341: if (initrd_filename) {
1.1.1.7 root 342: initrd_size = load_image_targphys(initrd_filename,
343: INITRD_LOAD_ADDR,
344: RAM_size - INITRD_LOAD_ADDR);
1.1.1.6 root 345: if (initrd_size < 0) {
346: fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
347: initrd_filename);
348: exit(1);
349: }
350: }
351: if (initrd_size > 0) {
352: for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
1.1.1.10 root 353: ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
354: if (ldl_p(ptr) == 0x48647253) { // HdrS
355: stl_p(ptr + 16, INITRD_LOAD_ADDR);
356: stl_p(ptr + 20, initrd_size);
1.1.1.6 root 357: break;
358: }
359: }
360: }
361: }
362: return kernel_size;
363: }
364:
1.1.1.10 root 365: static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
366: {
367: DeviceState *dev;
368: SysBusDevice *s;
369:
370: dev = qdev_create(NULL, "iommu");
371: qdev_prop_set_uint32(dev, "version", version);
372: qdev_init_nofail(dev);
373: s = sysbus_from_qdev(dev);
374: sysbus_connect_irq(s, 0, irq);
375: sysbus_mmio_map(s, 0, addr);
376:
377: return s;
378: }
379:
380: static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1.1.1.12! root 381: void *iommu, qemu_irq *dev_irq, int is_ledma)
1.1.1.10 root 382: {
383: DeviceState *dev;
384: SysBusDevice *s;
385:
386: dev = qdev_create(NULL, "sparc32_dma");
387: qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
1.1.1.12! root 388: qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
1.1.1.10 root 389: qdev_init_nofail(dev);
390: s = sysbus_from_qdev(dev);
391: sysbus_connect_irq(s, 0, parent_irq);
392: *dev_irq = qdev_get_gpio_in(dev, 0);
393: sysbus_mmio_map(s, 0, daddr);
394:
395: return s;
396: }
397:
1.1.1.8 root 398: static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
1.1.1.10 root 399: void *dma_opaque, qemu_irq irq)
1.1.1.8 root 400: {
401: DeviceState *dev;
402: SysBusDevice *s;
1.1.1.10 root 403: qemu_irq reset;
1.1.1.8 root 404:
405: qemu_check_nic_model(&nd_table[0], "lance");
406:
407: dev = qdev_create(NULL, "lance");
1.1.1.10 root 408: qdev_set_nic_properties(dev, nd);
1.1.1.9 root 409: qdev_prop_set_ptr(dev, "dma", dma_opaque);
1.1.1.10 root 410: qdev_init_nofail(dev);
1.1.1.8 root 411: s = sysbus_from_qdev(dev);
412: sysbus_mmio_map(s, 0, leaddr);
413: sysbus_connect_irq(s, 0, irq);
1.1.1.10 root 414: reset = qdev_get_gpio_in(dev, 0);
415: qdev_connect_gpio_out(dma_opaque, 0, reset);
416: }
417:
418: static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
419: target_phys_addr_t addrg,
420: qemu_irq **parent_irq)
421: {
422: DeviceState *dev;
423: SysBusDevice *s;
424: unsigned int i, j;
425:
426: dev = qdev_create(NULL, "slavio_intctl");
427: qdev_init_nofail(dev);
428:
429: s = sysbus_from_qdev(dev);
430:
431: for (i = 0; i < MAX_CPUS; i++) {
432: for (j = 0; j < MAX_PILS; j++) {
433: sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
434: }
435: }
436: sysbus_mmio_map(s, 0, addrg);
437: for (i = 0; i < MAX_CPUS; i++) {
438: sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
439: }
440:
441: return dev;
442: }
443:
444: #define SYS_TIMER_OFFSET 0x10000ULL
445: #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
446:
447: static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
448: qemu_irq *cpu_irqs, unsigned int num_cpus)
449: {
450: DeviceState *dev;
451: SysBusDevice *s;
452: unsigned int i;
453:
454: dev = qdev_create(NULL, "slavio_timer");
455: qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
456: qdev_init_nofail(dev);
457: s = sysbus_from_qdev(dev);
458: sysbus_connect_irq(s, 0, master_irq);
459: sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
460:
461: for (i = 0; i < MAX_CPUS; i++) {
462: sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
463: sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
464: }
465: }
466:
467: #define MISC_LEDS 0x01600000
468: #define MISC_CFG 0x01800000
469: #define MISC_DIAG 0x01a00000
470: #define MISC_MDM 0x01b00000
471: #define MISC_SYS 0x01f00000
472:
473: static void slavio_misc_init(target_phys_addr_t base,
474: target_phys_addr_t aux1_base,
475: target_phys_addr_t aux2_base, qemu_irq irq,
476: qemu_irq fdc_tc)
477: {
478: DeviceState *dev;
479: SysBusDevice *s;
480:
481: dev = qdev_create(NULL, "slavio_misc");
482: qdev_init_nofail(dev);
483: s = sysbus_from_qdev(dev);
484: if (base) {
485: /* 8 bit registers */
486: /* Slavio control */
487: sysbus_mmio_map(s, 0, base + MISC_CFG);
488: /* Diagnostics */
489: sysbus_mmio_map(s, 1, base + MISC_DIAG);
490: /* Modem control */
491: sysbus_mmio_map(s, 2, base + MISC_MDM);
492: /* 16 bit registers */
493: /* ss600mp diag LEDs */
494: sysbus_mmio_map(s, 3, base + MISC_LEDS);
495: /* 32 bit registers */
496: /* System control */
497: sysbus_mmio_map(s, 4, base + MISC_SYS);
498: }
499: if (aux1_base) {
500: /* AUX 1 (Misc System Functions) */
501: sysbus_mmio_map(s, 5, aux1_base);
502: }
503: if (aux2_base) {
504: /* AUX 2 (Software Powerdown Control) */
505: sysbus_mmio_map(s, 6, aux2_base);
506: }
507: sysbus_connect_irq(s, 0, irq);
508: sysbus_connect_irq(s, 1, fdc_tc);
509: qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
510: }
511:
512: static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
513: {
514: DeviceState *dev;
515: SysBusDevice *s;
516:
517: dev = qdev_create(NULL, "eccmemctl");
518: qdev_prop_set_uint32(dev, "version", version);
519: qdev_init_nofail(dev);
520: s = sysbus_from_qdev(dev);
521: sysbus_connect_irq(s, 0, irq);
522: sysbus_mmio_map(s, 0, base);
523: if (version == 0) { // SS-600MP only
524: sysbus_mmio_map(s, 1, base + 0x1000);
525: }
526: }
527:
528: static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
529: {
530: DeviceState *dev;
531: SysBusDevice *s;
532:
533: dev = qdev_create(NULL, "apc");
534: qdev_init_nofail(dev);
535: s = sysbus_from_qdev(dev);
536: /* Power management (APC) XXX: not a Slavio device */
537: sysbus_mmio_map(s, 0, power_base);
538: sysbus_connect_irq(s, 0, cpu_halt);
539: }
540:
541: static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
542: int height, int depth)
543: {
544: DeviceState *dev;
545: SysBusDevice *s;
546:
547: dev = qdev_create(NULL, "SUNW,tcx");
548: qdev_prop_set_taddr(dev, "addr", addr);
549: qdev_prop_set_uint32(dev, "vram_size", vram_size);
550: qdev_prop_set_uint16(dev, "width", width);
551: qdev_prop_set_uint16(dev, "height", height);
552: qdev_prop_set_uint16(dev, "depth", depth);
553: qdev_init_nofail(dev);
554: s = sysbus_from_qdev(dev);
555: /* 8-bit plane */
556: sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
557: /* DAC */
558: sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
559: /* TEC (dummy) */
560: sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
561: /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
562: sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
563: if (depth == 24) {
564: /* 24-bit plane */
565: sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
566: /* Control plane */
567: sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
568: } else {
569: /* THC 8 bit (dummy) */
570: sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
571: }
1.1.1.8 root 572: }
573:
574: /* NCR89C100/MACIO Internal ID register */
575: static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
576:
577: static void idreg_init(target_phys_addr_t addr)
578: {
579: DeviceState *dev;
580: SysBusDevice *s;
581:
582: dev = qdev_create(NULL, "macio_idreg");
1.1.1.10 root 583: qdev_init_nofail(dev);
1.1.1.8 root 584: s = sysbus_from_qdev(dev);
585:
586: sysbus_mmio_map(s, 0, addr);
587: cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
588: }
589:
1.1.1.10 root 590: static int idreg_init1(SysBusDevice *dev)
1.1.1.8 root 591: {
592: ram_addr_t idreg_offset;
593:
1.1.1.11 root 594: idreg_offset = qemu_ram_alloc(NULL, "sun4m.idreg", sizeof(idreg_data));
1.1.1.8 root 595: sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
1.1.1.10 root 596: return 0;
1.1.1.8 root 597: }
598:
599: static SysBusDeviceInfo idreg_info = {
600: .init = idreg_init1,
601: .qdev.name = "macio_idreg",
602: .qdev.size = sizeof(SysBusDevice),
603: };
604:
605: static void idreg_register_devices(void)
606: {
607: sysbus_register_withprop(&idreg_info);
608: }
609:
610: device_init(idreg_register_devices);
611:
1.1.1.11 root 612: /* SS-5 TCX AFX register */
613: static void afx_init(target_phys_addr_t addr)
614: {
615: DeviceState *dev;
616: SysBusDevice *s;
617:
618: dev = qdev_create(NULL, "tcx_afx");
619: qdev_init_nofail(dev);
620: s = sysbus_from_qdev(dev);
621:
622: sysbus_mmio_map(s, 0, addr);
623: }
624:
625: static int afx_init1(SysBusDevice *dev)
626: {
627: ram_addr_t afx_offset;
628:
629: afx_offset = qemu_ram_alloc(NULL, "sun4m.afx", 4);
630: sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
631: return 0;
632: }
633:
634: static SysBusDeviceInfo afx_info = {
635: .init = afx_init1,
636: .qdev.name = "tcx_afx",
637: .qdev.size = sizeof(SysBusDevice),
638: };
639:
640: static void afx_register_devices(void)
641: {
642: sysbus_register_withprop(&afx_info);
643: }
644:
645: device_init(afx_register_devices);
646:
1.1.1.8 root 647: /* Boot PROM (OpenBIOS) */
1.1.1.11 root 648: static uint64_t translate_prom_address(void *opaque, uint64_t addr)
649: {
650: target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
651: return addr + *base_addr - PROM_VADDR;
652: }
653:
1.1.1.8 root 654: static void prom_init(target_phys_addr_t addr, const char *bios_name)
655: {
656: DeviceState *dev;
657: SysBusDevice *s;
658: char *filename;
659: int ret;
660:
661: dev = qdev_create(NULL, "openprom");
1.1.1.10 root 662: qdev_init_nofail(dev);
1.1.1.8 root 663: s = sysbus_from_qdev(dev);
664:
665: sysbus_mmio_map(s, 0, addr);
666:
667: /* load boot prom */
668: if (bios_name == NULL) {
669: bios_name = PROM_FILENAME;
670: }
671: filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
672: if (filename) {
1.1.1.11 root 673: ret = load_elf(filename, translate_prom_address, &addr, NULL,
674: NULL, NULL, 1, ELF_MACHINE, 0);
1.1.1.8 root 675: if (ret < 0 || ret > PROM_SIZE_MAX) {
676: ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
677: }
678: qemu_free(filename);
679: } else {
680: ret = -1;
681: }
682: if (ret < 0 || ret > PROM_SIZE_MAX) {
683: fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
684: exit(1);
685: }
686: }
687:
1.1.1.10 root 688: static int prom_init1(SysBusDevice *dev)
1.1.1.8 root 689: {
690: ram_addr_t prom_offset;
691:
1.1.1.11 root 692: prom_offset = qemu_ram_alloc(NULL, "sun4m.prom", PROM_SIZE_MAX);
1.1.1.8 root 693: sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
1.1.1.10 root 694: return 0;
1.1.1.8 root 695: }
696:
697: static SysBusDeviceInfo prom_info = {
698: .init = prom_init1,
699: .qdev.name = "openprom",
700: .qdev.size = sizeof(SysBusDevice),
701: .qdev.props = (Property[]) {
702: {/* end of property list */}
703: }
704: };
705:
706: static void prom_register_devices(void)
707: {
708: sysbus_register_withprop(&prom_info);
709: }
710:
711: device_init(prom_register_devices);
712:
713: typedef struct RamDevice
714: {
715: SysBusDevice busdev;
1.1.1.10 root 716: uint64_t size;
1.1.1.8 root 717: } RamDevice;
718:
719: /* System RAM */
1.1.1.10 root 720: static int ram_init1(SysBusDevice *dev)
1.1.1.8 root 721: {
722: ram_addr_t RAM_size, ram_offset;
723: RamDevice *d = FROM_SYSBUS(RamDevice, dev);
724:
725: RAM_size = d->size;
726:
1.1.1.11 root 727: ram_offset = qemu_ram_alloc(NULL, "sun4m.ram", RAM_size);
1.1.1.8 root 728: sysbus_init_mmio(dev, RAM_size, ram_offset);
1.1.1.10 root 729: return 0;
1.1.1.8 root 730: }
731:
732: static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
733: uint64_t max_mem)
734: {
735: DeviceState *dev;
736: SysBusDevice *s;
737: RamDevice *d;
738:
739: /* allocate RAM */
740: if ((uint64_t)RAM_size > max_mem) {
741: fprintf(stderr,
742: "qemu: Too much memory for this machine: %d, maximum %d\n",
743: (unsigned int)(RAM_size / (1024 * 1024)),
744: (unsigned int)(max_mem / (1024 * 1024)));
745: exit(1);
746: }
747: dev = qdev_create(NULL, "memory");
748: s = sysbus_from_qdev(dev);
749:
750: d = FROM_SYSBUS(RamDevice, s);
751: d->size = RAM_size;
1.1.1.10 root 752: qdev_init_nofail(dev);
1.1.1.8 root 753:
754: sysbus_mmio_map(s, 0, addr);
755: }
756:
757: static SysBusDeviceInfo ram_info = {
758: .init = ram_init1,
759: .qdev.name = "memory",
760: .qdev.size = sizeof(RamDevice),
761: .qdev.props = (Property[]) {
1.1.1.10 root 762: DEFINE_PROP_UINT64("size", RamDevice, size, 0),
763: DEFINE_PROP_END_OF_LIST(),
1.1.1.8 root 764: }
765: };
766:
767: static void ram_register_devices(void)
768: {
769: sysbus_register_withprop(&ram_info);
770: }
771:
772: device_init(ram_register_devices);
773:
1.1.1.11 root 774: static void cpu_devinit(const char *cpu_model, unsigned int id,
775: uint64_t prom_addr, qemu_irq **cpu_irqs)
1.1.1.8 root 776: {
777: CPUState *env;
778:
779: env = cpu_init(cpu_model);
780: if (!env) {
781: fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
782: exit(1);
783: }
784:
785: cpu_sparc_set_id(env, id);
786: if (id == 0) {
787: qemu_register_reset(main_cpu_reset, env);
788: } else {
789: qemu_register_reset(secondary_cpu_reset, env);
790: env->halted = 1;
791: }
792: *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
793: env->prom_addr = prom_addr;
794: }
795:
1.1.1.7 root 796: static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
1.1.1.6 root 797: const char *boot_device,
1.1.1.7 root 798: const char *kernel_filename,
1.1.1.6 root 799: const char *kernel_cmdline,
800: const char *initrd_filename, const char *cpu_model)
801: {
802: unsigned int i;
1.1.1.8 root 803: void *iommu, *espdma, *ledma, *nvram;
804: qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
805: espdma_irq, ledma_irq;
1.1.1.12! root 806: qemu_irq esp_reset, dma_enable;
1.1.1.8 root 807: qemu_irq fdc_tc;
1.1.1.7 root 808: qemu_irq *cpu_halt;
809: unsigned long kernel_size;
1.1.1.10 root 810: DriveInfo *fd[MAX_FD];
1.1.1.7 root 811: void *fw_cfg;
1.1.1.11 root 812: unsigned int num_vsimms;
1.1.1.6 root 813:
1.1.1.2 root 814: /* init CPUs */
1.1.1.6 root 815: if (!cpu_model)
816: cpu_model = hwdef->default_cpu_model;
817:
1.1.1.2 root 818: for(i = 0; i < smp_cpus; i++) {
1.1.1.11 root 819: cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1.1.1.2 root 820: }
1.1.1.6 root 821:
822: for (i = smp_cpus; i < MAX_CPUS; i++)
823: cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
824:
825:
1.1.1.8 root 826: /* set up devices */
827: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.11 root 828: /* models without ECC don't trap when missing ram is accessed */
829: if (!hwdef->ecc_base) {
830: empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
831: }
1.1 root 832:
1.1.1.8 root 833: prom_init(hwdef->slavio_base, bios_name);
1.1.1.6 root 834:
1.1.1.10 root 835: slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
836: hwdef->intctl_base + 0x10000ULL,
837: cpu_irqs);
1.1.1.2 root 838:
1.1.1.8 root 839: for (i = 0; i < 32; i++) {
1.1.1.10 root 840: slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
1.1.1.8 root 841: }
842: for (i = 0; i < MAX_CPUS; i++) {
1.1.1.10 root 843: slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
1.1.1.8 root 844: }
1.1.1.6 root 845:
1.1.1.7 root 846: if (hwdef->idreg_base) {
1.1.1.8 root 847: idreg_init(hwdef->idreg_base);
1.1.1.3 root 848: }
1.1.1.6 root 849:
1.1.1.11 root 850: if (hwdef->afx_base) {
851: afx_init(hwdef->afx_base);
852: }
853:
1.1.1.6 root 854: iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1.1.1.10 root 855: slavio_irq[30]);
1.1.1.6 root 856:
1.1.1.11 root 857: if (hwdef->iommu_pad_base) {
858: /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
859: Software shouldn't use aliased addresses, neither should it crash
860: when does. Using empty_slot instead of aliasing can help with
861: debugging such accesses */
862: empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
863: }
864:
1.1.1.10 root 865: espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
1.1.1.12! root 866: iommu, &espdma_irq, 0);
1.1.1.6 root 867:
868: ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1.1.1.12! root 869: slavio_irq[16], iommu, &ledma_irq, 1);
1.1.1.6 root 870:
871: if (graphic_depth != 8 && graphic_depth != 24) {
872: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
873: exit (1);
874: }
1.1.1.11 root 875: num_vsimms = 0;
876: if (num_vsimms == 0) {
877: tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
878: graphic_depth);
879: }
880:
881: for (i = num_vsimms; i < MAX_VSIMMS; i++) {
882: /* vsimm registers probed by OBP */
883: if (hwdef->vsimm[i].reg_base) {
884: empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
885: }
886: }
887:
888: if (hwdef->sx_base) {
889: empty_slot_init(hwdef->sx_base, 0x2000);
890: }
1.1.1.6 root 891:
1.1.1.10 root 892: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1.1.1.6 root 893:
1.1.1.10 root 894: nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1.1.1.6 root 895:
1.1.1.10 root 896: slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
1.1.1.6 root 897:
1.1.1.10 root 898: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
1.1.1.8 root 899: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1 root 900: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
901: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1.1.1.10 root 902: escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
1.1.1.7 root 903: serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1.1.1.6 root 904:
1.1.1.7 root 905: cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
1.1.1.10 root 906: slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
907: slavio_irq[30], fdc_tc);
908:
1.1.1.8 root 909: if (hwdef->apc_base) {
910: apc_init(hwdef->apc_base, cpu_halt[0]);
911: }
1.1.1.7 root 912:
913: if (hwdef->fd_base) {
1.1.1.6 root 914: /* there is zero or one floppy drive */
1.1.1.7 root 915: memset(fd, 0, sizeof(fd));
1.1.1.10 root 916: fd[0] = drive_get(IF_FLOPPY, 0, 0);
917: sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1.1.1.8 root 918: &fdc_tc);
1.1.1.6 root 919: }
920:
921: if (drive_get_max_bus(IF_SCSI) > 0) {
922: fprintf(stderr, "qemu: too many SCSI bus\n");
923: exit(1);
924: }
925:
1.1.1.8 root 926: esp_init(hwdef->esp_base, 2,
927: espdma_memory_read, espdma_memory_write,
1.1.1.12! root 928: espdma, espdma_irq, &esp_reset, &dma_enable);
1.1.1.10 root 929:
1.1.1.12! root 930: qdev_connect_gpio_out(espdma, 0, esp_reset);
! 931: qdev_connect_gpio_out(espdma, 1, dma_enable);
1.1.1.8 root 932:
933: if (hwdef->cs_base) {
934: sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1.1.1.10 root 935: slavio_irq[5]);
1.1.1.6 root 936: }
937:
1.1.1.11 root 938: if (hwdef->dbri_base) {
939: /* ISDN chip with attached CS4215 audio codec */
940: /* prom space */
941: empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
942: /* reg space */
943: empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
944: }
945:
946: if (hwdef->bpp_base) {
947: /* parallel port */
948: empty_slot_init(hwdef->bpp_base, 0x20);
949: }
950:
1.1.1.7 root 951: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
952: RAM_size);
1.1.1.6 root 953:
954: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
955: boot_device, RAM_size, kernel_size, graphic_width,
1.1.1.7 root 956: graphic_height, graphic_depth, hwdef->nvram_machine_id,
957: "Sun4m");
1.1.1.6 root 958:
1.1.1.7 root 959: if (hwdef->ecc_base)
1.1.1.10 root 960: ecc_init(hwdef->ecc_base, slavio_irq[28],
1.1.1.7 root 961: hwdef->ecc_version);
962:
963: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
964: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
965: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
966: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
967: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1.1.1.8 root 968: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
969: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
970: if (kernel_cmdline) {
971: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1.1.1.10 root 972: pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1.1.1.11 root 973: fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
974: (uint8_t*)strdup(kernel_cmdline),
975: strlen(kernel_cmdline) + 1);
1.1.1.12! root 976: fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
! 977: strlen(kernel_cmdline) + 1);
1.1.1.8 root 978: } else {
979: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1.1.1.12! root 980: fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1.1.1.8 root 981: }
982: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
983: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
984: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
985: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.7 root 986: }
987:
988: enum {
989: ss2_id = 0,
990: ss5_id = 32,
991: vger_id,
992: lx_id,
993: ss4_id,
994: scls_id,
995: sbook_id,
996: ss10_id = 64,
997: ss20_id,
998: ss600mp_id,
999: ss1000_id = 96,
1000: ss2000_id,
1001: };
1.1.1.6 root 1002:
1.1.1.7 root 1003: static const struct sun4m_hwdef sun4m_hwdefs[] = {
1.1.1.6 root 1004: /* SS-5 */
1005: {
1006: .iommu_base = 0x10000000,
1.1.1.11 root 1007: .iommu_pad_base = 0x10004000,
1008: .iommu_pad_len = 0x0fffb000,
1.1.1.6 root 1009: .tcx_base = 0x50000000,
1010: .cs_base = 0x6c000000,
1011: .slavio_base = 0x70000000,
1012: .ms_kb_base = 0x71000000,
1013: .serial_base = 0x71100000,
1014: .nvram_base = 0x71200000,
1015: .fd_base = 0x71400000,
1016: .counter_base = 0x71d00000,
1017: .intctl_base = 0x71e00000,
1018: .idreg_base = 0x78000000,
1019: .dma_base = 0x78400000,
1020: .esp_base = 0x78800000,
1021: .le_base = 0x78c00000,
1.1.1.7 root 1022: .apc_base = 0x6a000000,
1.1.1.11 root 1023: .afx_base = 0x6e000000,
1.1.1.7 root 1024: .aux1_base = 0x71900000,
1025: .aux2_base = 0x71910000,
1026: .nvram_machine_id = 0x80,
1027: .machine_id = ss5_id,
1.1.1.6 root 1028: .iommu_version = 0x05000000,
1029: .max_mem = 0x10000000,
1030: .default_cpu_model = "Fujitsu MB86904",
1031: },
1032: /* SS-10 */
1033: {
1034: .iommu_base = 0xfe0000000ULL,
1035: .tcx_base = 0xe20000000ULL,
1036: .slavio_base = 0xff0000000ULL,
1037: .ms_kb_base = 0xff1000000ULL,
1038: .serial_base = 0xff1100000ULL,
1039: .nvram_base = 0xff1200000ULL,
1040: .fd_base = 0xff1700000ULL,
1041: .counter_base = 0xff1300000ULL,
1042: .intctl_base = 0xff1400000ULL,
1043: .idreg_base = 0xef0000000ULL,
1044: .dma_base = 0xef0400000ULL,
1045: .esp_base = 0xef0800000ULL,
1046: .le_base = 0xef0c00000ULL,
1.1.1.7 root 1047: .apc_base = 0xefa000000ULL, // XXX should not exist
1048: .aux1_base = 0xff1800000ULL,
1049: .aux2_base = 0xff1a01000ULL,
1.1.1.6 root 1050: .ecc_base = 0xf00000000ULL,
1051: .ecc_version = 0x10000000, // version 0, implementation 1
1.1.1.7 root 1052: .nvram_machine_id = 0x72,
1053: .machine_id = ss10_id,
1.1.1.6 root 1054: .iommu_version = 0x03000000,
1.1.1.7 root 1055: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1056: .default_cpu_model = "TI SuperSparc II",
1057: },
1058: /* SS-600MP */
1059: {
1060: .iommu_base = 0xfe0000000ULL,
1061: .tcx_base = 0xe20000000ULL,
1062: .slavio_base = 0xff0000000ULL,
1063: .ms_kb_base = 0xff1000000ULL,
1064: .serial_base = 0xff1100000ULL,
1065: .nvram_base = 0xff1200000ULL,
1066: .counter_base = 0xff1300000ULL,
1067: .intctl_base = 0xff1400000ULL,
1068: .dma_base = 0xef0081000ULL,
1069: .esp_base = 0xef0080000ULL,
1070: .le_base = 0xef0060000ULL,
1.1.1.7 root 1071: .apc_base = 0xefa000000ULL, // XXX should not exist
1072: .aux1_base = 0xff1800000ULL,
1073: .aux2_base = 0xff1a01000ULL, // XXX should not exist
1.1.1.6 root 1074: .ecc_base = 0xf00000000ULL,
1075: .ecc_version = 0x00000000, // version 0, implementation 0
1.1.1.7 root 1076: .nvram_machine_id = 0x71,
1077: .machine_id = ss600mp_id,
1.1.1.6 root 1078: .iommu_version = 0x01000000,
1.1.1.7 root 1079: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1080: .default_cpu_model = "TI SuperSparc II",
1081: },
1082: /* SS-20 */
1083: {
1084: .iommu_base = 0xfe0000000ULL,
1085: .tcx_base = 0xe20000000ULL,
1086: .slavio_base = 0xff0000000ULL,
1087: .ms_kb_base = 0xff1000000ULL,
1088: .serial_base = 0xff1100000ULL,
1089: .nvram_base = 0xff1200000ULL,
1090: .fd_base = 0xff1700000ULL,
1091: .counter_base = 0xff1300000ULL,
1092: .intctl_base = 0xff1400000ULL,
1093: .idreg_base = 0xef0000000ULL,
1094: .dma_base = 0xef0400000ULL,
1095: .esp_base = 0xef0800000ULL,
1096: .le_base = 0xef0c00000ULL,
1.1.1.11 root 1097: .bpp_base = 0xef4800000ULL,
1.1.1.7 root 1098: .apc_base = 0xefa000000ULL, // XXX should not exist
1099: .aux1_base = 0xff1800000ULL,
1100: .aux2_base = 0xff1a01000ULL,
1.1.1.11 root 1101: .dbri_base = 0xee0000000ULL,
1102: .sx_base = 0xf80000000ULL,
1103: .vsimm = {
1104: {
1105: .reg_base = 0x9c000000ULL,
1106: .vram_base = 0xfc000000ULL
1107: }, {
1108: .reg_base = 0x90000000ULL,
1109: .vram_base = 0xf0000000ULL
1110: }, {
1111: .reg_base = 0x94000000ULL
1112: }, {
1113: .reg_base = 0x98000000ULL
1114: }
1115: },
1.1.1.6 root 1116: .ecc_base = 0xf00000000ULL,
1117: .ecc_version = 0x20000000, // version 0, implementation 2
1.1.1.7 root 1118: .nvram_machine_id = 0x72,
1119: .machine_id = ss20_id,
1.1.1.6 root 1120: .iommu_version = 0x13000000,
1.1.1.7 root 1121: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1122: .default_cpu_model = "TI SuperSparc II",
1123: },
1.1.1.7 root 1124: /* Voyager */
1.1.1.6 root 1125: {
1.1.1.7 root 1126: .iommu_base = 0x10000000,
1127: .tcx_base = 0x50000000,
1128: .slavio_base = 0x70000000,
1129: .ms_kb_base = 0x71000000,
1130: .serial_base = 0x71100000,
1131: .nvram_base = 0x71200000,
1132: .fd_base = 0x71400000,
1133: .counter_base = 0x71d00000,
1134: .intctl_base = 0x71e00000,
1135: .idreg_base = 0x78000000,
1136: .dma_base = 0x78400000,
1137: .esp_base = 0x78800000,
1138: .le_base = 0x78c00000,
1139: .apc_base = 0x71300000, // pmc
1140: .aux1_base = 0x71900000,
1141: .aux2_base = 0x71910000,
1142: .nvram_machine_id = 0x80,
1143: .machine_id = vger_id,
1144: .iommu_version = 0x05000000,
1.1.1.6 root 1145: .max_mem = 0x10000000,
1.1.1.7 root 1146: .default_cpu_model = "Fujitsu MB86904",
1147: },
1148: /* LX */
1149: {
1150: .iommu_base = 0x10000000,
1.1.1.11 root 1151: .iommu_pad_base = 0x10004000,
1152: .iommu_pad_len = 0x0fffb000,
1.1.1.7 root 1153: .tcx_base = 0x50000000,
1154: .slavio_base = 0x70000000,
1155: .ms_kb_base = 0x71000000,
1156: .serial_base = 0x71100000,
1157: .nvram_base = 0x71200000,
1158: .fd_base = 0x71400000,
1159: .counter_base = 0x71d00000,
1160: .intctl_base = 0x71e00000,
1161: .idreg_base = 0x78000000,
1162: .dma_base = 0x78400000,
1163: .esp_base = 0x78800000,
1164: .le_base = 0x78c00000,
1165: .aux1_base = 0x71900000,
1166: .aux2_base = 0x71910000,
1167: .nvram_machine_id = 0x80,
1168: .machine_id = lx_id,
1169: .iommu_version = 0x04000000,
1170: .max_mem = 0x10000000,
1171: .default_cpu_model = "TI MicroSparc I",
1172: },
1173: /* SS-4 */
1174: {
1175: .iommu_base = 0x10000000,
1176: .tcx_base = 0x50000000,
1177: .cs_base = 0x6c000000,
1178: .slavio_base = 0x70000000,
1179: .ms_kb_base = 0x71000000,
1180: .serial_base = 0x71100000,
1181: .nvram_base = 0x71200000,
1182: .fd_base = 0x71400000,
1183: .counter_base = 0x71d00000,
1184: .intctl_base = 0x71e00000,
1185: .idreg_base = 0x78000000,
1186: .dma_base = 0x78400000,
1187: .esp_base = 0x78800000,
1188: .le_base = 0x78c00000,
1189: .apc_base = 0x6a000000,
1190: .aux1_base = 0x71900000,
1191: .aux2_base = 0x71910000,
1192: .nvram_machine_id = 0x80,
1193: .machine_id = ss4_id,
1194: .iommu_version = 0x05000000,
1195: .max_mem = 0x10000000,
1196: .default_cpu_model = "Fujitsu MB86904",
1197: },
1198: /* SPARCClassic */
1199: {
1200: .iommu_base = 0x10000000,
1201: .tcx_base = 0x50000000,
1202: .slavio_base = 0x70000000,
1203: .ms_kb_base = 0x71000000,
1204: .serial_base = 0x71100000,
1205: .nvram_base = 0x71200000,
1206: .fd_base = 0x71400000,
1207: .counter_base = 0x71d00000,
1208: .intctl_base = 0x71e00000,
1209: .idreg_base = 0x78000000,
1210: .dma_base = 0x78400000,
1211: .esp_base = 0x78800000,
1212: .le_base = 0x78c00000,
1213: .apc_base = 0x6a000000,
1214: .aux1_base = 0x71900000,
1215: .aux2_base = 0x71910000,
1216: .nvram_machine_id = 0x80,
1217: .machine_id = scls_id,
1218: .iommu_version = 0x05000000,
1219: .max_mem = 0x10000000,
1220: .default_cpu_model = "TI MicroSparc I",
1221: },
1222: /* SPARCbook */
1223: {
1224: .iommu_base = 0x10000000,
1225: .tcx_base = 0x50000000, // XXX
1226: .slavio_base = 0x70000000,
1227: .ms_kb_base = 0x71000000,
1228: .serial_base = 0x71100000,
1229: .nvram_base = 0x71200000,
1230: .fd_base = 0x71400000,
1231: .counter_base = 0x71d00000,
1232: .intctl_base = 0x71e00000,
1233: .idreg_base = 0x78000000,
1234: .dma_base = 0x78400000,
1235: .esp_base = 0x78800000,
1236: .le_base = 0x78c00000,
1237: .apc_base = 0x6a000000,
1238: .aux1_base = 0x71900000,
1239: .aux2_base = 0x71910000,
1240: .nvram_machine_id = 0x80,
1241: .machine_id = sbook_id,
1242: .iommu_version = 0x05000000,
1243: .max_mem = 0x10000000,
1244: .default_cpu_model = "TI MicroSparc I",
1.1.1.6 root 1245: },
1246: };
1247:
1248: /* SPARCstation 5 hardware initialisation */
1.1.1.8 root 1249: static void ss5_init(ram_addr_t RAM_size,
1.1.1.7 root 1250: const char *boot_device,
1.1.1.6 root 1251: const char *kernel_filename, const char *kernel_cmdline,
1252: const char *initrd_filename, const char *cpu_model)
1253: {
1.1.1.7 root 1254: sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1255: kernel_cmdline, initrd_filename, cpu_model);
1256: }
1257:
1258: /* SPARCstation 10 hardware initialisation */
1.1.1.8 root 1259: static void ss10_init(ram_addr_t RAM_size,
1.1.1.7 root 1260: const char *boot_device,
1.1.1.6 root 1261: const char *kernel_filename, const char *kernel_cmdline,
1262: const char *initrd_filename, const char *cpu_model)
1263: {
1.1.1.7 root 1264: sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1265: kernel_cmdline, initrd_filename, cpu_model);
1266: }
1267:
1268: /* SPARCserver 600MP hardware initialisation */
1.1.1.8 root 1269: static void ss600mp_init(ram_addr_t RAM_size,
1.1.1.7 root 1270: const char *boot_device,
1271: const char *kernel_filename,
1272: const char *kernel_cmdline,
1.1.1.6 root 1273: const char *initrd_filename, const char *cpu_model)
1274: {
1.1.1.7 root 1275: sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1276: kernel_cmdline, initrd_filename, cpu_model);
1277: }
1278:
1279: /* SPARCstation 20 hardware initialisation */
1.1.1.8 root 1280: static void ss20_init(ram_addr_t RAM_size,
1.1.1.7 root 1281: const char *boot_device,
1.1.1.6 root 1282: const char *kernel_filename, const char *kernel_cmdline,
1283: const char *initrd_filename, const char *cpu_model)
1284: {
1.1.1.7 root 1285: sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1286: kernel_cmdline, initrd_filename, cpu_model);
1287: }
1288:
1.1.1.7 root 1289: /* SPARCstation Voyager hardware initialisation */
1.1.1.8 root 1290: static void vger_init(ram_addr_t RAM_size,
1.1.1.7 root 1291: const char *boot_device,
1292: const char *kernel_filename, const char *kernel_cmdline,
1293: const char *initrd_filename, const char *cpu_model)
1294: {
1295: sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1296: kernel_cmdline, initrd_filename, cpu_model);
1297: }
1298:
1299: /* SPARCstation LX hardware initialisation */
1.1.1.8 root 1300: static void ss_lx_init(ram_addr_t RAM_size,
1.1.1.7 root 1301: const char *boot_device,
1302: const char *kernel_filename, const char *kernel_cmdline,
1303: const char *initrd_filename, const char *cpu_model)
1304: {
1305: sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1306: kernel_cmdline, initrd_filename, cpu_model);
1307: }
1308:
1309: /* SPARCstation 4 hardware initialisation */
1.1.1.8 root 1310: static void ss4_init(ram_addr_t RAM_size,
1.1.1.7 root 1311: const char *boot_device,
1.1.1.6 root 1312: const char *kernel_filename, const char *kernel_cmdline,
1313: const char *initrd_filename, const char *cpu_model)
1314: {
1.1.1.7 root 1315: sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1316: kernel_cmdline, initrd_filename, cpu_model);
1317: }
1318:
1319: /* SPARCClassic hardware initialisation */
1.1.1.8 root 1320: static void scls_init(ram_addr_t RAM_size,
1.1.1.7 root 1321: const char *boot_device,
1322: const char *kernel_filename, const char *kernel_cmdline,
1323: const char *initrd_filename, const char *cpu_model)
1324: {
1325: sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1326: kernel_cmdline, initrd_filename, cpu_model);
1327: }
1328:
1329: /* SPARCbook hardware initialisation */
1.1.1.8 root 1330: static void sbook_init(ram_addr_t RAM_size,
1.1.1.7 root 1331: const char *boot_device,
1332: const char *kernel_filename, const char *kernel_cmdline,
1333: const char *initrd_filename, const char *cpu_model)
1334: {
1335: sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1336: kernel_cmdline, initrd_filename, cpu_model);
1337: }
1338:
1.1.1.8 root 1339: static QEMUMachine ss5_machine = {
1.1.1.7 root 1340: .name = "SS-5",
1341: .desc = "Sun4m platform, SPARCstation 5",
1342: .init = ss5_init,
1343: .use_scsi = 1,
1.1.1.8 root 1344: .is_default = 1,
1.1.1.6 root 1345: };
1346:
1.1.1.8 root 1347: static QEMUMachine ss10_machine = {
1.1.1.7 root 1348: .name = "SS-10",
1349: .desc = "Sun4m platform, SPARCstation 10",
1350: .init = ss10_init,
1351: .use_scsi = 1,
1352: .max_cpus = 4,
1.1.1.6 root 1353: };
1354:
1.1.1.8 root 1355: static QEMUMachine ss600mp_machine = {
1.1.1.7 root 1356: .name = "SS-600MP",
1357: .desc = "Sun4m platform, SPARCserver 600MP",
1358: .init = ss600mp_init,
1359: .use_scsi = 1,
1360: .max_cpus = 4,
1.1.1.6 root 1361: };
1362:
1.1.1.8 root 1363: static QEMUMachine ss20_machine = {
1.1.1.7 root 1364: .name = "SS-20",
1365: .desc = "Sun4m platform, SPARCstation 20",
1366: .init = ss20_init,
1367: .use_scsi = 1,
1368: .max_cpus = 4,
1.1.1.6 root 1369: };
1370:
1.1.1.8 root 1371: static QEMUMachine voyager_machine = {
1.1.1.7 root 1372: .name = "Voyager",
1373: .desc = "Sun4m platform, SPARCstation Voyager",
1374: .init = vger_init,
1375: .use_scsi = 1,
1376: };
1377:
1.1.1.8 root 1378: static QEMUMachine ss_lx_machine = {
1.1.1.7 root 1379: .name = "LX",
1380: .desc = "Sun4m platform, SPARCstation LX",
1381: .init = ss_lx_init,
1382: .use_scsi = 1,
1383: };
1384:
1.1.1.8 root 1385: static QEMUMachine ss4_machine = {
1.1.1.7 root 1386: .name = "SS-4",
1387: .desc = "Sun4m platform, SPARCstation 4",
1388: .init = ss4_init,
1389: .use_scsi = 1,
1390: };
1391:
1.1.1.8 root 1392: static QEMUMachine scls_machine = {
1.1.1.7 root 1393: .name = "SPARCClassic",
1394: .desc = "Sun4m platform, SPARCClassic",
1395: .init = scls_init,
1396: .use_scsi = 1,
1397: };
1398:
1.1.1.8 root 1399: static QEMUMachine sbook_machine = {
1.1.1.7 root 1400: .name = "SPARCbook",
1401: .desc = "Sun4m platform, SPARCbook",
1402: .init = sbook_init,
1403: .use_scsi = 1,
1.1.1.6 root 1404: };
1405:
1406: static const struct sun4d_hwdef sun4d_hwdefs[] = {
1407: /* SS-1000 */
1408: {
1409: .iounit_bases = {
1410: 0xfe0200000ULL,
1411: 0xfe1200000ULL,
1412: 0xfe2200000ULL,
1413: 0xfe3200000ULL,
1414: -1,
1415: },
1416: .tcx_base = 0x820000000ULL,
1417: .slavio_base = 0xf00000000ULL,
1418: .ms_kb_base = 0xf00240000ULL,
1419: .serial_base = 0xf00200000ULL,
1420: .nvram_base = 0xf00280000ULL,
1421: .counter_base = 0xf00300000ULL,
1422: .espdma_base = 0x800081000ULL,
1423: .esp_base = 0x800080000ULL,
1424: .ledma_base = 0x800040000ULL,
1425: .le_base = 0x800060000ULL,
1426: .sbi_base = 0xf02800000ULL,
1.1.1.7 root 1427: .nvram_machine_id = 0x80,
1428: .machine_id = ss1000_id,
1.1.1.6 root 1429: .iounit_version = 0x03000000,
1.1.1.7 root 1430: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1431: .default_cpu_model = "TI SuperSparc II",
1432: },
1433: /* SS-2000 */
1434: {
1435: .iounit_bases = {
1436: 0xfe0200000ULL,
1437: 0xfe1200000ULL,
1438: 0xfe2200000ULL,
1439: 0xfe3200000ULL,
1440: 0xfe4200000ULL,
1441: },
1442: .tcx_base = 0x820000000ULL,
1443: .slavio_base = 0xf00000000ULL,
1444: .ms_kb_base = 0xf00240000ULL,
1445: .serial_base = 0xf00200000ULL,
1446: .nvram_base = 0xf00280000ULL,
1447: .counter_base = 0xf00300000ULL,
1448: .espdma_base = 0x800081000ULL,
1449: .esp_base = 0x800080000ULL,
1450: .ledma_base = 0x800040000ULL,
1451: .le_base = 0x800060000ULL,
1452: .sbi_base = 0xf02800000ULL,
1.1.1.7 root 1453: .nvram_machine_id = 0x80,
1454: .machine_id = ss2000_id,
1.1.1.6 root 1455: .iounit_version = 0x03000000,
1.1.1.7 root 1456: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1457: .default_cpu_model = "TI SuperSparc II",
1458: },
1459: };
1460:
1.1.1.10 root 1461: static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1462: {
1463: DeviceState *dev;
1464: SysBusDevice *s;
1465: unsigned int i;
1466:
1467: dev = qdev_create(NULL, "sbi");
1468: qdev_init_nofail(dev);
1469:
1470: s = sysbus_from_qdev(dev);
1471:
1472: for (i = 0; i < MAX_CPUS; i++) {
1473: sysbus_connect_irq(s, i, *parent_irq[i]);
1474: }
1475:
1476: sysbus_mmio_map(s, 0, addr);
1477:
1478: return dev;
1479: }
1480:
1.1.1.7 root 1481: static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1.1.1.6 root 1482: const char *boot_device,
1.1.1.7 root 1483: const char *kernel_filename,
1.1.1.6 root 1484: const char *kernel_cmdline,
1485: const char *initrd_filename, const char *cpu_model)
1486: {
1487: unsigned int i;
1.1.1.10 root 1488: void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1489: qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1.1.1.8 root 1490: espdma_irq, ledma_irq;
1.1.1.12! root 1491: qemu_irq esp_reset, dma_enable;
1.1.1.7 root 1492: unsigned long kernel_size;
1493: void *fw_cfg;
1.1.1.10 root 1494: DeviceState *dev;
1.1.1.6 root 1495:
1496: /* init CPUs */
1497: if (!cpu_model)
1498: cpu_model = hwdef->default_cpu_model;
1499:
1.1.1.8 root 1500: for(i = 0; i < smp_cpus; i++) {
1.1.1.11 root 1501: cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1.1.1.6 root 1502: }
1503:
1504: for (i = smp_cpus; i < MAX_CPUS; i++)
1505: cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1506:
1.1.1.8 root 1507: /* set up devices */
1508: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.6 root 1509:
1.1.1.8 root 1510: prom_init(hwdef->slavio_base, bios_name);
1.1.1.6 root 1511:
1.1.1.10 root 1512: dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1513:
1514: for (i = 0; i < 32; i++) {
1515: sbi_irq[i] = qdev_get_gpio_in(dev, i);
1516: }
1517: for (i = 0; i < MAX_CPUS; i++) {
1518: sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1519: }
1.1.1.6 root 1520:
1521: for (i = 0; i < MAX_IOUNITS; i++)
1522: if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1523: iounits[i] = iommu_init(hwdef->iounit_bases[i],
1524: hwdef->iounit_version,
1.1.1.10 root 1525: sbi_irq[0]);
1.1.1.6 root 1526:
1.1.1.10 root 1527: espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1.1.1.12! root 1528: iounits[0], &espdma_irq, 0);
1.1.1.6 root 1529:
1.1.1.12! root 1530: /* should be lebuffer instead */
1.1.1.10 root 1531: ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1.1.1.12! root 1532: iounits[0], &ledma_irq, 0);
1.1.1.6 root 1533:
1534: if (graphic_depth != 8 && graphic_depth != 24) {
1535: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1536: exit (1);
1537: }
1.1.1.10 root 1538: tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1.1.1.8 root 1539: graphic_depth);
1.1.1.6 root 1540:
1.1.1.10 root 1541: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1.1.1.6 root 1542:
1.1.1.10 root 1543: nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1.1.1.6 root 1544:
1.1.1.10 root 1545: slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1.1.1.6 root 1546:
1.1.1.10 root 1547: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1.1.1.8 root 1548: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1.1.6 root 1549: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1550: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1.1.1.10 root 1551: escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1.1.1.7 root 1552: serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1.1.1.6 root 1553:
1554: if (drive_get_max_bus(IF_SCSI) > 0) {
1555: fprintf(stderr, "qemu: too many SCSI bus\n");
1556: exit(1);
1557: }
1558:
1.1.1.8 root 1559: esp_init(hwdef->esp_base, 2,
1560: espdma_memory_read, espdma_memory_write,
1.1.1.12! root 1561: espdma, espdma_irq, &esp_reset, &dma_enable);
! 1562:
! 1563: qdev_connect_gpio_out(espdma, 0, esp_reset);
! 1564: qdev_connect_gpio_out(espdma, 1, dma_enable);
1.1.1.6 root 1565:
1.1.1.7 root 1566: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1567: RAM_size);
1.1.1.6 root 1568:
1569: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1570: boot_device, RAM_size, kernel_size, graphic_width,
1.1.1.7 root 1571: graphic_height, graphic_depth, hwdef->nvram_machine_id,
1572: "Sun4d");
1573:
1574: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1575: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1576: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1577: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1.1.1.8 root 1578: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1579: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1580: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1581: if (kernel_cmdline) {
1582: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1.1.1.10 root 1583: pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1.1.1.11 root 1584: fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1585: (uint8_t*)strdup(kernel_cmdline),
1586: strlen(kernel_cmdline) + 1);
1.1.1.8 root 1587: } else {
1588: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1589: }
1590: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1591: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1592: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1593: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.6 root 1594: }
1595:
1596: /* SPARCserver 1000 hardware initialisation */
1.1.1.8 root 1597: static void ss1000_init(ram_addr_t RAM_size,
1.1.1.7 root 1598: const char *boot_device,
1.1.1.6 root 1599: const char *kernel_filename, const char *kernel_cmdline,
1600: const char *initrd_filename, const char *cpu_model)
1601: {
1.1.1.7 root 1602: sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1603: kernel_cmdline, initrd_filename, cpu_model);
1.1 root 1604: }
1605:
1.1.1.6 root 1606: /* SPARCcenter 2000 hardware initialisation */
1.1.1.8 root 1607: static void ss2000_init(ram_addr_t RAM_size,
1.1.1.7 root 1608: const char *boot_device,
1.1.1.6 root 1609: const char *kernel_filename, const char *kernel_cmdline,
1610: const char *initrd_filename, const char *cpu_model)
1611: {
1.1.1.7 root 1612: sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1613: kernel_cmdline, initrd_filename, cpu_model);
1614: }
1615:
1.1.1.8 root 1616: static QEMUMachine ss1000_machine = {
1.1.1.7 root 1617: .name = "SS-1000",
1618: .desc = "Sun4d platform, SPARCserver 1000",
1619: .init = ss1000_init,
1620: .use_scsi = 1,
1621: .max_cpus = 8,
1.1.1.6 root 1622: };
1623:
1.1.1.8 root 1624: static QEMUMachine ss2000_machine = {
1.1.1.7 root 1625: .name = "SS-2000",
1626: .desc = "Sun4d platform, SPARCcenter 2000",
1627: .init = ss2000_init,
1628: .use_scsi = 1,
1629: .max_cpus = 20,
1630: };
1631:
1632: static const struct sun4c_hwdef sun4c_hwdefs[] = {
1633: /* SS-2 */
1634: {
1635: .iommu_base = 0xf8000000,
1636: .tcx_base = 0xfe000000,
1637: .slavio_base = 0xf6000000,
1638: .intctl_base = 0xf5000000,
1639: .counter_base = 0xf3000000,
1640: .ms_kb_base = 0xf0000000,
1641: .serial_base = 0xf1000000,
1642: .nvram_base = 0xf2000000,
1643: .fd_base = 0xf7200000,
1644: .dma_base = 0xf8400000,
1645: .esp_base = 0xf8800000,
1646: .le_base = 0xf8c00000,
1647: .aux1_base = 0xf7400003,
1648: .nvram_machine_id = 0x55,
1649: .machine_id = ss2_id,
1650: .max_mem = 0x10000000,
1651: .default_cpu_model = "Cypress CY7C601",
1652: },
1653: };
1654:
1.1.1.10 root 1655: static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1656: qemu_irq *parent_irq)
1657: {
1658: DeviceState *dev;
1659: SysBusDevice *s;
1660: unsigned int i;
1661:
1662: dev = qdev_create(NULL, "sun4c_intctl");
1663: qdev_init_nofail(dev);
1664:
1665: s = sysbus_from_qdev(dev);
1666:
1667: for (i = 0; i < MAX_PILS; i++) {
1668: sysbus_connect_irq(s, i, parent_irq[i]);
1669: }
1670: sysbus_mmio_map(s, 0, addr);
1671:
1672: return dev;
1673: }
1674:
1.1.1.7 root 1675: static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1676: const char *boot_device,
1677: const char *kernel_filename,
1678: const char *kernel_cmdline,
1679: const char *initrd_filename, const char *cpu_model)
1680: {
1.1.1.8 root 1681: void *iommu, *espdma, *ledma, *nvram;
1.1.1.10 root 1682: qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1.1.1.12! root 1683: qemu_irq esp_reset, dma_enable;
1.1.1.8 root 1684: qemu_irq fdc_tc;
1.1.1.7 root 1685: unsigned long kernel_size;
1.1.1.10 root 1686: DriveInfo *fd[MAX_FD];
1.1.1.7 root 1687: void *fw_cfg;
1.1.1.10 root 1688: DeviceState *dev;
1689: unsigned int i;
1.1.1.7 root 1690:
1691: /* init CPU */
1692: if (!cpu_model)
1693: cpu_model = hwdef->default_cpu_model;
1694:
1.1.1.11 root 1695: cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1.1.1.7 root 1696:
1.1.1.8 root 1697: /* set up devices */
1698: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.7 root 1699:
1.1.1.8 root 1700: prom_init(hwdef->slavio_base, bios_name);
1.1.1.7 root 1701:
1.1.1.10 root 1702: dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1703:
1704: for (i = 0; i < 8; i++) {
1705: slavio_irq[i] = qdev_get_gpio_in(dev, i);
1706: }
1.1.1.7 root 1707:
1708: iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1.1.1.10 root 1709: slavio_irq[1]);
1.1.1.7 root 1710:
1.1.1.10 root 1711: espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1.1.1.12! root 1712: iommu, &espdma_irq, 0);
1.1.1.7 root 1713:
1714: ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1.1.1.12! root 1715: slavio_irq[3], iommu, &ledma_irq, 1);
1.1.1.7 root 1716:
1717: if (graphic_depth != 8 && graphic_depth != 24) {
1718: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1719: exit (1);
1720: }
1.1.1.10 root 1721: tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1.1.1.8 root 1722: graphic_depth);
1.1.1.7 root 1723:
1.1.1.10 root 1724: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1.1.1.7 root 1725:
1.1.1.10 root 1726: nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1.1.1.7 root 1727:
1.1.1.10 root 1728: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1.1.1.8 root 1729: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1.1.7 root 1730: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1731: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1.1.1.10 root 1732: escc_init(hwdef->serial_base, slavio_irq[1],
1733: slavio_irq[1], serial_hds[0], serial_hds[1],
1.1.1.7 root 1734: ESCC_CLOCK, 1);
1735:
1.1.1.10 root 1736: slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1.1.1.7 root 1737:
1738: if (hwdef->fd_base != (target_phys_addr_t)-1) {
1739: /* there is zero or one floppy drive */
1740: memset(fd, 0, sizeof(fd));
1.1.1.10 root 1741: fd[0] = drive_get(IF_FLOPPY, 0, 0);
1742: sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1.1.1.8 root 1743: &fdc_tc);
1.1.1.7 root 1744: }
1745:
1746: if (drive_get_max_bus(IF_SCSI) > 0) {
1747: fprintf(stderr, "qemu: too many SCSI bus\n");
1748: exit(1);
1749: }
1750:
1.1.1.8 root 1751: esp_init(hwdef->esp_base, 2,
1752: espdma_memory_read, espdma_memory_write,
1.1.1.12! root 1753: espdma, espdma_irq, &esp_reset, &dma_enable);
! 1754:
! 1755: qdev_connect_gpio_out(espdma, 0, esp_reset);
! 1756: qdev_connect_gpio_out(espdma, 1, dma_enable);
1.1.1.7 root 1757:
1758: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1759: RAM_size);
1760:
1761: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1762: boot_device, RAM_size, kernel_size, graphic_width,
1763: graphic_height, graphic_depth, hwdef->nvram_machine_id,
1764: "Sun4c");
1765:
1766: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1767: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1768: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1769: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1.1.1.8 root 1770: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1771: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1772: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1773: if (kernel_cmdline) {
1774: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1.1.1.10 root 1775: pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1.1.1.11 root 1776: fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1777: (uint8_t*)strdup(kernel_cmdline),
1778: strlen(kernel_cmdline) + 1);
1.1.1.8 root 1779: } else {
1780: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1781: }
1782: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1783: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1784: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1785: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.7 root 1786: }
1787:
1788: /* SPARCstation 2 hardware initialisation */
1.1.1.8 root 1789: static void ss2_init(ram_addr_t RAM_size,
1.1.1.7 root 1790: const char *boot_device,
1791: const char *kernel_filename, const char *kernel_cmdline,
1792: const char *initrd_filename, const char *cpu_model)
1793: {
1794: sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1795: kernel_cmdline, initrd_filename, cpu_model);
1796: }
1797:
1.1.1.8 root 1798: static QEMUMachine ss2_machine = {
1.1.1.7 root 1799: .name = "SS-2",
1800: .desc = "Sun4c platform, SPARCstation 2",
1801: .init = ss2_init,
1802: .use_scsi = 1,
1.1 root 1803: };
1.1.1.8 root 1804:
1805: static void ss2_machine_init(void)
1806: {
1807: qemu_register_machine(&ss5_machine);
1808: qemu_register_machine(&ss10_machine);
1809: qemu_register_machine(&ss600mp_machine);
1810: qemu_register_machine(&ss20_machine);
1811: qemu_register_machine(&voyager_machine);
1812: qemu_register_machine(&ss_lx_machine);
1813: qemu_register_machine(&ss4_machine);
1814: qemu_register_machine(&scls_machine);
1815: qemu_register_machine(&sbook_machine);
1816: qemu_register_machine(&ss1000_machine);
1817: qemu_register_machine(&ss2000_machine);
1818: qemu_register_machine(&ss2_machine);
1819: }
1820:
1821: machine_init(ss2_machine_init);
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