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1.1 root 1: /*
1.1.1.6 root 2: * QEMU Sun4m & Sun4d & Sun4c System Emulator
3: *
1.1 root 4: * Copyright (c) 2003-2005 Fabrice Bellard
1.1.1.6 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.8 root 24: #include "sysbus.h"
1.1.1.6 root 25: #include "qemu-timer.h"
26: #include "sun4m.h"
27: #include "nvram.h"
28: #include "sparc32_dma.h"
29: #include "fdc.h"
30: #include "sysemu.h"
31: #include "net.h"
32: #include "boards.h"
33: #include "firmware_abi.h"
1.1.1.10 root 34: #include "esp.h"
1.1.1.7 root 35: #include "pc.h"
36: #include "isa.h"
37: #include "fw_cfg.h"
38: #include "escc.h"
1.1.1.11 root 39: #include "empty_slot.h"
1.1.1.10 root 40: #include "qdev-addr.h"
41: #include "loader.h"
42: #include "elf.h"
1.1.1.12 root 43: #include "blockdev.h"
44: #include "trace.h"
1.1.1.6 root 45:
46: /*
47: * Sun4m architecture was used in the following machines:
48: *
49: * SPARCserver 6xxMP/xx
1.1.1.7 root 50: * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51: * SPARCclassic X (4/10)
1.1.1.6 root 52: * SPARCstation LX/ZX (4/30)
53: * SPARCstation Voyager
54: * SPARCstation 10/xx, SPARCserver 10/xx
55: * SPARCstation 5, SPARCserver 5
56: * SPARCstation 20/xx, SPARCserver 20
57: * SPARCstation 4
58: *
59: * Sun4d architecture was used in the following machines:
60: *
61: * SPARCcenter 2000
62: * SPARCserver 1000
63: *
64: * Sun4c architecture was used in the following machines:
65: * SPARCstation 1/1+, SPARCserver 1/1+
66: * SPARCstation SLC
67: * SPARCstation IPC
68: * SPARCstation ELC
69: * SPARCstation IPX
70: *
71: * See for example: http://www.sunhelp.org/faq/sunref1.html
72: */
73:
1.1 root 74: #define KERNEL_LOAD_ADDR 0x00004000
75: #define CMDLINE_ADDR 0x007ff000
76: #define INITRD_LOAD_ADDR 0x00800000
1.1.1.7 root 77: #define PROM_SIZE_MAX (1024 * 1024)
1.1.1.6 root 78: #define PROM_VADDR 0xffd00000
79: #define PROM_FILENAME "openbios-sparc32"
1.1.1.7 root 80: #define CFG_ADDR 0xd00000510ULL
81: #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82:
1.1.1.2 root 83: #define MAX_CPUS 16
1.1.1.6 root 84: #define MAX_PILS 16
1.1.1.11 root 85: #define MAX_VSIMMS 4
1.1.1.6 root 86:
1.1.1.7 root 87: #define ESCC_CLOCK 4915200
88:
89: struct sun4m_hwdef {
1.1.1.11 root 90: target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
1.1.1.6 root 91: target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92: target_phys_addr_t serial_base, fd_base;
1.1.1.11 root 93: target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
1.1.1.7 root 94: target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
1.1.1.11 root 95: target_phys_addr_t bpp_base, dbri_base, sx_base;
96: struct {
97: target_phys_addr_t reg_base, vram_base;
98: } vsimm[MAX_VSIMMS];
1.1.1.6 root 99: target_phys_addr_t ecc_base;
100: uint64_t max_mem;
101: const char * const default_cpu_model;
1.1.1.14! root 102: uint32_t ecc_version;
! 103: uint32_t iommu_version;
! 104: uint16_t machine_id;
! 105: uint8_t nvram_machine_id;
1.1.1.6 root 106: };
107:
108: #define MAX_IOUNITS 5
109:
110: struct sun4d_hwdef {
111: target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112: target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113: target_phys_addr_t serial_base;
114: target_phys_addr_t espdma_base, esp_base;
115: target_phys_addr_t ledma_base, le_base;
116: target_phys_addr_t tcx_base;
117: target_phys_addr_t sbi_base;
118: uint64_t max_mem;
119: const char * const default_cpu_model;
1.1.1.14! root 120: uint32_t iounit_version;
! 121: uint16_t machine_id;
! 122: uint8_t nvram_machine_id;
1.1.1.6 root 123: };
1.1 root 124:
1.1.1.7 root 125: struct sun4c_hwdef {
126: target_phys_addr_t iommu_base, slavio_base;
127: target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128: target_phys_addr_t serial_base, fd_base;
129: target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130: target_phys_addr_t tcx_base, aux1_base;
131: uint64_t max_mem;
132: const char * const default_cpu_model;
1.1.1.14! root 133: uint32_t iommu_version;
! 134: uint16_t machine_id;
! 135: uint8_t nvram_machine_id;
1.1.1.7 root 136: };
1.1 root 137:
138: int DMA_get_channel_mode (int nchan)
139: {
140: return 0;
141: }
142: int DMA_read_memory (int nchan, void *buf, int pos, int size)
143: {
144: return 0;
145: }
146: int DMA_write_memory (int nchan, void *buf, int pos, int size)
147: {
148: return 0;
149: }
150: void DMA_hold_DREQ (int nchan) {}
151: void DMA_release_DREQ (int nchan) {}
152: void DMA_schedule(int nchan) {}
1.1.1.11 root 153:
154: void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155: {
156: }
157:
1.1 root 158: void DMA_register_channel (int nchan,
159: DMA_transfer_handler transfer_handler,
160: void *opaque)
161: {
162: }
163:
1.1.1.8 root 164: static int fw_cfg_boot_set(void *opaque, const char *boot_device)
1.1.1.7 root 165: {
1.1.1.8 root 166: fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
1.1.1.7 root 167: return 0;
168: }
1.1 root 169:
1.1.1.11 root 170: static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171: const char *cmdline, const char *boot_devices,
172: ram_addr_t RAM_size, uint32_t kernel_size,
1.1.1.6 root 173: int width, int height, int depth,
1.1.1.7 root 174: int nvram_machine_id, const char *arch)
1.1 root 175: {
1.1.1.6 root 176: unsigned int i;
177: uint32_t start, end;
178: uint8_t image[0x1ff0];
179: struct OpenBIOS_nvpart_v1 *part_header;
180:
181: memset(image, '\0', sizeof(image));
1.1 root 182:
1.1.1.8 root 183: start = 0;
1.1.1.6 root 184:
185: // OpenBIOS nvram variables
186: // Variable partition
187: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188: part_header->signature = OPENBIOS_PART_SYSTEM;
1.1.1.7 root 189: pstrcpy(part_header->name, sizeof(part_header->name), "system");
1.1.1.6 root 190:
191: end = start + sizeof(struct OpenBIOS_nvpart_v1);
192: for (i = 0; i < nb_prom_envs; i++)
193: end = OpenBIOS_set_var(image, end, prom_envs[i]);
194:
195: // End marker
196: image[end++] = '\0';
197:
198: end = start + ((end - start + 15) & ~15);
199: OpenBIOS_finish_partition(part_header, end - start);
200:
201: // free partition
202: start = end;
203: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204: part_header->signature = OPENBIOS_PART_FREE;
1.1.1.7 root 205: pstrcpy(part_header->name, sizeof(part_header->name), "free");
1.1.1.6 root 206:
207: end = 0x1fd0;
208: OpenBIOS_finish_partition(part_header, end - start);
209:
1.1.1.7 root 210: Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211: nvram_machine_id);
1.1.1.6 root 212:
213: for (i = 0; i < sizeof(image); i++)
214: m48t59_write(nvram, i, image[i]);
1.1 root 215: }
216:
1.1.1.10 root 217: static DeviceState *slavio_intctl;
1.1 root 218:
1.1.1.14! root 219: void sun4m_pic_info(Monitor *mon)
1.1 root 220: {
1.1.1.6 root 221: if (slavio_intctl)
1.1.1.8 root 222: slavio_pic_info(mon, slavio_intctl);
1.1 root 223: }
224:
1.1.1.14! root 225: void sun4m_irq_info(Monitor *mon)
1.1 root 226: {
1.1.1.6 root 227: if (slavio_intctl)
1.1.1.8 root 228: slavio_irq_info(mon, slavio_intctl);
1.1 root 229: }
230:
1.1.1.6 root 231: void cpu_check_irqs(CPUState *env)
1.1 root 232: {
1.1.1.6 root 233: if (env->pil_in && (env->interrupt_index == 0 ||
234: (env->interrupt_index & ~15) == TT_EXTINT)) {
235: unsigned int i;
236:
237: for (i = 15; i > 0; i--) {
238: if (env->pil_in & (1 << i)) {
239: int old_interrupt = env->interrupt_index;
240:
241: env->interrupt_index = TT_EXTINT | i;
1.1.1.7 root 242: if (old_interrupt != env->interrupt_index) {
1.1.1.12 root 243: trace_sun4m_cpu_interrupt(i);
1.1.1.6 root 244: cpu_interrupt(env, CPU_INTERRUPT_HARD);
1.1.1.7 root 245: }
1.1.1.6 root 246: break;
247: }
248: }
249: } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
1.1.1.12 root 250: trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
1.1.1.6 root 251: env->interrupt_index = 0;
252: cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253: }
1.1 root 254: }
255:
1.1.1.13 root 256: static void cpu_kick_irq(CPUState *env)
257: {
258: env->halted = 0;
259: cpu_check_irqs(env);
260: qemu_cpu_kick(env);
261: }
262:
1.1.1.6 root 263: static void cpu_set_irq(void *opaque, int irq, int level)
1.1.1.4 root 264: {
1.1.1.6 root 265: CPUState *env = opaque;
266:
267: if (level) {
1.1.1.12 root 268: trace_sun4m_cpu_set_irq_raise(irq);
1.1.1.6 root 269: env->pil_in |= 1 << irq;
1.1.1.13 root 270: cpu_kick_irq(env);
1.1.1.6 root 271: } else {
1.1.1.12 root 272: trace_sun4m_cpu_set_irq_lower(irq);
1.1.1.6 root 273: env->pil_in &= ~(1 << irq);
274: cpu_check_irqs(env);
275: }
1.1.1.4 root 276: }
277:
1.1.1.6 root 278: static void dummy_cpu_set_irq(void *opaque, int irq, int level)
1.1.1.2 root 279: {
280: }
281:
282: static void main_cpu_reset(void *opaque)
283: {
284: CPUState *env = opaque;
1.1.1.6 root 285:
1.1.1.2 root 286: cpu_reset(env);
1.1.1.6 root 287: env->halted = 0;
1.1.1.2 root 288: }
289:
1.1.1.6 root 290: static void secondary_cpu_reset(void *opaque)
1.1 root 291: {
1.1.1.6 root 292: CPUState *env = opaque;
293:
294: cpu_reset(env);
295: env->halted = 1;
296: }
297:
1.1.1.7 root 298: static void cpu_halt_signal(void *opaque, int irq, int level)
299: {
300: if (level && cpu_single_env)
301: cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
302: }
303:
1.1.1.11 root 304: static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
305: {
306: return addr - 0xf0000000ULL;
307: }
308:
1.1.1.6 root 309: static unsigned long sun4m_load_kernel(const char *kernel_filename,
1.1.1.7 root 310: const char *initrd_filename,
311: ram_addr_t RAM_size)
1.1.1.6 root 312: {
313: int linux_boot;
1.1 root 314: unsigned int i;
1.1.1.6 root 315: long initrd_size, kernel_size;
1.1.1.10 root 316: uint8_t *ptr;
1.1 root 317:
318: linux_boot = (kernel_filename != NULL);
319:
1.1.1.6 root 320: kernel_size = 0;
321: if (linux_boot) {
1.1.1.10 root 322: int bswap_needed;
323:
324: #ifdef BSWAP_NEEDED
325: bswap_needed = 1;
326: #else
327: bswap_needed = 0;
328: #endif
1.1.1.11 root 329: kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
330: NULL, NULL, NULL, 1, ELF_MACHINE, 0);
1.1.1.6 root 331: if (kernel_size < 0)
1.1.1.7 root 332: kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
1.1.1.10 root 333: RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
334: TARGET_PAGE_SIZE);
1.1.1.6 root 335: if (kernel_size < 0)
1.1.1.7 root 336: kernel_size = load_image_targphys(kernel_filename,
337: KERNEL_LOAD_ADDR,
338: RAM_size - KERNEL_LOAD_ADDR);
1.1.1.6 root 339: if (kernel_size < 0) {
340: fprintf(stderr, "qemu: could not load kernel '%s'\n",
341: kernel_filename);
342: exit(1);
343: }
344:
345: /* load initrd */
346: initrd_size = 0;
347: if (initrd_filename) {
1.1.1.7 root 348: initrd_size = load_image_targphys(initrd_filename,
349: INITRD_LOAD_ADDR,
350: RAM_size - INITRD_LOAD_ADDR);
1.1.1.6 root 351: if (initrd_size < 0) {
352: fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
353: initrd_filename);
354: exit(1);
355: }
356: }
357: if (initrd_size > 0) {
358: for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
1.1.1.10 root 359: ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
360: if (ldl_p(ptr) == 0x48647253) { // HdrS
361: stl_p(ptr + 16, INITRD_LOAD_ADDR);
362: stl_p(ptr + 20, initrd_size);
1.1.1.6 root 363: break;
364: }
365: }
366: }
367: }
368: return kernel_size;
369: }
370:
1.1.1.10 root 371: static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
372: {
373: DeviceState *dev;
374: SysBusDevice *s;
375:
376: dev = qdev_create(NULL, "iommu");
377: qdev_prop_set_uint32(dev, "version", version);
378: qdev_init_nofail(dev);
379: s = sysbus_from_qdev(dev);
380: sysbus_connect_irq(s, 0, irq);
381: sysbus_mmio_map(s, 0, addr);
382:
383: return s;
384: }
385:
386: static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1.1.1.12 root 387: void *iommu, qemu_irq *dev_irq, int is_ledma)
1.1.1.10 root 388: {
389: DeviceState *dev;
390: SysBusDevice *s;
391:
392: dev = qdev_create(NULL, "sparc32_dma");
393: qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
1.1.1.12 root 394: qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
1.1.1.10 root 395: qdev_init_nofail(dev);
396: s = sysbus_from_qdev(dev);
397: sysbus_connect_irq(s, 0, parent_irq);
398: *dev_irq = qdev_get_gpio_in(dev, 0);
399: sysbus_mmio_map(s, 0, daddr);
400:
401: return s;
402: }
403:
1.1.1.8 root 404: static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
1.1.1.10 root 405: void *dma_opaque, qemu_irq irq)
1.1.1.8 root 406: {
407: DeviceState *dev;
408: SysBusDevice *s;
1.1.1.10 root 409: qemu_irq reset;
1.1.1.8 root 410:
411: qemu_check_nic_model(&nd_table[0], "lance");
412:
413: dev = qdev_create(NULL, "lance");
1.1.1.10 root 414: qdev_set_nic_properties(dev, nd);
1.1.1.9 root 415: qdev_prop_set_ptr(dev, "dma", dma_opaque);
1.1.1.10 root 416: qdev_init_nofail(dev);
1.1.1.8 root 417: s = sysbus_from_qdev(dev);
418: sysbus_mmio_map(s, 0, leaddr);
419: sysbus_connect_irq(s, 0, irq);
1.1.1.10 root 420: reset = qdev_get_gpio_in(dev, 0);
421: qdev_connect_gpio_out(dma_opaque, 0, reset);
422: }
423:
424: static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
425: target_phys_addr_t addrg,
426: qemu_irq **parent_irq)
427: {
428: DeviceState *dev;
429: SysBusDevice *s;
430: unsigned int i, j;
431:
432: dev = qdev_create(NULL, "slavio_intctl");
433: qdev_init_nofail(dev);
434:
435: s = sysbus_from_qdev(dev);
436:
437: for (i = 0; i < MAX_CPUS; i++) {
438: for (j = 0; j < MAX_PILS; j++) {
439: sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
440: }
441: }
442: sysbus_mmio_map(s, 0, addrg);
443: for (i = 0; i < MAX_CPUS; i++) {
444: sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
445: }
446:
447: return dev;
448: }
449:
450: #define SYS_TIMER_OFFSET 0x10000ULL
451: #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
452:
453: static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
454: qemu_irq *cpu_irqs, unsigned int num_cpus)
455: {
456: DeviceState *dev;
457: SysBusDevice *s;
458: unsigned int i;
459:
460: dev = qdev_create(NULL, "slavio_timer");
461: qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
462: qdev_init_nofail(dev);
463: s = sysbus_from_qdev(dev);
464: sysbus_connect_irq(s, 0, master_irq);
465: sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
466:
467: for (i = 0; i < MAX_CPUS; i++) {
468: sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
469: sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
470: }
471: }
472:
473: #define MISC_LEDS 0x01600000
474: #define MISC_CFG 0x01800000
475: #define MISC_DIAG 0x01a00000
476: #define MISC_MDM 0x01b00000
477: #define MISC_SYS 0x01f00000
478:
479: static void slavio_misc_init(target_phys_addr_t base,
480: target_phys_addr_t aux1_base,
481: target_phys_addr_t aux2_base, qemu_irq irq,
482: qemu_irq fdc_tc)
483: {
484: DeviceState *dev;
485: SysBusDevice *s;
486:
487: dev = qdev_create(NULL, "slavio_misc");
488: qdev_init_nofail(dev);
489: s = sysbus_from_qdev(dev);
490: if (base) {
491: /* 8 bit registers */
492: /* Slavio control */
493: sysbus_mmio_map(s, 0, base + MISC_CFG);
494: /* Diagnostics */
495: sysbus_mmio_map(s, 1, base + MISC_DIAG);
496: /* Modem control */
497: sysbus_mmio_map(s, 2, base + MISC_MDM);
498: /* 16 bit registers */
499: /* ss600mp diag LEDs */
500: sysbus_mmio_map(s, 3, base + MISC_LEDS);
501: /* 32 bit registers */
502: /* System control */
503: sysbus_mmio_map(s, 4, base + MISC_SYS);
504: }
505: if (aux1_base) {
506: /* AUX 1 (Misc System Functions) */
507: sysbus_mmio_map(s, 5, aux1_base);
508: }
509: if (aux2_base) {
510: /* AUX 2 (Software Powerdown Control) */
511: sysbus_mmio_map(s, 6, aux2_base);
512: }
513: sysbus_connect_irq(s, 0, irq);
514: sysbus_connect_irq(s, 1, fdc_tc);
515: qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
516: }
517:
518: static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
519: {
520: DeviceState *dev;
521: SysBusDevice *s;
522:
523: dev = qdev_create(NULL, "eccmemctl");
524: qdev_prop_set_uint32(dev, "version", version);
525: qdev_init_nofail(dev);
526: s = sysbus_from_qdev(dev);
527: sysbus_connect_irq(s, 0, irq);
528: sysbus_mmio_map(s, 0, base);
529: if (version == 0) { // SS-600MP only
530: sysbus_mmio_map(s, 1, base + 0x1000);
531: }
532: }
533:
534: static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
535: {
536: DeviceState *dev;
537: SysBusDevice *s;
538:
539: dev = qdev_create(NULL, "apc");
540: qdev_init_nofail(dev);
541: s = sysbus_from_qdev(dev);
542: /* Power management (APC) XXX: not a Slavio device */
543: sysbus_mmio_map(s, 0, power_base);
544: sysbus_connect_irq(s, 0, cpu_halt);
545: }
546:
547: static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
548: int height, int depth)
549: {
550: DeviceState *dev;
551: SysBusDevice *s;
552:
553: dev = qdev_create(NULL, "SUNW,tcx");
554: qdev_prop_set_taddr(dev, "addr", addr);
555: qdev_prop_set_uint32(dev, "vram_size", vram_size);
556: qdev_prop_set_uint16(dev, "width", width);
557: qdev_prop_set_uint16(dev, "height", height);
558: qdev_prop_set_uint16(dev, "depth", depth);
559: qdev_init_nofail(dev);
560: s = sysbus_from_qdev(dev);
561: /* 8-bit plane */
562: sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
563: /* DAC */
564: sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
565: /* TEC (dummy) */
566: sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
567: /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
568: sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
569: if (depth == 24) {
570: /* 24-bit plane */
571: sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
572: /* Control plane */
573: sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
574: } else {
575: /* THC 8 bit (dummy) */
576: sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
577: }
1.1.1.8 root 578: }
579:
580: /* NCR89C100/MACIO Internal ID register */
581: static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
582:
583: static void idreg_init(target_phys_addr_t addr)
584: {
585: DeviceState *dev;
586: SysBusDevice *s;
587:
588: dev = qdev_create(NULL, "macio_idreg");
1.1.1.10 root 589: qdev_init_nofail(dev);
1.1.1.8 root 590: s = sysbus_from_qdev(dev);
591:
592: sysbus_mmio_map(s, 0, addr);
593: cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
594: }
595:
1.1.1.14! root 596: typedef struct IDRegState {
! 597: SysBusDevice busdev;
! 598: MemoryRegion mem;
! 599: } IDRegState;
! 600:
1.1.1.10 root 601: static int idreg_init1(SysBusDevice *dev)
1.1.1.8 root 602: {
1.1.1.14! root 603: IDRegState *s = FROM_SYSBUS(IDRegState, dev);
1.1.1.8 root 604:
1.1.1.14! root 605: memory_region_init_ram(&s->mem, NULL, "sun4m.idreg", sizeof(idreg_data));
! 606: memory_region_set_readonly(&s->mem, true);
! 607: sysbus_init_mmio_region(dev, &s->mem);
1.1.1.10 root 608: return 0;
1.1.1.8 root 609: }
610:
611: static SysBusDeviceInfo idreg_info = {
612: .init = idreg_init1,
613: .qdev.name = "macio_idreg",
1.1.1.14! root 614: .qdev.size = sizeof(IDRegState),
1.1.1.8 root 615: };
616:
617: static void idreg_register_devices(void)
618: {
619: sysbus_register_withprop(&idreg_info);
620: }
621:
622: device_init(idreg_register_devices);
623:
1.1.1.14! root 624: typedef struct AFXState {
! 625: SysBusDevice busdev;
! 626: MemoryRegion mem;
! 627: } AFXState;
! 628:
1.1.1.11 root 629: /* SS-5 TCX AFX register */
630: static void afx_init(target_phys_addr_t addr)
631: {
632: DeviceState *dev;
633: SysBusDevice *s;
634:
635: dev = qdev_create(NULL, "tcx_afx");
636: qdev_init_nofail(dev);
637: s = sysbus_from_qdev(dev);
638:
639: sysbus_mmio_map(s, 0, addr);
640: }
641:
642: static int afx_init1(SysBusDevice *dev)
643: {
1.1.1.14! root 644: AFXState *s = FROM_SYSBUS(AFXState, dev);
1.1.1.11 root 645:
1.1.1.14! root 646: memory_region_init_ram(&s->mem, NULL, "sun4m.afx", 4);
! 647: sysbus_init_mmio_region(dev, &s->mem);
1.1.1.11 root 648: return 0;
649: }
650:
651: static SysBusDeviceInfo afx_info = {
652: .init = afx_init1,
653: .qdev.name = "tcx_afx",
1.1.1.14! root 654: .qdev.size = sizeof(AFXState),
1.1.1.11 root 655: };
656:
657: static void afx_register_devices(void)
658: {
659: sysbus_register_withprop(&afx_info);
660: }
661:
662: device_init(afx_register_devices);
663:
1.1.1.14! root 664: typedef struct PROMState {
! 665: SysBusDevice busdev;
! 666: MemoryRegion prom;
! 667: } PROMState;
! 668:
1.1.1.8 root 669: /* Boot PROM (OpenBIOS) */
1.1.1.11 root 670: static uint64_t translate_prom_address(void *opaque, uint64_t addr)
671: {
672: target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
673: return addr + *base_addr - PROM_VADDR;
674: }
675:
1.1.1.8 root 676: static void prom_init(target_phys_addr_t addr, const char *bios_name)
677: {
678: DeviceState *dev;
679: SysBusDevice *s;
680: char *filename;
681: int ret;
682:
683: dev = qdev_create(NULL, "openprom");
1.1.1.10 root 684: qdev_init_nofail(dev);
1.1.1.8 root 685: s = sysbus_from_qdev(dev);
686:
687: sysbus_mmio_map(s, 0, addr);
688:
689: /* load boot prom */
690: if (bios_name == NULL) {
691: bios_name = PROM_FILENAME;
692: }
693: filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
694: if (filename) {
1.1.1.11 root 695: ret = load_elf(filename, translate_prom_address, &addr, NULL,
696: NULL, NULL, 1, ELF_MACHINE, 0);
1.1.1.8 root 697: if (ret < 0 || ret > PROM_SIZE_MAX) {
698: ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
699: }
1.1.1.14! root 700: g_free(filename);
1.1.1.8 root 701: } else {
702: ret = -1;
703: }
704: if (ret < 0 || ret > PROM_SIZE_MAX) {
705: fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
706: exit(1);
707: }
708: }
709:
1.1.1.10 root 710: static int prom_init1(SysBusDevice *dev)
1.1.1.8 root 711: {
1.1.1.14! root 712: PROMState *s = FROM_SYSBUS(PROMState, dev);
1.1.1.8 root 713:
1.1.1.14! root 714: memory_region_init_ram(&s->prom, NULL, "sun4m.prom", PROM_SIZE_MAX);
! 715: memory_region_set_readonly(&s->prom, true);
! 716: sysbus_init_mmio_region(dev, &s->prom);
1.1.1.10 root 717: return 0;
1.1.1.8 root 718: }
719:
720: static SysBusDeviceInfo prom_info = {
721: .init = prom_init1,
722: .qdev.name = "openprom",
1.1.1.14! root 723: .qdev.size = sizeof(PROMState),
1.1.1.8 root 724: .qdev.props = (Property[]) {
725: {/* end of property list */}
726: }
727: };
728:
729: static void prom_register_devices(void)
730: {
731: sysbus_register_withprop(&prom_info);
732: }
733:
734: device_init(prom_register_devices);
735:
736: typedef struct RamDevice
737: {
738: SysBusDevice busdev;
1.1.1.14! root 739: MemoryRegion ram;
1.1.1.10 root 740: uint64_t size;
1.1.1.8 root 741: } RamDevice;
742:
743: /* System RAM */
1.1.1.10 root 744: static int ram_init1(SysBusDevice *dev)
1.1.1.8 root 745: {
746: RamDevice *d = FROM_SYSBUS(RamDevice, dev);
747:
1.1.1.14! root 748: memory_region_init_ram(&d->ram, NULL, "sun4m.ram", d->size);
! 749: sysbus_init_mmio_region(dev, &d->ram);
1.1.1.10 root 750: return 0;
1.1.1.8 root 751: }
752:
753: static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
754: uint64_t max_mem)
755: {
756: DeviceState *dev;
757: SysBusDevice *s;
758: RamDevice *d;
759:
760: /* allocate RAM */
761: if ((uint64_t)RAM_size > max_mem) {
762: fprintf(stderr,
763: "qemu: Too much memory for this machine: %d, maximum %d\n",
764: (unsigned int)(RAM_size / (1024 * 1024)),
765: (unsigned int)(max_mem / (1024 * 1024)));
766: exit(1);
767: }
768: dev = qdev_create(NULL, "memory");
769: s = sysbus_from_qdev(dev);
770:
771: d = FROM_SYSBUS(RamDevice, s);
772: d->size = RAM_size;
1.1.1.10 root 773: qdev_init_nofail(dev);
1.1.1.8 root 774:
775: sysbus_mmio_map(s, 0, addr);
776: }
777:
778: static SysBusDeviceInfo ram_info = {
779: .init = ram_init1,
780: .qdev.name = "memory",
781: .qdev.size = sizeof(RamDevice),
782: .qdev.props = (Property[]) {
1.1.1.10 root 783: DEFINE_PROP_UINT64("size", RamDevice, size, 0),
784: DEFINE_PROP_END_OF_LIST(),
1.1.1.8 root 785: }
786: };
787:
788: static void ram_register_devices(void)
789: {
790: sysbus_register_withprop(&ram_info);
791: }
792:
793: device_init(ram_register_devices);
794:
1.1.1.11 root 795: static void cpu_devinit(const char *cpu_model, unsigned int id,
796: uint64_t prom_addr, qemu_irq **cpu_irqs)
1.1.1.8 root 797: {
798: CPUState *env;
799:
800: env = cpu_init(cpu_model);
801: if (!env) {
802: fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
803: exit(1);
804: }
805:
806: cpu_sparc_set_id(env, id);
807: if (id == 0) {
808: qemu_register_reset(main_cpu_reset, env);
809: } else {
810: qemu_register_reset(secondary_cpu_reset, env);
811: env->halted = 1;
812: }
813: *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
814: env->prom_addr = prom_addr;
815: }
816:
1.1.1.7 root 817: static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
1.1.1.6 root 818: const char *boot_device,
1.1.1.7 root 819: const char *kernel_filename,
1.1.1.6 root 820: const char *kernel_cmdline,
821: const char *initrd_filename, const char *cpu_model)
822: {
823: unsigned int i;
1.1.1.8 root 824: void *iommu, *espdma, *ledma, *nvram;
825: qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
826: espdma_irq, ledma_irq;
1.1.1.12 root 827: qemu_irq esp_reset, dma_enable;
1.1.1.8 root 828: qemu_irq fdc_tc;
1.1.1.7 root 829: qemu_irq *cpu_halt;
830: unsigned long kernel_size;
1.1.1.10 root 831: DriveInfo *fd[MAX_FD];
1.1.1.7 root 832: void *fw_cfg;
1.1.1.11 root 833: unsigned int num_vsimms;
1.1.1.6 root 834:
1.1.1.2 root 835: /* init CPUs */
1.1.1.6 root 836: if (!cpu_model)
837: cpu_model = hwdef->default_cpu_model;
838:
1.1.1.2 root 839: for(i = 0; i < smp_cpus; i++) {
1.1.1.11 root 840: cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1.1.1.2 root 841: }
1.1.1.6 root 842:
843: for (i = smp_cpus; i < MAX_CPUS; i++)
844: cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
845:
846:
1.1.1.8 root 847: /* set up devices */
848: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.11 root 849: /* models without ECC don't trap when missing ram is accessed */
850: if (!hwdef->ecc_base) {
851: empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
852: }
1.1 root 853:
1.1.1.8 root 854: prom_init(hwdef->slavio_base, bios_name);
1.1.1.6 root 855:
1.1.1.10 root 856: slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
857: hwdef->intctl_base + 0x10000ULL,
858: cpu_irqs);
1.1.1.2 root 859:
1.1.1.8 root 860: for (i = 0; i < 32; i++) {
1.1.1.10 root 861: slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
1.1.1.8 root 862: }
863: for (i = 0; i < MAX_CPUS; i++) {
1.1.1.10 root 864: slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
1.1.1.8 root 865: }
1.1.1.6 root 866:
1.1.1.7 root 867: if (hwdef->idreg_base) {
1.1.1.8 root 868: idreg_init(hwdef->idreg_base);
1.1.1.3 root 869: }
1.1.1.6 root 870:
1.1.1.11 root 871: if (hwdef->afx_base) {
872: afx_init(hwdef->afx_base);
873: }
874:
1.1.1.6 root 875: iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1.1.1.10 root 876: slavio_irq[30]);
1.1.1.6 root 877:
1.1.1.11 root 878: if (hwdef->iommu_pad_base) {
879: /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
880: Software shouldn't use aliased addresses, neither should it crash
881: when does. Using empty_slot instead of aliasing can help with
882: debugging such accesses */
883: empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
884: }
885:
1.1.1.10 root 886: espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
1.1.1.12 root 887: iommu, &espdma_irq, 0);
1.1.1.6 root 888:
889: ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1.1.1.12 root 890: slavio_irq[16], iommu, &ledma_irq, 1);
1.1.1.6 root 891:
892: if (graphic_depth != 8 && graphic_depth != 24) {
893: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
894: exit (1);
895: }
1.1.1.11 root 896: num_vsimms = 0;
897: if (num_vsimms == 0) {
898: tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
899: graphic_depth);
900: }
901:
902: for (i = num_vsimms; i < MAX_VSIMMS; i++) {
903: /* vsimm registers probed by OBP */
904: if (hwdef->vsimm[i].reg_base) {
905: empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
906: }
907: }
908:
909: if (hwdef->sx_base) {
910: empty_slot_init(hwdef->sx_base, 0x2000);
911: }
1.1.1.6 root 912:
1.1.1.10 root 913: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1.1.1.6 root 914:
1.1.1.10 root 915: nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1.1.1.6 root 916:
1.1.1.10 root 917: slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
1.1.1.6 root 918:
1.1.1.10 root 919: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
1.1.1.8 root 920: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1 root 921: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
922: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1.1.1.10 root 923: escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
1.1.1.7 root 924: serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1.1.1.6 root 925:
1.1.1.7 root 926: cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
1.1.1.10 root 927: slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
928: slavio_irq[30], fdc_tc);
929:
1.1.1.8 root 930: if (hwdef->apc_base) {
931: apc_init(hwdef->apc_base, cpu_halt[0]);
932: }
1.1.1.7 root 933:
934: if (hwdef->fd_base) {
1.1.1.6 root 935: /* there is zero or one floppy drive */
1.1.1.7 root 936: memset(fd, 0, sizeof(fd));
1.1.1.10 root 937: fd[0] = drive_get(IF_FLOPPY, 0, 0);
938: sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1.1.1.8 root 939: &fdc_tc);
1.1.1.6 root 940: }
941:
942: if (drive_get_max_bus(IF_SCSI) > 0) {
943: fprintf(stderr, "qemu: too many SCSI bus\n");
944: exit(1);
945: }
946:
1.1.1.8 root 947: esp_init(hwdef->esp_base, 2,
948: espdma_memory_read, espdma_memory_write,
1.1.1.12 root 949: espdma, espdma_irq, &esp_reset, &dma_enable);
1.1.1.10 root 950:
1.1.1.12 root 951: qdev_connect_gpio_out(espdma, 0, esp_reset);
952: qdev_connect_gpio_out(espdma, 1, dma_enable);
1.1.1.8 root 953:
954: if (hwdef->cs_base) {
955: sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1.1.1.10 root 956: slavio_irq[5]);
1.1.1.6 root 957: }
958:
1.1.1.11 root 959: if (hwdef->dbri_base) {
960: /* ISDN chip with attached CS4215 audio codec */
961: /* prom space */
962: empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
963: /* reg space */
964: empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
965: }
966:
967: if (hwdef->bpp_base) {
968: /* parallel port */
969: empty_slot_init(hwdef->bpp_base, 0x20);
970: }
971:
1.1.1.7 root 972: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
973: RAM_size);
1.1.1.6 root 974:
975: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
976: boot_device, RAM_size, kernel_size, graphic_width,
1.1.1.7 root 977: graphic_height, graphic_depth, hwdef->nvram_machine_id,
978: "Sun4m");
1.1.1.6 root 979:
1.1.1.7 root 980: if (hwdef->ecc_base)
1.1.1.10 root 981: ecc_init(hwdef->ecc_base, slavio_irq[28],
1.1.1.7 root 982: hwdef->ecc_version);
983:
984: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
985: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
986: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
987: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
988: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1.1.1.8 root 989: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
990: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
991: if (kernel_cmdline) {
992: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1.1.1.10 root 993: pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1.1.1.11 root 994: fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
995: (uint8_t*)strdup(kernel_cmdline),
996: strlen(kernel_cmdline) + 1);
1.1.1.12 root 997: fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
998: strlen(kernel_cmdline) + 1);
1.1.1.8 root 999: } else {
1000: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1.1.1.12 root 1001: fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1.1.1.8 root 1002: }
1003: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1004: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1005: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1006: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.7 root 1007: }
1008:
1009: enum {
1010: ss2_id = 0,
1011: ss5_id = 32,
1012: vger_id,
1013: lx_id,
1014: ss4_id,
1015: scls_id,
1016: sbook_id,
1017: ss10_id = 64,
1018: ss20_id,
1019: ss600mp_id,
1020: ss1000_id = 96,
1021: ss2000_id,
1022: };
1.1.1.6 root 1023:
1.1.1.7 root 1024: static const struct sun4m_hwdef sun4m_hwdefs[] = {
1.1.1.6 root 1025: /* SS-5 */
1026: {
1027: .iommu_base = 0x10000000,
1.1.1.11 root 1028: .iommu_pad_base = 0x10004000,
1029: .iommu_pad_len = 0x0fffb000,
1.1.1.6 root 1030: .tcx_base = 0x50000000,
1031: .cs_base = 0x6c000000,
1032: .slavio_base = 0x70000000,
1033: .ms_kb_base = 0x71000000,
1034: .serial_base = 0x71100000,
1035: .nvram_base = 0x71200000,
1036: .fd_base = 0x71400000,
1037: .counter_base = 0x71d00000,
1038: .intctl_base = 0x71e00000,
1039: .idreg_base = 0x78000000,
1040: .dma_base = 0x78400000,
1041: .esp_base = 0x78800000,
1042: .le_base = 0x78c00000,
1.1.1.7 root 1043: .apc_base = 0x6a000000,
1.1.1.11 root 1044: .afx_base = 0x6e000000,
1.1.1.7 root 1045: .aux1_base = 0x71900000,
1046: .aux2_base = 0x71910000,
1047: .nvram_machine_id = 0x80,
1048: .machine_id = ss5_id,
1.1.1.6 root 1049: .iommu_version = 0x05000000,
1050: .max_mem = 0x10000000,
1051: .default_cpu_model = "Fujitsu MB86904",
1052: },
1053: /* SS-10 */
1054: {
1055: .iommu_base = 0xfe0000000ULL,
1056: .tcx_base = 0xe20000000ULL,
1057: .slavio_base = 0xff0000000ULL,
1058: .ms_kb_base = 0xff1000000ULL,
1059: .serial_base = 0xff1100000ULL,
1060: .nvram_base = 0xff1200000ULL,
1061: .fd_base = 0xff1700000ULL,
1062: .counter_base = 0xff1300000ULL,
1063: .intctl_base = 0xff1400000ULL,
1064: .idreg_base = 0xef0000000ULL,
1065: .dma_base = 0xef0400000ULL,
1066: .esp_base = 0xef0800000ULL,
1067: .le_base = 0xef0c00000ULL,
1.1.1.7 root 1068: .apc_base = 0xefa000000ULL, // XXX should not exist
1069: .aux1_base = 0xff1800000ULL,
1070: .aux2_base = 0xff1a01000ULL,
1.1.1.6 root 1071: .ecc_base = 0xf00000000ULL,
1072: .ecc_version = 0x10000000, // version 0, implementation 1
1.1.1.7 root 1073: .nvram_machine_id = 0x72,
1074: .machine_id = ss10_id,
1.1.1.6 root 1075: .iommu_version = 0x03000000,
1.1.1.7 root 1076: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1077: .default_cpu_model = "TI SuperSparc II",
1078: },
1079: /* SS-600MP */
1080: {
1081: .iommu_base = 0xfe0000000ULL,
1082: .tcx_base = 0xe20000000ULL,
1083: .slavio_base = 0xff0000000ULL,
1084: .ms_kb_base = 0xff1000000ULL,
1085: .serial_base = 0xff1100000ULL,
1086: .nvram_base = 0xff1200000ULL,
1087: .counter_base = 0xff1300000ULL,
1088: .intctl_base = 0xff1400000ULL,
1089: .dma_base = 0xef0081000ULL,
1090: .esp_base = 0xef0080000ULL,
1091: .le_base = 0xef0060000ULL,
1.1.1.7 root 1092: .apc_base = 0xefa000000ULL, // XXX should not exist
1093: .aux1_base = 0xff1800000ULL,
1094: .aux2_base = 0xff1a01000ULL, // XXX should not exist
1.1.1.6 root 1095: .ecc_base = 0xf00000000ULL,
1096: .ecc_version = 0x00000000, // version 0, implementation 0
1.1.1.7 root 1097: .nvram_machine_id = 0x71,
1098: .machine_id = ss600mp_id,
1.1.1.6 root 1099: .iommu_version = 0x01000000,
1.1.1.7 root 1100: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1101: .default_cpu_model = "TI SuperSparc II",
1102: },
1103: /* SS-20 */
1104: {
1105: .iommu_base = 0xfe0000000ULL,
1106: .tcx_base = 0xe20000000ULL,
1107: .slavio_base = 0xff0000000ULL,
1108: .ms_kb_base = 0xff1000000ULL,
1109: .serial_base = 0xff1100000ULL,
1110: .nvram_base = 0xff1200000ULL,
1111: .fd_base = 0xff1700000ULL,
1112: .counter_base = 0xff1300000ULL,
1113: .intctl_base = 0xff1400000ULL,
1114: .idreg_base = 0xef0000000ULL,
1115: .dma_base = 0xef0400000ULL,
1116: .esp_base = 0xef0800000ULL,
1117: .le_base = 0xef0c00000ULL,
1.1.1.11 root 1118: .bpp_base = 0xef4800000ULL,
1.1.1.7 root 1119: .apc_base = 0xefa000000ULL, // XXX should not exist
1120: .aux1_base = 0xff1800000ULL,
1121: .aux2_base = 0xff1a01000ULL,
1.1.1.11 root 1122: .dbri_base = 0xee0000000ULL,
1123: .sx_base = 0xf80000000ULL,
1124: .vsimm = {
1125: {
1126: .reg_base = 0x9c000000ULL,
1127: .vram_base = 0xfc000000ULL
1128: }, {
1129: .reg_base = 0x90000000ULL,
1130: .vram_base = 0xf0000000ULL
1131: }, {
1132: .reg_base = 0x94000000ULL
1133: }, {
1134: .reg_base = 0x98000000ULL
1135: }
1136: },
1.1.1.6 root 1137: .ecc_base = 0xf00000000ULL,
1138: .ecc_version = 0x20000000, // version 0, implementation 2
1.1.1.7 root 1139: .nvram_machine_id = 0x72,
1140: .machine_id = ss20_id,
1.1.1.6 root 1141: .iommu_version = 0x13000000,
1.1.1.7 root 1142: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1143: .default_cpu_model = "TI SuperSparc II",
1144: },
1.1.1.7 root 1145: /* Voyager */
1.1.1.6 root 1146: {
1.1.1.7 root 1147: .iommu_base = 0x10000000,
1148: .tcx_base = 0x50000000,
1149: .slavio_base = 0x70000000,
1150: .ms_kb_base = 0x71000000,
1151: .serial_base = 0x71100000,
1152: .nvram_base = 0x71200000,
1153: .fd_base = 0x71400000,
1154: .counter_base = 0x71d00000,
1155: .intctl_base = 0x71e00000,
1156: .idreg_base = 0x78000000,
1157: .dma_base = 0x78400000,
1158: .esp_base = 0x78800000,
1159: .le_base = 0x78c00000,
1160: .apc_base = 0x71300000, // pmc
1161: .aux1_base = 0x71900000,
1162: .aux2_base = 0x71910000,
1163: .nvram_machine_id = 0x80,
1164: .machine_id = vger_id,
1165: .iommu_version = 0x05000000,
1.1.1.6 root 1166: .max_mem = 0x10000000,
1.1.1.7 root 1167: .default_cpu_model = "Fujitsu MB86904",
1168: },
1169: /* LX */
1170: {
1171: .iommu_base = 0x10000000,
1.1.1.11 root 1172: .iommu_pad_base = 0x10004000,
1173: .iommu_pad_len = 0x0fffb000,
1.1.1.7 root 1174: .tcx_base = 0x50000000,
1175: .slavio_base = 0x70000000,
1176: .ms_kb_base = 0x71000000,
1177: .serial_base = 0x71100000,
1178: .nvram_base = 0x71200000,
1179: .fd_base = 0x71400000,
1180: .counter_base = 0x71d00000,
1181: .intctl_base = 0x71e00000,
1182: .idreg_base = 0x78000000,
1183: .dma_base = 0x78400000,
1184: .esp_base = 0x78800000,
1185: .le_base = 0x78c00000,
1186: .aux1_base = 0x71900000,
1187: .aux2_base = 0x71910000,
1188: .nvram_machine_id = 0x80,
1189: .machine_id = lx_id,
1190: .iommu_version = 0x04000000,
1191: .max_mem = 0x10000000,
1192: .default_cpu_model = "TI MicroSparc I",
1193: },
1194: /* SS-4 */
1195: {
1196: .iommu_base = 0x10000000,
1197: .tcx_base = 0x50000000,
1198: .cs_base = 0x6c000000,
1199: .slavio_base = 0x70000000,
1200: .ms_kb_base = 0x71000000,
1201: .serial_base = 0x71100000,
1202: .nvram_base = 0x71200000,
1203: .fd_base = 0x71400000,
1204: .counter_base = 0x71d00000,
1205: .intctl_base = 0x71e00000,
1206: .idreg_base = 0x78000000,
1207: .dma_base = 0x78400000,
1208: .esp_base = 0x78800000,
1209: .le_base = 0x78c00000,
1210: .apc_base = 0x6a000000,
1211: .aux1_base = 0x71900000,
1212: .aux2_base = 0x71910000,
1213: .nvram_machine_id = 0x80,
1214: .machine_id = ss4_id,
1215: .iommu_version = 0x05000000,
1216: .max_mem = 0x10000000,
1217: .default_cpu_model = "Fujitsu MB86904",
1218: },
1219: /* SPARCClassic */
1220: {
1221: .iommu_base = 0x10000000,
1222: .tcx_base = 0x50000000,
1223: .slavio_base = 0x70000000,
1224: .ms_kb_base = 0x71000000,
1225: .serial_base = 0x71100000,
1226: .nvram_base = 0x71200000,
1227: .fd_base = 0x71400000,
1228: .counter_base = 0x71d00000,
1229: .intctl_base = 0x71e00000,
1230: .idreg_base = 0x78000000,
1231: .dma_base = 0x78400000,
1232: .esp_base = 0x78800000,
1233: .le_base = 0x78c00000,
1234: .apc_base = 0x6a000000,
1235: .aux1_base = 0x71900000,
1236: .aux2_base = 0x71910000,
1237: .nvram_machine_id = 0x80,
1238: .machine_id = scls_id,
1239: .iommu_version = 0x05000000,
1240: .max_mem = 0x10000000,
1241: .default_cpu_model = "TI MicroSparc I",
1242: },
1243: /* SPARCbook */
1244: {
1245: .iommu_base = 0x10000000,
1246: .tcx_base = 0x50000000, // XXX
1247: .slavio_base = 0x70000000,
1248: .ms_kb_base = 0x71000000,
1249: .serial_base = 0x71100000,
1250: .nvram_base = 0x71200000,
1251: .fd_base = 0x71400000,
1252: .counter_base = 0x71d00000,
1253: .intctl_base = 0x71e00000,
1254: .idreg_base = 0x78000000,
1255: .dma_base = 0x78400000,
1256: .esp_base = 0x78800000,
1257: .le_base = 0x78c00000,
1258: .apc_base = 0x6a000000,
1259: .aux1_base = 0x71900000,
1260: .aux2_base = 0x71910000,
1261: .nvram_machine_id = 0x80,
1262: .machine_id = sbook_id,
1263: .iommu_version = 0x05000000,
1264: .max_mem = 0x10000000,
1265: .default_cpu_model = "TI MicroSparc I",
1.1.1.6 root 1266: },
1267: };
1268:
1269: /* SPARCstation 5 hardware initialisation */
1.1.1.8 root 1270: static void ss5_init(ram_addr_t RAM_size,
1.1.1.7 root 1271: const char *boot_device,
1.1.1.6 root 1272: const char *kernel_filename, const char *kernel_cmdline,
1273: const char *initrd_filename, const char *cpu_model)
1274: {
1.1.1.7 root 1275: sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1276: kernel_cmdline, initrd_filename, cpu_model);
1277: }
1278:
1279: /* SPARCstation 10 hardware initialisation */
1.1.1.8 root 1280: static void ss10_init(ram_addr_t RAM_size,
1.1.1.7 root 1281: const char *boot_device,
1.1.1.6 root 1282: const char *kernel_filename, const char *kernel_cmdline,
1283: const char *initrd_filename, const char *cpu_model)
1284: {
1.1.1.7 root 1285: sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1286: kernel_cmdline, initrd_filename, cpu_model);
1287: }
1288:
1289: /* SPARCserver 600MP hardware initialisation */
1.1.1.8 root 1290: static void ss600mp_init(ram_addr_t RAM_size,
1.1.1.7 root 1291: const char *boot_device,
1292: const char *kernel_filename,
1293: const char *kernel_cmdline,
1.1.1.6 root 1294: const char *initrd_filename, const char *cpu_model)
1295: {
1.1.1.7 root 1296: sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1297: kernel_cmdline, initrd_filename, cpu_model);
1298: }
1299:
1300: /* SPARCstation 20 hardware initialisation */
1.1.1.8 root 1301: static void ss20_init(ram_addr_t RAM_size,
1.1.1.7 root 1302: const char *boot_device,
1.1.1.6 root 1303: const char *kernel_filename, const char *kernel_cmdline,
1304: const char *initrd_filename, const char *cpu_model)
1305: {
1.1.1.7 root 1306: sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1307: kernel_cmdline, initrd_filename, cpu_model);
1308: }
1309:
1.1.1.7 root 1310: /* SPARCstation Voyager hardware initialisation */
1.1.1.8 root 1311: static void vger_init(ram_addr_t RAM_size,
1.1.1.7 root 1312: const char *boot_device,
1313: const char *kernel_filename, const char *kernel_cmdline,
1314: const char *initrd_filename, const char *cpu_model)
1315: {
1316: sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1317: kernel_cmdline, initrd_filename, cpu_model);
1318: }
1319:
1320: /* SPARCstation LX hardware initialisation */
1.1.1.8 root 1321: static void ss_lx_init(ram_addr_t RAM_size,
1.1.1.7 root 1322: const char *boot_device,
1323: const char *kernel_filename, const char *kernel_cmdline,
1324: const char *initrd_filename, const char *cpu_model)
1325: {
1326: sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1327: kernel_cmdline, initrd_filename, cpu_model);
1328: }
1329:
1330: /* SPARCstation 4 hardware initialisation */
1.1.1.8 root 1331: static void ss4_init(ram_addr_t RAM_size,
1.1.1.7 root 1332: const char *boot_device,
1.1.1.6 root 1333: const char *kernel_filename, const char *kernel_cmdline,
1334: const char *initrd_filename, const char *cpu_model)
1335: {
1.1.1.7 root 1336: sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1337: kernel_cmdline, initrd_filename, cpu_model);
1338: }
1339:
1340: /* SPARCClassic hardware initialisation */
1.1.1.8 root 1341: static void scls_init(ram_addr_t RAM_size,
1.1.1.7 root 1342: const char *boot_device,
1343: const char *kernel_filename, const char *kernel_cmdline,
1344: const char *initrd_filename, const char *cpu_model)
1345: {
1346: sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1347: kernel_cmdline, initrd_filename, cpu_model);
1348: }
1349:
1350: /* SPARCbook hardware initialisation */
1.1.1.8 root 1351: static void sbook_init(ram_addr_t RAM_size,
1.1.1.7 root 1352: const char *boot_device,
1353: const char *kernel_filename, const char *kernel_cmdline,
1354: const char *initrd_filename, const char *cpu_model)
1355: {
1356: sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1357: kernel_cmdline, initrd_filename, cpu_model);
1358: }
1359:
1.1.1.8 root 1360: static QEMUMachine ss5_machine = {
1.1.1.7 root 1361: .name = "SS-5",
1362: .desc = "Sun4m platform, SPARCstation 5",
1363: .init = ss5_init,
1364: .use_scsi = 1,
1.1.1.8 root 1365: .is_default = 1,
1.1.1.6 root 1366: };
1367:
1.1.1.8 root 1368: static QEMUMachine ss10_machine = {
1.1.1.7 root 1369: .name = "SS-10",
1370: .desc = "Sun4m platform, SPARCstation 10",
1371: .init = ss10_init,
1372: .use_scsi = 1,
1373: .max_cpus = 4,
1.1.1.6 root 1374: };
1375:
1.1.1.8 root 1376: static QEMUMachine ss600mp_machine = {
1.1.1.7 root 1377: .name = "SS-600MP",
1378: .desc = "Sun4m platform, SPARCserver 600MP",
1379: .init = ss600mp_init,
1380: .use_scsi = 1,
1381: .max_cpus = 4,
1.1.1.6 root 1382: };
1383:
1.1.1.8 root 1384: static QEMUMachine ss20_machine = {
1.1.1.7 root 1385: .name = "SS-20",
1386: .desc = "Sun4m platform, SPARCstation 20",
1387: .init = ss20_init,
1388: .use_scsi = 1,
1389: .max_cpus = 4,
1.1.1.6 root 1390: };
1391:
1.1.1.8 root 1392: static QEMUMachine voyager_machine = {
1.1.1.7 root 1393: .name = "Voyager",
1394: .desc = "Sun4m platform, SPARCstation Voyager",
1395: .init = vger_init,
1396: .use_scsi = 1,
1397: };
1398:
1.1.1.8 root 1399: static QEMUMachine ss_lx_machine = {
1.1.1.7 root 1400: .name = "LX",
1401: .desc = "Sun4m platform, SPARCstation LX",
1402: .init = ss_lx_init,
1403: .use_scsi = 1,
1404: };
1405:
1.1.1.8 root 1406: static QEMUMachine ss4_machine = {
1.1.1.7 root 1407: .name = "SS-4",
1408: .desc = "Sun4m platform, SPARCstation 4",
1409: .init = ss4_init,
1410: .use_scsi = 1,
1411: };
1412:
1.1.1.8 root 1413: static QEMUMachine scls_machine = {
1.1.1.7 root 1414: .name = "SPARCClassic",
1415: .desc = "Sun4m platform, SPARCClassic",
1416: .init = scls_init,
1417: .use_scsi = 1,
1418: };
1419:
1.1.1.8 root 1420: static QEMUMachine sbook_machine = {
1.1.1.7 root 1421: .name = "SPARCbook",
1422: .desc = "Sun4m platform, SPARCbook",
1423: .init = sbook_init,
1424: .use_scsi = 1,
1.1.1.6 root 1425: };
1426:
1427: static const struct sun4d_hwdef sun4d_hwdefs[] = {
1428: /* SS-1000 */
1429: {
1430: .iounit_bases = {
1431: 0xfe0200000ULL,
1432: 0xfe1200000ULL,
1433: 0xfe2200000ULL,
1434: 0xfe3200000ULL,
1435: -1,
1436: },
1437: .tcx_base = 0x820000000ULL,
1438: .slavio_base = 0xf00000000ULL,
1439: .ms_kb_base = 0xf00240000ULL,
1440: .serial_base = 0xf00200000ULL,
1441: .nvram_base = 0xf00280000ULL,
1442: .counter_base = 0xf00300000ULL,
1443: .espdma_base = 0x800081000ULL,
1444: .esp_base = 0x800080000ULL,
1445: .ledma_base = 0x800040000ULL,
1446: .le_base = 0x800060000ULL,
1447: .sbi_base = 0xf02800000ULL,
1.1.1.7 root 1448: .nvram_machine_id = 0x80,
1449: .machine_id = ss1000_id,
1.1.1.6 root 1450: .iounit_version = 0x03000000,
1.1.1.7 root 1451: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1452: .default_cpu_model = "TI SuperSparc II",
1453: },
1454: /* SS-2000 */
1455: {
1456: .iounit_bases = {
1457: 0xfe0200000ULL,
1458: 0xfe1200000ULL,
1459: 0xfe2200000ULL,
1460: 0xfe3200000ULL,
1461: 0xfe4200000ULL,
1462: },
1463: .tcx_base = 0x820000000ULL,
1464: .slavio_base = 0xf00000000ULL,
1465: .ms_kb_base = 0xf00240000ULL,
1466: .serial_base = 0xf00200000ULL,
1467: .nvram_base = 0xf00280000ULL,
1468: .counter_base = 0xf00300000ULL,
1469: .espdma_base = 0x800081000ULL,
1470: .esp_base = 0x800080000ULL,
1471: .ledma_base = 0x800040000ULL,
1472: .le_base = 0x800060000ULL,
1473: .sbi_base = 0xf02800000ULL,
1.1.1.7 root 1474: .nvram_machine_id = 0x80,
1475: .machine_id = ss2000_id,
1.1.1.6 root 1476: .iounit_version = 0x03000000,
1.1.1.7 root 1477: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1478: .default_cpu_model = "TI SuperSparc II",
1479: },
1480: };
1481:
1.1.1.10 root 1482: static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1483: {
1484: DeviceState *dev;
1485: SysBusDevice *s;
1486: unsigned int i;
1487:
1488: dev = qdev_create(NULL, "sbi");
1489: qdev_init_nofail(dev);
1490:
1491: s = sysbus_from_qdev(dev);
1492:
1493: for (i = 0; i < MAX_CPUS; i++) {
1494: sysbus_connect_irq(s, i, *parent_irq[i]);
1495: }
1496:
1497: sysbus_mmio_map(s, 0, addr);
1498:
1499: return dev;
1500: }
1501:
1.1.1.7 root 1502: static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1.1.1.6 root 1503: const char *boot_device,
1.1.1.7 root 1504: const char *kernel_filename,
1.1.1.6 root 1505: const char *kernel_cmdline,
1506: const char *initrd_filename, const char *cpu_model)
1507: {
1508: unsigned int i;
1.1.1.10 root 1509: void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1510: qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1.1.1.8 root 1511: espdma_irq, ledma_irq;
1.1.1.12 root 1512: qemu_irq esp_reset, dma_enable;
1.1.1.7 root 1513: unsigned long kernel_size;
1514: void *fw_cfg;
1.1.1.10 root 1515: DeviceState *dev;
1.1.1.6 root 1516:
1517: /* init CPUs */
1518: if (!cpu_model)
1519: cpu_model = hwdef->default_cpu_model;
1520:
1.1.1.8 root 1521: for(i = 0; i < smp_cpus; i++) {
1.1.1.11 root 1522: cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1.1.1.6 root 1523: }
1524:
1525: for (i = smp_cpus; i < MAX_CPUS; i++)
1526: cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1527:
1.1.1.8 root 1528: /* set up devices */
1529: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.6 root 1530:
1.1.1.8 root 1531: prom_init(hwdef->slavio_base, bios_name);
1.1.1.6 root 1532:
1.1.1.10 root 1533: dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1534:
1535: for (i = 0; i < 32; i++) {
1536: sbi_irq[i] = qdev_get_gpio_in(dev, i);
1537: }
1538: for (i = 0; i < MAX_CPUS; i++) {
1539: sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1540: }
1.1.1.6 root 1541:
1542: for (i = 0; i < MAX_IOUNITS; i++)
1543: if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1544: iounits[i] = iommu_init(hwdef->iounit_bases[i],
1545: hwdef->iounit_version,
1.1.1.10 root 1546: sbi_irq[0]);
1.1.1.6 root 1547:
1.1.1.10 root 1548: espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1.1.1.12 root 1549: iounits[0], &espdma_irq, 0);
1.1.1.6 root 1550:
1.1.1.12 root 1551: /* should be lebuffer instead */
1.1.1.10 root 1552: ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1.1.1.12 root 1553: iounits[0], &ledma_irq, 0);
1.1.1.6 root 1554:
1555: if (graphic_depth != 8 && graphic_depth != 24) {
1556: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1557: exit (1);
1558: }
1.1.1.10 root 1559: tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1.1.1.8 root 1560: graphic_depth);
1.1.1.6 root 1561:
1.1.1.10 root 1562: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1.1.1.6 root 1563:
1.1.1.10 root 1564: nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1.1.1.6 root 1565:
1.1.1.10 root 1566: slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1.1.1.6 root 1567:
1.1.1.10 root 1568: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1.1.1.8 root 1569: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1.1.6 root 1570: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1571: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1.1.1.10 root 1572: escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1.1.1.7 root 1573: serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1.1.1.6 root 1574:
1575: if (drive_get_max_bus(IF_SCSI) > 0) {
1576: fprintf(stderr, "qemu: too many SCSI bus\n");
1577: exit(1);
1578: }
1579:
1.1.1.8 root 1580: esp_init(hwdef->esp_base, 2,
1581: espdma_memory_read, espdma_memory_write,
1.1.1.12 root 1582: espdma, espdma_irq, &esp_reset, &dma_enable);
1583:
1584: qdev_connect_gpio_out(espdma, 0, esp_reset);
1585: qdev_connect_gpio_out(espdma, 1, dma_enable);
1.1.1.6 root 1586:
1.1.1.7 root 1587: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1588: RAM_size);
1.1.1.6 root 1589:
1590: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1591: boot_device, RAM_size, kernel_size, graphic_width,
1.1.1.7 root 1592: graphic_height, graphic_depth, hwdef->nvram_machine_id,
1593: "Sun4d");
1594:
1595: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1596: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1597: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1598: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1.1.1.8 root 1599: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1600: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1601: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1602: if (kernel_cmdline) {
1603: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1.1.1.10 root 1604: pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1.1.1.11 root 1605: fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1606: (uint8_t*)strdup(kernel_cmdline),
1607: strlen(kernel_cmdline) + 1);
1.1.1.8 root 1608: } else {
1609: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1610: }
1611: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1612: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1613: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1614: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.6 root 1615: }
1616:
1617: /* SPARCserver 1000 hardware initialisation */
1.1.1.8 root 1618: static void ss1000_init(ram_addr_t RAM_size,
1.1.1.7 root 1619: const char *boot_device,
1.1.1.6 root 1620: const char *kernel_filename, const char *kernel_cmdline,
1621: const char *initrd_filename, const char *cpu_model)
1622: {
1.1.1.7 root 1623: sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1624: kernel_cmdline, initrd_filename, cpu_model);
1.1 root 1625: }
1626:
1.1.1.6 root 1627: /* SPARCcenter 2000 hardware initialisation */
1.1.1.8 root 1628: static void ss2000_init(ram_addr_t RAM_size,
1.1.1.7 root 1629: const char *boot_device,
1.1.1.6 root 1630: const char *kernel_filename, const char *kernel_cmdline,
1631: const char *initrd_filename, const char *cpu_model)
1632: {
1.1.1.7 root 1633: sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1634: kernel_cmdline, initrd_filename, cpu_model);
1635: }
1636:
1.1.1.8 root 1637: static QEMUMachine ss1000_machine = {
1.1.1.7 root 1638: .name = "SS-1000",
1639: .desc = "Sun4d platform, SPARCserver 1000",
1640: .init = ss1000_init,
1641: .use_scsi = 1,
1642: .max_cpus = 8,
1.1.1.6 root 1643: };
1644:
1.1.1.8 root 1645: static QEMUMachine ss2000_machine = {
1.1.1.7 root 1646: .name = "SS-2000",
1647: .desc = "Sun4d platform, SPARCcenter 2000",
1648: .init = ss2000_init,
1649: .use_scsi = 1,
1650: .max_cpus = 20,
1651: };
1652:
1653: static const struct sun4c_hwdef sun4c_hwdefs[] = {
1654: /* SS-2 */
1655: {
1656: .iommu_base = 0xf8000000,
1657: .tcx_base = 0xfe000000,
1658: .slavio_base = 0xf6000000,
1659: .intctl_base = 0xf5000000,
1660: .counter_base = 0xf3000000,
1661: .ms_kb_base = 0xf0000000,
1662: .serial_base = 0xf1000000,
1663: .nvram_base = 0xf2000000,
1664: .fd_base = 0xf7200000,
1665: .dma_base = 0xf8400000,
1666: .esp_base = 0xf8800000,
1667: .le_base = 0xf8c00000,
1668: .aux1_base = 0xf7400003,
1669: .nvram_machine_id = 0x55,
1670: .machine_id = ss2_id,
1671: .max_mem = 0x10000000,
1672: .default_cpu_model = "Cypress CY7C601",
1673: },
1674: };
1675:
1.1.1.10 root 1676: static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1677: qemu_irq *parent_irq)
1678: {
1679: DeviceState *dev;
1680: SysBusDevice *s;
1681: unsigned int i;
1682:
1683: dev = qdev_create(NULL, "sun4c_intctl");
1684: qdev_init_nofail(dev);
1685:
1686: s = sysbus_from_qdev(dev);
1687:
1688: for (i = 0; i < MAX_PILS; i++) {
1689: sysbus_connect_irq(s, i, parent_irq[i]);
1690: }
1691: sysbus_mmio_map(s, 0, addr);
1692:
1693: return dev;
1694: }
1695:
1.1.1.7 root 1696: static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1697: const char *boot_device,
1698: const char *kernel_filename,
1699: const char *kernel_cmdline,
1700: const char *initrd_filename, const char *cpu_model)
1701: {
1.1.1.8 root 1702: void *iommu, *espdma, *ledma, *nvram;
1.1.1.10 root 1703: qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1.1.1.12 root 1704: qemu_irq esp_reset, dma_enable;
1.1.1.8 root 1705: qemu_irq fdc_tc;
1.1.1.7 root 1706: unsigned long kernel_size;
1.1.1.10 root 1707: DriveInfo *fd[MAX_FD];
1.1.1.7 root 1708: void *fw_cfg;
1.1.1.10 root 1709: DeviceState *dev;
1710: unsigned int i;
1.1.1.7 root 1711:
1712: /* init CPU */
1713: if (!cpu_model)
1714: cpu_model = hwdef->default_cpu_model;
1715:
1.1.1.11 root 1716: cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1.1.1.7 root 1717:
1.1.1.8 root 1718: /* set up devices */
1719: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.7 root 1720:
1.1.1.8 root 1721: prom_init(hwdef->slavio_base, bios_name);
1.1.1.7 root 1722:
1.1.1.10 root 1723: dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1724:
1725: for (i = 0; i < 8; i++) {
1726: slavio_irq[i] = qdev_get_gpio_in(dev, i);
1727: }
1.1.1.7 root 1728:
1729: iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1.1.1.10 root 1730: slavio_irq[1]);
1.1.1.7 root 1731:
1.1.1.10 root 1732: espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1.1.1.12 root 1733: iommu, &espdma_irq, 0);
1.1.1.7 root 1734:
1735: ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1.1.1.12 root 1736: slavio_irq[3], iommu, &ledma_irq, 1);
1.1.1.7 root 1737:
1738: if (graphic_depth != 8 && graphic_depth != 24) {
1739: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1740: exit (1);
1741: }
1.1.1.10 root 1742: tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1.1.1.8 root 1743: graphic_depth);
1.1.1.7 root 1744:
1.1.1.10 root 1745: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1.1.1.7 root 1746:
1.1.1.10 root 1747: nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1.1.1.7 root 1748:
1.1.1.10 root 1749: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1.1.1.8 root 1750: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1.1.7 root 1751: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1752: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1.1.1.10 root 1753: escc_init(hwdef->serial_base, slavio_irq[1],
1754: slavio_irq[1], serial_hds[0], serial_hds[1],
1.1.1.7 root 1755: ESCC_CLOCK, 1);
1756:
1.1.1.10 root 1757: slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1.1.1.7 root 1758:
1759: if (hwdef->fd_base != (target_phys_addr_t)-1) {
1760: /* there is zero or one floppy drive */
1761: memset(fd, 0, sizeof(fd));
1.1.1.10 root 1762: fd[0] = drive_get(IF_FLOPPY, 0, 0);
1763: sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1.1.1.8 root 1764: &fdc_tc);
1.1.1.7 root 1765: }
1766:
1767: if (drive_get_max_bus(IF_SCSI) > 0) {
1768: fprintf(stderr, "qemu: too many SCSI bus\n");
1769: exit(1);
1770: }
1771:
1.1.1.8 root 1772: esp_init(hwdef->esp_base, 2,
1773: espdma_memory_read, espdma_memory_write,
1.1.1.12 root 1774: espdma, espdma_irq, &esp_reset, &dma_enable);
1775:
1776: qdev_connect_gpio_out(espdma, 0, esp_reset);
1777: qdev_connect_gpio_out(espdma, 1, dma_enable);
1.1.1.7 root 1778:
1779: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1780: RAM_size);
1781:
1782: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1783: boot_device, RAM_size, kernel_size, graphic_width,
1784: graphic_height, graphic_depth, hwdef->nvram_machine_id,
1785: "Sun4c");
1786:
1787: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1788: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1789: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1790: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1.1.1.8 root 1791: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1792: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1793: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1794: if (kernel_cmdline) {
1795: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1.1.1.10 root 1796: pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1.1.1.11 root 1797: fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1798: (uint8_t*)strdup(kernel_cmdline),
1799: strlen(kernel_cmdline) + 1);
1.1.1.8 root 1800: } else {
1801: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1802: }
1803: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1804: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1805: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1806: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.7 root 1807: }
1808:
1809: /* SPARCstation 2 hardware initialisation */
1.1.1.8 root 1810: static void ss2_init(ram_addr_t RAM_size,
1.1.1.7 root 1811: const char *boot_device,
1812: const char *kernel_filename, const char *kernel_cmdline,
1813: const char *initrd_filename, const char *cpu_model)
1814: {
1815: sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1816: kernel_cmdline, initrd_filename, cpu_model);
1817: }
1818:
1.1.1.8 root 1819: static QEMUMachine ss2_machine = {
1.1.1.7 root 1820: .name = "SS-2",
1821: .desc = "Sun4c platform, SPARCstation 2",
1822: .init = ss2_init,
1823: .use_scsi = 1,
1.1 root 1824: };
1.1.1.8 root 1825:
1826: static void ss2_machine_init(void)
1827: {
1828: qemu_register_machine(&ss5_machine);
1829: qemu_register_machine(&ss10_machine);
1830: qemu_register_machine(&ss600mp_machine);
1831: qemu_register_machine(&ss20_machine);
1832: qemu_register_machine(&voyager_machine);
1833: qemu_register_machine(&ss_lx_machine);
1834: qemu_register_machine(&ss4_machine);
1835: qemu_register_machine(&scls_machine);
1836: qemu_register_machine(&sbook_machine);
1837: qemu_register_machine(&ss1000_machine);
1838: qemu_register_machine(&ss2000_machine);
1839: qemu_register_machine(&ss2_machine);
1840: }
1841:
1842: machine_init(ss2_machine_init);
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