![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to sun4m.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / hw|
Return to sun4m.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu / hw |
1.1 root 1: /*
1.1.1.6 root 2: * QEMU Sun4m & Sun4d & Sun4c System Emulator
3: *
1.1 root 4: * Copyright (c) 2003-2005 Fabrice Bellard
1.1.1.6 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.8 root 24: #include "sysbus.h"
1.1.1.6 root 25: #include "qemu-timer.h"
26: #include "sun4m.h"
27: #include "nvram.h"
28: #include "sparc32_dma.h"
29: #include "fdc.h"
30: #include "sysemu.h"
31: #include "net.h"
32: #include "boards.h"
33: #include "firmware_abi.h"
1.1.1.10 root 34: #include "esp.h"
1.1.1.7 root 35: #include "pc.h"
36: #include "isa.h"
37: #include "fw_cfg.h"
38: #include "escc.h"
1.1.1.11 root 39: #include "empty_slot.h"
1.1.1.10 root 40: #include "qdev-addr.h"
41: #include "loader.h"
42: #include "elf.h"
1.1.1.12 root 43: #include "blockdev.h"
44: #include "trace.h"
1.1.1.6 root 45:
46: /*
47: * Sun4m architecture was used in the following machines:
48: *
49: * SPARCserver 6xxMP/xx
1.1.1.7 root 50: * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51: * SPARCclassic X (4/10)
1.1.1.6 root 52: * SPARCstation LX/ZX (4/30)
53: * SPARCstation Voyager
54: * SPARCstation 10/xx, SPARCserver 10/xx
55: * SPARCstation 5, SPARCserver 5
56: * SPARCstation 20/xx, SPARCserver 20
57: * SPARCstation 4
58: *
59: * Sun4d architecture was used in the following machines:
60: *
61: * SPARCcenter 2000
62: * SPARCserver 1000
63: *
64: * Sun4c architecture was used in the following machines:
65: * SPARCstation 1/1+, SPARCserver 1/1+
66: * SPARCstation SLC
67: * SPARCstation IPC
68: * SPARCstation ELC
69: * SPARCstation IPX
70: *
71: * See for example: http://www.sunhelp.org/faq/sunref1.html
72: */
73:
1.1 root 74: #define KERNEL_LOAD_ADDR 0x00004000
75: #define CMDLINE_ADDR 0x007ff000
76: #define INITRD_LOAD_ADDR 0x00800000
1.1.1.7 root 77: #define PROM_SIZE_MAX (1024 * 1024)
1.1.1.6 root 78: #define PROM_VADDR 0xffd00000
79: #define PROM_FILENAME "openbios-sparc32"
1.1.1.7 root 80: #define CFG_ADDR 0xd00000510ULL
81: #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82:
1.1.1.2 root 83: #define MAX_CPUS 16
1.1.1.6 root 84: #define MAX_PILS 16
1.1.1.11 root 85: #define MAX_VSIMMS 4
1.1.1.6 root 86:
1.1.1.7 root 87: #define ESCC_CLOCK 4915200
88:
89: struct sun4m_hwdef {
1.1.1.11 root 90: target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
1.1.1.6 root 91: target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92: target_phys_addr_t serial_base, fd_base;
1.1.1.11 root 93: target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
1.1.1.7 root 94: target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
1.1.1.11 root 95: target_phys_addr_t bpp_base, dbri_base, sx_base;
96: struct {
97: target_phys_addr_t reg_base, vram_base;
98: } vsimm[MAX_VSIMMS];
1.1.1.6 root 99: target_phys_addr_t ecc_base;
100: uint64_t max_mem;
101: const char * const default_cpu_model;
1.1.1.14 root 102: uint32_t ecc_version;
103: uint32_t iommu_version;
104: uint16_t machine_id;
105: uint8_t nvram_machine_id;
1.1.1.6 root 106: };
107:
108: #define MAX_IOUNITS 5
109:
110: struct sun4d_hwdef {
111: target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112: target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113: target_phys_addr_t serial_base;
114: target_phys_addr_t espdma_base, esp_base;
115: target_phys_addr_t ledma_base, le_base;
116: target_phys_addr_t tcx_base;
117: target_phys_addr_t sbi_base;
118: uint64_t max_mem;
119: const char * const default_cpu_model;
1.1.1.14 root 120: uint32_t iounit_version;
121: uint16_t machine_id;
122: uint8_t nvram_machine_id;
1.1.1.6 root 123: };
1.1 root 124:
1.1.1.7 root 125: struct sun4c_hwdef {
126: target_phys_addr_t iommu_base, slavio_base;
127: target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128: target_phys_addr_t serial_base, fd_base;
129: target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130: target_phys_addr_t tcx_base, aux1_base;
131: uint64_t max_mem;
132: const char * const default_cpu_model;
1.1.1.14 root 133: uint32_t iommu_version;
134: uint16_t machine_id;
135: uint8_t nvram_machine_id;
1.1.1.7 root 136: };
1.1 root 137:
138: int DMA_get_channel_mode (int nchan)
139: {
140: return 0;
141: }
142: int DMA_read_memory (int nchan, void *buf, int pos, int size)
143: {
144: return 0;
145: }
146: int DMA_write_memory (int nchan, void *buf, int pos, int size)
147: {
148: return 0;
149: }
150: void DMA_hold_DREQ (int nchan) {}
151: void DMA_release_DREQ (int nchan) {}
152: void DMA_schedule(int nchan) {}
1.1.1.11 root 153:
154: void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155: {
156: }
157:
1.1 root 158: void DMA_register_channel (int nchan,
159: DMA_transfer_handler transfer_handler,
160: void *opaque)
161: {
162: }
163:
1.1.1.8 root 164: static int fw_cfg_boot_set(void *opaque, const char *boot_device)
1.1.1.7 root 165: {
1.1.1.8 root 166: fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
1.1.1.7 root 167: return 0;
168: }
1.1 root 169:
1.1.1.11 root 170: static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171: const char *cmdline, const char *boot_devices,
172: ram_addr_t RAM_size, uint32_t kernel_size,
1.1.1.6 root 173: int width, int height, int depth,
1.1.1.7 root 174: int nvram_machine_id, const char *arch)
1.1 root 175: {
1.1.1.6 root 176: unsigned int i;
177: uint32_t start, end;
178: uint8_t image[0x1ff0];
179: struct OpenBIOS_nvpart_v1 *part_header;
180:
181: memset(image, '\0', sizeof(image));
1.1 root 182:
1.1.1.8 root 183: start = 0;
1.1.1.6 root 184:
185: // OpenBIOS nvram variables
186: // Variable partition
187: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188: part_header->signature = OPENBIOS_PART_SYSTEM;
1.1.1.7 root 189: pstrcpy(part_header->name, sizeof(part_header->name), "system");
1.1.1.6 root 190:
191: end = start + sizeof(struct OpenBIOS_nvpart_v1);
192: for (i = 0; i < nb_prom_envs; i++)
193: end = OpenBIOS_set_var(image, end, prom_envs[i]);
194:
195: // End marker
196: image[end++] = '\0';
197:
198: end = start + ((end - start + 15) & ~15);
199: OpenBIOS_finish_partition(part_header, end - start);
200:
201: // free partition
202: start = end;
203: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204: part_header->signature = OPENBIOS_PART_FREE;
1.1.1.7 root 205: pstrcpy(part_header->name, sizeof(part_header->name), "free");
1.1.1.6 root 206:
207: end = 0x1fd0;
208: OpenBIOS_finish_partition(part_header, end - start);
209:
1.1.1.7 root 210: Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211: nvram_machine_id);
1.1.1.6 root 212:
213: for (i = 0; i < sizeof(image); i++)
214: m48t59_write(nvram, i, image[i]);
1.1 root 215: }
216:
1.1.1.10 root 217: static DeviceState *slavio_intctl;
1.1 root 218:
1.1.1.14 root 219: void sun4m_pic_info(Monitor *mon)
1.1 root 220: {
1.1.1.6 root 221: if (slavio_intctl)
1.1.1.8 root 222: slavio_pic_info(mon, slavio_intctl);
1.1 root 223: }
224:
1.1.1.14 root 225: void sun4m_irq_info(Monitor *mon)
1.1 root 226: {
1.1.1.6 root 227: if (slavio_intctl)
1.1.1.8 root 228: slavio_irq_info(mon, slavio_intctl);
1.1 root 229: }
230:
1.1.1.15! root 231: void cpu_check_irqs(CPUSPARCState *env)
1.1 root 232: {
1.1.1.6 root 233: if (env->pil_in && (env->interrupt_index == 0 ||
234: (env->interrupt_index & ~15) == TT_EXTINT)) {
235: unsigned int i;
236:
237: for (i = 15; i > 0; i--) {
238: if (env->pil_in & (1 << i)) {
239: int old_interrupt = env->interrupt_index;
240:
241: env->interrupt_index = TT_EXTINT | i;
1.1.1.7 root 242: if (old_interrupt != env->interrupt_index) {
1.1.1.12 root 243: trace_sun4m_cpu_interrupt(i);
1.1.1.6 root 244: cpu_interrupt(env, CPU_INTERRUPT_HARD);
1.1.1.7 root 245: }
1.1.1.6 root 246: break;
247: }
248: }
249: } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
1.1.1.12 root 250: trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
1.1.1.6 root 251: env->interrupt_index = 0;
252: cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253: }
1.1 root 254: }
255:
1.1.1.15! root 256: static void cpu_kick_irq(CPUSPARCState *env)
1.1.1.13 root 257: {
258: env->halted = 0;
259: cpu_check_irqs(env);
260: qemu_cpu_kick(env);
261: }
262:
1.1.1.6 root 263: static void cpu_set_irq(void *opaque, int irq, int level)
1.1.1.4 root 264: {
1.1.1.15! root 265: CPUSPARCState *env = opaque;
1.1.1.6 root 266:
267: if (level) {
1.1.1.12 root 268: trace_sun4m_cpu_set_irq_raise(irq);
1.1.1.6 root 269: env->pil_in |= 1 << irq;
1.1.1.13 root 270: cpu_kick_irq(env);
1.1.1.6 root 271: } else {
1.1.1.12 root 272: trace_sun4m_cpu_set_irq_lower(irq);
1.1.1.6 root 273: env->pil_in &= ~(1 << irq);
274: cpu_check_irqs(env);
275: }
1.1.1.4 root 276: }
277:
1.1.1.6 root 278: static void dummy_cpu_set_irq(void *opaque, int irq, int level)
1.1.1.2 root 279: {
280: }
281:
282: static void main_cpu_reset(void *opaque)
283: {
1.1.1.15! root 284: CPUSPARCState *env = opaque;
1.1.1.6 root 285:
1.1.1.15! root 286: cpu_state_reset(env);
1.1.1.6 root 287: env->halted = 0;
1.1.1.2 root 288: }
289:
1.1.1.6 root 290: static void secondary_cpu_reset(void *opaque)
1.1 root 291: {
1.1.1.15! root 292: CPUSPARCState *env = opaque;
1.1.1.6 root 293:
1.1.1.15! root 294: cpu_state_reset(env);
1.1.1.6 root 295: env->halted = 1;
296: }
297:
1.1.1.7 root 298: static void cpu_halt_signal(void *opaque, int irq, int level)
299: {
300: if (level && cpu_single_env)
301: cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
302: }
303:
1.1.1.11 root 304: static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
305: {
306: return addr - 0xf0000000ULL;
307: }
308:
1.1.1.6 root 309: static unsigned long sun4m_load_kernel(const char *kernel_filename,
1.1.1.7 root 310: const char *initrd_filename,
311: ram_addr_t RAM_size)
1.1.1.6 root 312: {
313: int linux_boot;
1.1 root 314: unsigned int i;
1.1.1.6 root 315: long initrd_size, kernel_size;
1.1.1.10 root 316: uint8_t *ptr;
1.1 root 317:
318: linux_boot = (kernel_filename != NULL);
319:
1.1.1.6 root 320: kernel_size = 0;
321: if (linux_boot) {
1.1.1.10 root 322: int bswap_needed;
323:
324: #ifdef BSWAP_NEEDED
325: bswap_needed = 1;
326: #else
327: bswap_needed = 0;
328: #endif
1.1.1.11 root 329: kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
330: NULL, NULL, NULL, 1, ELF_MACHINE, 0);
1.1.1.6 root 331: if (kernel_size < 0)
1.1.1.7 root 332: kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
1.1.1.10 root 333: RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
334: TARGET_PAGE_SIZE);
1.1.1.6 root 335: if (kernel_size < 0)
1.1.1.7 root 336: kernel_size = load_image_targphys(kernel_filename,
337: KERNEL_LOAD_ADDR,
338: RAM_size - KERNEL_LOAD_ADDR);
1.1.1.6 root 339: if (kernel_size < 0) {
340: fprintf(stderr, "qemu: could not load kernel '%s'\n",
341: kernel_filename);
342: exit(1);
343: }
344:
345: /* load initrd */
346: initrd_size = 0;
347: if (initrd_filename) {
1.1.1.7 root 348: initrd_size = load_image_targphys(initrd_filename,
349: INITRD_LOAD_ADDR,
350: RAM_size - INITRD_LOAD_ADDR);
1.1.1.6 root 351: if (initrd_size < 0) {
352: fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
353: initrd_filename);
354: exit(1);
355: }
356: }
357: if (initrd_size > 0) {
358: for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
1.1.1.10 root 359: ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
360: if (ldl_p(ptr) == 0x48647253) { // HdrS
361: stl_p(ptr + 16, INITRD_LOAD_ADDR);
362: stl_p(ptr + 20, initrd_size);
1.1.1.6 root 363: break;
364: }
365: }
366: }
367: }
368: return kernel_size;
369: }
370:
1.1.1.10 root 371: static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
372: {
373: DeviceState *dev;
374: SysBusDevice *s;
375:
376: dev = qdev_create(NULL, "iommu");
377: qdev_prop_set_uint32(dev, "version", version);
378: qdev_init_nofail(dev);
379: s = sysbus_from_qdev(dev);
380: sysbus_connect_irq(s, 0, irq);
381: sysbus_mmio_map(s, 0, addr);
382:
383: return s;
384: }
385:
386: static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1.1.1.12 root 387: void *iommu, qemu_irq *dev_irq, int is_ledma)
1.1.1.10 root 388: {
389: DeviceState *dev;
390: SysBusDevice *s;
391:
392: dev = qdev_create(NULL, "sparc32_dma");
393: qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
1.1.1.12 root 394: qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
1.1.1.10 root 395: qdev_init_nofail(dev);
396: s = sysbus_from_qdev(dev);
397: sysbus_connect_irq(s, 0, parent_irq);
398: *dev_irq = qdev_get_gpio_in(dev, 0);
399: sysbus_mmio_map(s, 0, daddr);
400:
401: return s;
402: }
403:
1.1.1.8 root 404: static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
1.1.1.10 root 405: void *dma_opaque, qemu_irq irq)
1.1.1.8 root 406: {
407: DeviceState *dev;
408: SysBusDevice *s;
1.1.1.10 root 409: qemu_irq reset;
1.1.1.8 root 410:
411: qemu_check_nic_model(&nd_table[0], "lance");
412:
413: dev = qdev_create(NULL, "lance");
1.1.1.10 root 414: qdev_set_nic_properties(dev, nd);
1.1.1.9 root 415: qdev_prop_set_ptr(dev, "dma", dma_opaque);
1.1.1.10 root 416: qdev_init_nofail(dev);
1.1.1.8 root 417: s = sysbus_from_qdev(dev);
418: sysbus_mmio_map(s, 0, leaddr);
419: sysbus_connect_irq(s, 0, irq);
1.1.1.10 root 420: reset = qdev_get_gpio_in(dev, 0);
421: qdev_connect_gpio_out(dma_opaque, 0, reset);
422: }
423:
424: static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
425: target_phys_addr_t addrg,
426: qemu_irq **parent_irq)
427: {
428: DeviceState *dev;
429: SysBusDevice *s;
430: unsigned int i, j;
431:
432: dev = qdev_create(NULL, "slavio_intctl");
433: qdev_init_nofail(dev);
434:
435: s = sysbus_from_qdev(dev);
436:
437: for (i = 0; i < MAX_CPUS; i++) {
438: for (j = 0; j < MAX_PILS; j++) {
439: sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
440: }
441: }
442: sysbus_mmio_map(s, 0, addrg);
443: for (i = 0; i < MAX_CPUS; i++) {
444: sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
445: }
446:
447: return dev;
448: }
449:
450: #define SYS_TIMER_OFFSET 0x10000ULL
451: #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
452:
453: static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
454: qemu_irq *cpu_irqs, unsigned int num_cpus)
455: {
456: DeviceState *dev;
457: SysBusDevice *s;
458: unsigned int i;
459:
460: dev = qdev_create(NULL, "slavio_timer");
461: qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
462: qdev_init_nofail(dev);
463: s = sysbus_from_qdev(dev);
464: sysbus_connect_irq(s, 0, master_irq);
465: sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
466:
467: for (i = 0; i < MAX_CPUS; i++) {
468: sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
469: sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
470: }
471: }
472:
473: #define MISC_LEDS 0x01600000
474: #define MISC_CFG 0x01800000
475: #define MISC_DIAG 0x01a00000
476: #define MISC_MDM 0x01b00000
477: #define MISC_SYS 0x01f00000
478:
479: static void slavio_misc_init(target_phys_addr_t base,
480: target_phys_addr_t aux1_base,
481: target_phys_addr_t aux2_base, qemu_irq irq,
482: qemu_irq fdc_tc)
483: {
484: DeviceState *dev;
485: SysBusDevice *s;
486:
487: dev = qdev_create(NULL, "slavio_misc");
488: qdev_init_nofail(dev);
489: s = sysbus_from_qdev(dev);
490: if (base) {
491: /* 8 bit registers */
492: /* Slavio control */
493: sysbus_mmio_map(s, 0, base + MISC_CFG);
494: /* Diagnostics */
495: sysbus_mmio_map(s, 1, base + MISC_DIAG);
496: /* Modem control */
497: sysbus_mmio_map(s, 2, base + MISC_MDM);
498: /* 16 bit registers */
499: /* ss600mp diag LEDs */
500: sysbus_mmio_map(s, 3, base + MISC_LEDS);
501: /* 32 bit registers */
502: /* System control */
503: sysbus_mmio_map(s, 4, base + MISC_SYS);
504: }
505: if (aux1_base) {
506: /* AUX 1 (Misc System Functions) */
507: sysbus_mmio_map(s, 5, aux1_base);
508: }
509: if (aux2_base) {
510: /* AUX 2 (Software Powerdown Control) */
511: sysbus_mmio_map(s, 6, aux2_base);
512: }
513: sysbus_connect_irq(s, 0, irq);
514: sysbus_connect_irq(s, 1, fdc_tc);
515: qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
516: }
517:
518: static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
519: {
520: DeviceState *dev;
521: SysBusDevice *s;
522:
523: dev = qdev_create(NULL, "eccmemctl");
524: qdev_prop_set_uint32(dev, "version", version);
525: qdev_init_nofail(dev);
526: s = sysbus_from_qdev(dev);
527: sysbus_connect_irq(s, 0, irq);
528: sysbus_mmio_map(s, 0, base);
529: if (version == 0) { // SS-600MP only
530: sysbus_mmio_map(s, 1, base + 0x1000);
531: }
532: }
533:
534: static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
535: {
536: DeviceState *dev;
537: SysBusDevice *s;
538:
539: dev = qdev_create(NULL, "apc");
540: qdev_init_nofail(dev);
541: s = sysbus_from_qdev(dev);
542: /* Power management (APC) XXX: not a Slavio device */
543: sysbus_mmio_map(s, 0, power_base);
544: sysbus_connect_irq(s, 0, cpu_halt);
545: }
546:
547: static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
548: int height, int depth)
549: {
550: DeviceState *dev;
551: SysBusDevice *s;
552:
553: dev = qdev_create(NULL, "SUNW,tcx");
554: qdev_prop_set_taddr(dev, "addr", addr);
555: qdev_prop_set_uint32(dev, "vram_size", vram_size);
556: qdev_prop_set_uint16(dev, "width", width);
557: qdev_prop_set_uint16(dev, "height", height);
558: qdev_prop_set_uint16(dev, "depth", depth);
559: qdev_init_nofail(dev);
560: s = sysbus_from_qdev(dev);
561: /* 8-bit plane */
562: sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
563: /* DAC */
564: sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
565: /* TEC (dummy) */
566: sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
567: /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
568: sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
569: if (depth == 24) {
570: /* 24-bit plane */
571: sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
572: /* Control plane */
573: sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
574: } else {
575: /* THC 8 bit (dummy) */
576: sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
577: }
1.1.1.8 root 578: }
579:
580: /* NCR89C100/MACIO Internal ID register */
581: static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
582:
583: static void idreg_init(target_phys_addr_t addr)
584: {
585: DeviceState *dev;
586: SysBusDevice *s;
587:
588: dev = qdev_create(NULL, "macio_idreg");
1.1.1.10 root 589: qdev_init_nofail(dev);
1.1.1.8 root 590: s = sysbus_from_qdev(dev);
591:
592: sysbus_mmio_map(s, 0, addr);
593: cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
594: }
595:
1.1.1.14 root 596: typedef struct IDRegState {
597: SysBusDevice busdev;
598: MemoryRegion mem;
599: } IDRegState;
600:
1.1.1.10 root 601: static int idreg_init1(SysBusDevice *dev)
1.1.1.8 root 602: {
1.1.1.14 root 603: IDRegState *s = FROM_SYSBUS(IDRegState, dev);
1.1.1.8 root 604:
1.1.1.15! root 605: memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
! 606: vmstate_register_ram_global(&s->mem);
1.1.1.14 root 607: memory_region_set_readonly(&s->mem, true);
1.1.1.15! root 608: sysbus_init_mmio(dev, &s->mem);
1.1.1.10 root 609: return 0;
1.1.1.8 root 610: }
611:
1.1.1.15! root 612: static void idreg_class_init(ObjectClass *klass, void *data)
1.1.1.8 root 613: {
1.1.1.15! root 614: SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
! 615:
! 616: k->init = idreg_init1;
1.1.1.8 root 617: }
618:
1.1.1.15! root 619: static TypeInfo idreg_info = {
! 620: .name = "macio_idreg",
! 621: .parent = TYPE_SYS_BUS_DEVICE,
! 622: .instance_size = sizeof(IDRegState),
! 623: .class_init = idreg_class_init,
! 624: };
1.1.1.8 root 625:
1.1.1.14 root 626: typedef struct AFXState {
627: SysBusDevice busdev;
628: MemoryRegion mem;
629: } AFXState;
630:
1.1.1.11 root 631: /* SS-5 TCX AFX register */
632: static void afx_init(target_phys_addr_t addr)
633: {
634: DeviceState *dev;
635: SysBusDevice *s;
636:
637: dev = qdev_create(NULL, "tcx_afx");
638: qdev_init_nofail(dev);
639: s = sysbus_from_qdev(dev);
640:
641: sysbus_mmio_map(s, 0, addr);
642: }
643:
644: static int afx_init1(SysBusDevice *dev)
645: {
1.1.1.14 root 646: AFXState *s = FROM_SYSBUS(AFXState, dev);
1.1.1.11 root 647:
1.1.1.15! root 648: memory_region_init_ram(&s->mem, "sun4m.afx", 4);
! 649: vmstate_register_ram_global(&s->mem);
! 650: sysbus_init_mmio(dev, &s->mem);
1.1.1.11 root 651: return 0;
652: }
653:
1.1.1.15! root 654: static void afx_class_init(ObjectClass *klass, void *data)
1.1.1.11 root 655: {
1.1.1.15! root 656: SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
! 657:
! 658: k->init = afx_init1;
1.1.1.11 root 659: }
660:
1.1.1.15! root 661: static TypeInfo afx_info = {
! 662: .name = "tcx_afx",
! 663: .parent = TYPE_SYS_BUS_DEVICE,
! 664: .instance_size = sizeof(AFXState),
! 665: .class_init = afx_class_init,
! 666: };
1.1.1.11 root 667:
1.1.1.14 root 668: typedef struct PROMState {
669: SysBusDevice busdev;
670: MemoryRegion prom;
671: } PROMState;
672:
1.1.1.8 root 673: /* Boot PROM (OpenBIOS) */
1.1.1.11 root 674: static uint64_t translate_prom_address(void *opaque, uint64_t addr)
675: {
676: target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
677: return addr + *base_addr - PROM_VADDR;
678: }
679:
1.1.1.8 root 680: static void prom_init(target_phys_addr_t addr, const char *bios_name)
681: {
682: DeviceState *dev;
683: SysBusDevice *s;
684: char *filename;
685: int ret;
686:
687: dev = qdev_create(NULL, "openprom");
1.1.1.10 root 688: qdev_init_nofail(dev);
1.1.1.8 root 689: s = sysbus_from_qdev(dev);
690:
691: sysbus_mmio_map(s, 0, addr);
692:
693: /* load boot prom */
694: if (bios_name == NULL) {
695: bios_name = PROM_FILENAME;
696: }
697: filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
698: if (filename) {
1.1.1.11 root 699: ret = load_elf(filename, translate_prom_address, &addr, NULL,
700: NULL, NULL, 1, ELF_MACHINE, 0);
1.1.1.8 root 701: if (ret < 0 || ret > PROM_SIZE_MAX) {
702: ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
703: }
1.1.1.14 root 704: g_free(filename);
1.1.1.8 root 705: } else {
706: ret = -1;
707: }
708: if (ret < 0 || ret > PROM_SIZE_MAX) {
709: fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
710: exit(1);
711: }
712: }
713:
1.1.1.10 root 714: static int prom_init1(SysBusDevice *dev)
1.1.1.8 root 715: {
1.1.1.14 root 716: PROMState *s = FROM_SYSBUS(PROMState, dev);
1.1.1.8 root 717:
1.1.1.15! root 718: memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
! 719: vmstate_register_ram_global(&s->prom);
1.1.1.14 root 720: memory_region_set_readonly(&s->prom, true);
1.1.1.15! root 721: sysbus_init_mmio(dev, &s->prom);
1.1.1.10 root 722: return 0;
1.1.1.8 root 723: }
724:
1.1.1.15! root 725: static Property prom_properties[] = {
! 726: {/* end of property list */},
1.1.1.8 root 727: };
728:
1.1.1.15! root 729: static void prom_class_init(ObjectClass *klass, void *data)
1.1.1.8 root 730: {
1.1.1.15! root 731: DeviceClass *dc = DEVICE_CLASS(klass);
! 732: SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
! 733:
! 734: k->init = prom_init1;
! 735: dc->props = prom_properties;
1.1.1.8 root 736: }
737:
1.1.1.15! root 738: static TypeInfo prom_info = {
! 739: .name = "openprom",
! 740: .parent = TYPE_SYS_BUS_DEVICE,
! 741: .instance_size = sizeof(PROMState),
! 742: .class_init = prom_class_init,
! 743: };
1.1.1.8 root 744:
745: typedef struct RamDevice
746: {
747: SysBusDevice busdev;
1.1.1.14 root 748: MemoryRegion ram;
1.1.1.10 root 749: uint64_t size;
1.1.1.8 root 750: } RamDevice;
751:
752: /* System RAM */
1.1.1.10 root 753: static int ram_init1(SysBusDevice *dev)
1.1.1.8 root 754: {
755: RamDevice *d = FROM_SYSBUS(RamDevice, dev);
756:
1.1.1.15! root 757: memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
! 758: vmstate_register_ram_global(&d->ram);
! 759: sysbus_init_mmio(dev, &d->ram);
1.1.1.10 root 760: return 0;
1.1.1.8 root 761: }
762:
763: static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
764: uint64_t max_mem)
765: {
766: DeviceState *dev;
767: SysBusDevice *s;
768: RamDevice *d;
769:
770: /* allocate RAM */
771: if ((uint64_t)RAM_size > max_mem) {
772: fprintf(stderr,
773: "qemu: Too much memory for this machine: %d, maximum %d\n",
774: (unsigned int)(RAM_size / (1024 * 1024)),
775: (unsigned int)(max_mem / (1024 * 1024)));
776: exit(1);
777: }
778: dev = qdev_create(NULL, "memory");
779: s = sysbus_from_qdev(dev);
780:
781: d = FROM_SYSBUS(RamDevice, s);
782: d->size = RAM_size;
1.1.1.10 root 783: qdev_init_nofail(dev);
1.1.1.8 root 784:
785: sysbus_mmio_map(s, 0, addr);
786: }
787:
1.1.1.15! root 788: static Property ram_properties[] = {
! 789: DEFINE_PROP_UINT64("size", RamDevice, size, 0),
! 790: DEFINE_PROP_END_OF_LIST(),
1.1.1.8 root 791: };
792:
1.1.1.15! root 793: static void ram_class_init(ObjectClass *klass, void *data)
1.1.1.8 root 794: {
1.1.1.15! root 795: DeviceClass *dc = DEVICE_CLASS(klass);
! 796: SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
! 797:
! 798: k->init = ram_init1;
! 799: dc->props = ram_properties;
1.1.1.8 root 800: }
801:
1.1.1.15! root 802: static TypeInfo ram_info = {
! 803: .name = "memory",
! 804: .parent = TYPE_SYS_BUS_DEVICE,
! 805: .instance_size = sizeof(RamDevice),
! 806: .class_init = ram_class_init,
! 807: };
1.1.1.8 root 808:
1.1.1.11 root 809: static void cpu_devinit(const char *cpu_model, unsigned int id,
810: uint64_t prom_addr, qemu_irq **cpu_irqs)
1.1.1.8 root 811: {
1.1.1.15! root 812: CPUSPARCState *env;
1.1.1.8 root 813:
814: env = cpu_init(cpu_model);
815: if (!env) {
816: fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
817: exit(1);
818: }
819:
820: cpu_sparc_set_id(env, id);
821: if (id == 0) {
822: qemu_register_reset(main_cpu_reset, env);
823: } else {
824: qemu_register_reset(secondary_cpu_reset, env);
825: env->halted = 1;
826: }
827: *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
828: env->prom_addr = prom_addr;
829: }
830:
1.1.1.7 root 831: static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
1.1.1.6 root 832: const char *boot_device,
1.1.1.7 root 833: const char *kernel_filename,
1.1.1.6 root 834: const char *kernel_cmdline,
835: const char *initrd_filename, const char *cpu_model)
836: {
837: unsigned int i;
1.1.1.8 root 838: void *iommu, *espdma, *ledma, *nvram;
839: qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
840: espdma_irq, ledma_irq;
1.1.1.12 root 841: qemu_irq esp_reset, dma_enable;
1.1.1.8 root 842: qemu_irq fdc_tc;
1.1.1.7 root 843: qemu_irq *cpu_halt;
844: unsigned long kernel_size;
1.1.1.10 root 845: DriveInfo *fd[MAX_FD];
1.1.1.7 root 846: void *fw_cfg;
1.1.1.11 root 847: unsigned int num_vsimms;
1.1.1.6 root 848:
1.1.1.2 root 849: /* init CPUs */
1.1.1.6 root 850: if (!cpu_model)
851: cpu_model = hwdef->default_cpu_model;
852:
1.1.1.2 root 853: for(i = 0; i < smp_cpus; i++) {
1.1.1.11 root 854: cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1.1.1.2 root 855: }
1.1.1.6 root 856:
857: for (i = smp_cpus; i < MAX_CPUS; i++)
858: cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
859:
860:
1.1.1.8 root 861: /* set up devices */
862: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.11 root 863: /* models without ECC don't trap when missing ram is accessed */
864: if (!hwdef->ecc_base) {
865: empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
866: }
1.1 root 867:
1.1.1.8 root 868: prom_init(hwdef->slavio_base, bios_name);
1.1.1.6 root 869:
1.1.1.10 root 870: slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
871: hwdef->intctl_base + 0x10000ULL,
872: cpu_irqs);
1.1.1.2 root 873:
1.1.1.8 root 874: for (i = 0; i < 32; i++) {
1.1.1.10 root 875: slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
1.1.1.8 root 876: }
877: for (i = 0; i < MAX_CPUS; i++) {
1.1.1.10 root 878: slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
1.1.1.8 root 879: }
1.1.1.6 root 880:
1.1.1.7 root 881: if (hwdef->idreg_base) {
1.1.1.8 root 882: idreg_init(hwdef->idreg_base);
1.1.1.3 root 883: }
1.1.1.6 root 884:
1.1.1.11 root 885: if (hwdef->afx_base) {
886: afx_init(hwdef->afx_base);
887: }
888:
1.1.1.6 root 889: iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1.1.1.10 root 890: slavio_irq[30]);
1.1.1.6 root 891:
1.1.1.11 root 892: if (hwdef->iommu_pad_base) {
893: /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
894: Software shouldn't use aliased addresses, neither should it crash
895: when does. Using empty_slot instead of aliasing can help with
896: debugging such accesses */
897: empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
898: }
899:
1.1.1.10 root 900: espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
1.1.1.12 root 901: iommu, &espdma_irq, 0);
1.1.1.6 root 902:
903: ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1.1.1.12 root 904: slavio_irq[16], iommu, &ledma_irq, 1);
1.1.1.6 root 905:
906: if (graphic_depth != 8 && graphic_depth != 24) {
907: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
908: exit (1);
909: }
1.1.1.11 root 910: num_vsimms = 0;
911: if (num_vsimms == 0) {
912: tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
913: graphic_depth);
914: }
915:
916: for (i = num_vsimms; i < MAX_VSIMMS; i++) {
917: /* vsimm registers probed by OBP */
918: if (hwdef->vsimm[i].reg_base) {
919: empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
920: }
921: }
922:
923: if (hwdef->sx_base) {
924: empty_slot_init(hwdef->sx_base, 0x2000);
925: }
1.1.1.6 root 926:
1.1.1.10 root 927: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1.1.1.6 root 928:
1.1.1.10 root 929: nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1.1.1.6 root 930:
1.1.1.10 root 931: slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
1.1.1.6 root 932:
1.1.1.10 root 933: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
1.1.1.8 root 934: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1.1.15! root 935: /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
! 936: Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1.1.1.10 root 937: escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
1.1.1.7 root 938: serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1.1.1.6 root 939:
1.1.1.7 root 940: cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
1.1.1.10 root 941: slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
942: slavio_irq[30], fdc_tc);
943:
1.1.1.8 root 944: if (hwdef->apc_base) {
945: apc_init(hwdef->apc_base, cpu_halt[0]);
946: }
1.1.1.7 root 947:
948: if (hwdef->fd_base) {
1.1.1.6 root 949: /* there is zero or one floppy drive */
1.1.1.7 root 950: memset(fd, 0, sizeof(fd));
1.1.1.10 root 951: fd[0] = drive_get(IF_FLOPPY, 0, 0);
952: sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1.1.1.8 root 953: &fdc_tc);
1.1.1.6 root 954: }
955:
956: if (drive_get_max_bus(IF_SCSI) > 0) {
957: fprintf(stderr, "qemu: too many SCSI bus\n");
958: exit(1);
959: }
960:
1.1.1.8 root 961: esp_init(hwdef->esp_base, 2,
962: espdma_memory_read, espdma_memory_write,
1.1.1.12 root 963: espdma, espdma_irq, &esp_reset, &dma_enable);
1.1.1.10 root 964:
1.1.1.12 root 965: qdev_connect_gpio_out(espdma, 0, esp_reset);
966: qdev_connect_gpio_out(espdma, 1, dma_enable);
1.1.1.8 root 967:
968: if (hwdef->cs_base) {
969: sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1.1.1.10 root 970: slavio_irq[5]);
1.1.1.6 root 971: }
972:
1.1.1.11 root 973: if (hwdef->dbri_base) {
974: /* ISDN chip with attached CS4215 audio codec */
975: /* prom space */
976: empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
977: /* reg space */
978: empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
979: }
980:
981: if (hwdef->bpp_base) {
982: /* parallel port */
983: empty_slot_init(hwdef->bpp_base, 0x20);
984: }
985:
1.1.1.7 root 986: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
987: RAM_size);
1.1.1.6 root 988:
989: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
990: boot_device, RAM_size, kernel_size, graphic_width,
1.1.1.7 root 991: graphic_height, graphic_depth, hwdef->nvram_machine_id,
992: "Sun4m");
1.1.1.6 root 993:
1.1.1.7 root 994: if (hwdef->ecc_base)
1.1.1.10 root 995: ecc_init(hwdef->ecc_base, slavio_irq[28],
1.1.1.7 root 996: hwdef->ecc_version);
997:
998: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
999: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1000: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1001: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1002: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1.1.1.8 root 1003: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1004: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1005: if (kernel_cmdline) {
1006: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1.1.1.10 root 1007: pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1.1.1.11 root 1008: fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1009: (uint8_t*)strdup(kernel_cmdline),
1010: strlen(kernel_cmdline) + 1);
1.1.1.12 root 1011: fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1012: strlen(kernel_cmdline) + 1);
1.1.1.8 root 1013: } else {
1014: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1.1.1.12 root 1015: fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1.1.1.8 root 1016: }
1017: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1018: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1019: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1020: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.7 root 1021: }
1022:
1023: enum {
1024: ss2_id = 0,
1025: ss5_id = 32,
1026: vger_id,
1027: lx_id,
1028: ss4_id,
1029: scls_id,
1030: sbook_id,
1031: ss10_id = 64,
1032: ss20_id,
1033: ss600mp_id,
1034: ss1000_id = 96,
1035: ss2000_id,
1036: };
1.1.1.6 root 1037:
1.1.1.7 root 1038: static const struct sun4m_hwdef sun4m_hwdefs[] = {
1.1.1.6 root 1039: /* SS-5 */
1040: {
1041: .iommu_base = 0x10000000,
1.1.1.11 root 1042: .iommu_pad_base = 0x10004000,
1043: .iommu_pad_len = 0x0fffb000,
1.1.1.6 root 1044: .tcx_base = 0x50000000,
1045: .cs_base = 0x6c000000,
1046: .slavio_base = 0x70000000,
1047: .ms_kb_base = 0x71000000,
1048: .serial_base = 0x71100000,
1049: .nvram_base = 0x71200000,
1050: .fd_base = 0x71400000,
1051: .counter_base = 0x71d00000,
1052: .intctl_base = 0x71e00000,
1053: .idreg_base = 0x78000000,
1054: .dma_base = 0x78400000,
1055: .esp_base = 0x78800000,
1056: .le_base = 0x78c00000,
1.1.1.7 root 1057: .apc_base = 0x6a000000,
1.1.1.11 root 1058: .afx_base = 0x6e000000,
1.1.1.7 root 1059: .aux1_base = 0x71900000,
1060: .aux2_base = 0x71910000,
1061: .nvram_machine_id = 0x80,
1062: .machine_id = ss5_id,
1.1.1.6 root 1063: .iommu_version = 0x05000000,
1064: .max_mem = 0x10000000,
1065: .default_cpu_model = "Fujitsu MB86904",
1066: },
1067: /* SS-10 */
1068: {
1069: .iommu_base = 0xfe0000000ULL,
1070: .tcx_base = 0xe20000000ULL,
1071: .slavio_base = 0xff0000000ULL,
1072: .ms_kb_base = 0xff1000000ULL,
1073: .serial_base = 0xff1100000ULL,
1074: .nvram_base = 0xff1200000ULL,
1075: .fd_base = 0xff1700000ULL,
1076: .counter_base = 0xff1300000ULL,
1077: .intctl_base = 0xff1400000ULL,
1078: .idreg_base = 0xef0000000ULL,
1079: .dma_base = 0xef0400000ULL,
1080: .esp_base = 0xef0800000ULL,
1081: .le_base = 0xef0c00000ULL,
1.1.1.7 root 1082: .apc_base = 0xefa000000ULL, // XXX should not exist
1083: .aux1_base = 0xff1800000ULL,
1084: .aux2_base = 0xff1a01000ULL,
1.1.1.6 root 1085: .ecc_base = 0xf00000000ULL,
1086: .ecc_version = 0x10000000, // version 0, implementation 1
1.1.1.7 root 1087: .nvram_machine_id = 0x72,
1088: .machine_id = ss10_id,
1.1.1.6 root 1089: .iommu_version = 0x03000000,
1.1.1.7 root 1090: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1091: .default_cpu_model = "TI SuperSparc II",
1092: },
1093: /* SS-600MP */
1094: {
1095: .iommu_base = 0xfe0000000ULL,
1096: .tcx_base = 0xe20000000ULL,
1097: .slavio_base = 0xff0000000ULL,
1098: .ms_kb_base = 0xff1000000ULL,
1099: .serial_base = 0xff1100000ULL,
1100: .nvram_base = 0xff1200000ULL,
1101: .counter_base = 0xff1300000ULL,
1102: .intctl_base = 0xff1400000ULL,
1103: .dma_base = 0xef0081000ULL,
1104: .esp_base = 0xef0080000ULL,
1105: .le_base = 0xef0060000ULL,
1.1.1.7 root 1106: .apc_base = 0xefa000000ULL, // XXX should not exist
1107: .aux1_base = 0xff1800000ULL,
1108: .aux2_base = 0xff1a01000ULL, // XXX should not exist
1.1.1.6 root 1109: .ecc_base = 0xf00000000ULL,
1110: .ecc_version = 0x00000000, // version 0, implementation 0
1.1.1.7 root 1111: .nvram_machine_id = 0x71,
1112: .machine_id = ss600mp_id,
1.1.1.6 root 1113: .iommu_version = 0x01000000,
1.1.1.7 root 1114: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1115: .default_cpu_model = "TI SuperSparc II",
1116: },
1117: /* SS-20 */
1118: {
1119: .iommu_base = 0xfe0000000ULL,
1120: .tcx_base = 0xe20000000ULL,
1121: .slavio_base = 0xff0000000ULL,
1122: .ms_kb_base = 0xff1000000ULL,
1123: .serial_base = 0xff1100000ULL,
1124: .nvram_base = 0xff1200000ULL,
1125: .fd_base = 0xff1700000ULL,
1126: .counter_base = 0xff1300000ULL,
1127: .intctl_base = 0xff1400000ULL,
1128: .idreg_base = 0xef0000000ULL,
1129: .dma_base = 0xef0400000ULL,
1130: .esp_base = 0xef0800000ULL,
1131: .le_base = 0xef0c00000ULL,
1.1.1.11 root 1132: .bpp_base = 0xef4800000ULL,
1.1.1.7 root 1133: .apc_base = 0xefa000000ULL, // XXX should not exist
1134: .aux1_base = 0xff1800000ULL,
1135: .aux2_base = 0xff1a01000ULL,
1.1.1.11 root 1136: .dbri_base = 0xee0000000ULL,
1137: .sx_base = 0xf80000000ULL,
1138: .vsimm = {
1139: {
1140: .reg_base = 0x9c000000ULL,
1141: .vram_base = 0xfc000000ULL
1142: }, {
1143: .reg_base = 0x90000000ULL,
1144: .vram_base = 0xf0000000ULL
1145: }, {
1146: .reg_base = 0x94000000ULL
1147: }, {
1148: .reg_base = 0x98000000ULL
1149: }
1150: },
1.1.1.6 root 1151: .ecc_base = 0xf00000000ULL,
1152: .ecc_version = 0x20000000, // version 0, implementation 2
1.1.1.7 root 1153: .nvram_machine_id = 0x72,
1154: .machine_id = ss20_id,
1.1.1.6 root 1155: .iommu_version = 0x13000000,
1.1.1.7 root 1156: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1157: .default_cpu_model = "TI SuperSparc II",
1158: },
1.1.1.7 root 1159: /* Voyager */
1.1.1.6 root 1160: {
1.1.1.7 root 1161: .iommu_base = 0x10000000,
1162: .tcx_base = 0x50000000,
1163: .slavio_base = 0x70000000,
1164: .ms_kb_base = 0x71000000,
1165: .serial_base = 0x71100000,
1166: .nvram_base = 0x71200000,
1167: .fd_base = 0x71400000,
1168: .counter_base = 0x71d00000,
1169: .intctl_base = 0x71e00000,
1170: .idreg_base = 0x78000000,
1171: .dma_base = 0x78400000,
1172: .esp_base = 0x78800000,
1173: .le_base = 0x78c00000,
1174: .apc_base = 0x71300000, // pmc
1175: .aux1_base = 0x71900000,
1176: .aux2_base = 0x71910000,
1177: .nvram_machine_id = 0x80,
1178: .machine_id = vger_id,
1179: .iommu_version = 0x05000000,
1.1.1.6 root 1180: .max_mem = 0x10000000,
1.1.1.7 root 1181: .default_cpu_model = "Fujitsu MB86904",
1182: },
1183: /* LX */
1184: {
1185: .iommu_base = 0x10000000,
1.1.1.11 root 1186: .iommu_pad_base = 0x10004000,
1187: .iommu_pad_len = 0x0fffb000,
1.1.1.7 root 1188: .tcx_base = 0x50000000,
1189: .slavio_base = 0x70000000,
1190: .ms_kb_base = 0x71000000,
1191: .serial_base = 0x71100000,
1192: .nvram_base = 0x71200000,
1193: .fd_base = 0x71400000,
1194: .counter_base = 0x71d00000,
1195: .intctl_base = 0x71e00000,
1196: .idreg_base = 0x78000000,
1197: .dma_base = 0x78400000,
1198: .esp_base = 0x78800000,
1199: .le_base = 0x78c00000,
1200: .aux1_base = 0x71900000,
1201: .aux2_base = 0x71910000,
1202: .nvram_machine_id = 0x80,
1203: .machine_id = lx_id,
1204: .iommu_version = 0x04000000,
1205: .max_mem = 0x10000000,
1206: .default_cpu_model = "TI MicroSparc I",
1207: },
1208: /* SS-4 */
1209: {
1210: .iommu_base = 0x10000000,
1211: .tcx_base = 0x50000000,
1212: .cs_base = 0x6c000000,
1213: .slavio_base = 0x70000000,
1214: .ms_kb_base = 0x71000000,
1215: .serial_base = 0x71100000,
1216: .nvram_base = 0x71200000,
1217: .fd_base = 0x71400000,
1218: .counter_base = 0x71d00000,
1219: .intctl_base = 0x71e00000,
1220: .idreg_base = 0x78000000,
1221: .dma_base = 0x78400000,
1222: .esp_base = 0x78800000,
1223: .le_base = 0x78c00000,
1224: .apc_base = 0x6a000000,
1225: .aux1_base = 0x71900000,
1226: .aux2_base = 0x71910000,
1227: .nvram_machine_id = 0x80,
1228: .machine_id = ss4_id,
1229: .iommu_version = 0x05000000,
1230: .max_mem = 0x10000000,
1231: .default_cpu_model = "Fujitsu MB86904",
1232: },
1233: /* SPARCClassic */
1234: {
1235: .iommu_base = 0x10000000,
1236: .tcx_base = 0x50000000,
1237: .slavio_base = 0x70000000,
1238: .ms_kb_base = 0x71000000,
1239: .serial_base = 0x71100000,
1240: .nvram_base = 0x71200000,
1241: .fd_base = 0x71400000,
1242: .counter_base = 0x71d00000,
1243: .intctl_base = 0x71e00000,
1244: .idreg_base = 0x78000000,
1245: .dma_base = 0x78400000,
1246: .esp_base = 0x78800000,
1247: .le_base = 0x78c00000,
1248: .apc_base = 0x6a000000,
1249: .aux1_base = 0x71900000,
1250: .aux2_base = 0x71910000,
1251: .nvram_machine_id = 0x80,
1252: .machine_id = scls_id,
1253: .iommu_version = 0x05000000,
1254: .max_mem = 0x10000000,
1255: .default_cpu_model = "TI MicroSparc I",
1256: },
1257: /* SPARCbook */
1258: {
1259: .iommu_base = 0x10000000,
1260: .tcx_base = 0x50000000, // XXX
1261: .slavio_base = 0x70000000,
1262: .ms_kb_base = 0x71000000,
1263: .serial_base = 0x71100000,
1264: .nvram_base = 0x71200000,
1265: .fd_base = 0x71400000,
1266: .counter_base = 0x71d00000,
1267: .intctl_base = 0x71e00000,
1268: .idreg_base = 0x78000000,
1269: .dma_base = 0x78400000,
1270: .esp_base = 0x78800000,
1271: .le_base = 0x78c00000,
1272: .apc_base = 0x6a000000,
1273: .aux1_base = 0x71900000,
1274: .aux2_base = 0x71910000,
1275: .nvram_machine_id = 0x80,
1276: .machine_id = sbook_id,
1277: .iommu_version = 0x05000000,
1278: .max_mem = 0x10000000,
1279: .default_cpu_model = "TI MicroSparc I",
1.1.1.6 root 1280: },
1281: };
1282:
1283: /* SPARCstation 5 hardware initialisation */
1.1.1.8 root 1284: static void ss5_init(ram_addr_t RAM_size,
1.1.1.7 root 1285: const char *boot_device,
1.1.1.6 root 1286: const char *kernel_filename, const char *kernel_cmdline,
1287: const char *initrd_filename, const char *cpu_model)
1288: {
1.1.1.7 root 1289: sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1290: kernel_cmdline, initrd_filename, cpu_model);
1291: }
1292:
1293: /* SPARCstation 10 hardware initialisation */
1.1.1.8 root 1294: static void ss10_init(ram_addr_t RAM_size,
1.1.1.7 root 1295: const char *boot_device,
1.1.1.6 root 1296: const char *kernel_filename, const char *kernel_cmdline,
1297: const char *initrd_filename, const char *cpu_model)
1298: {
1.1.1.7 root 1299: sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1300: kernel_cmdline, initrd_filename, cpu_model);
1301: }
1302:
1303: /* SPARCserver 600MP hardware initialisation */
1.1.1.8 root 1304: static void ss600mp_init(ram_addr_t RAM_size,
1.1.1.7 root 1305: const char *boot_device,
1306: const char *kernel_filename,
1307: const char *kernel_cmdline,
1.1.1.6 root 1308: const char *initrd_filename, const char *cpu_model)
1309: {
1.1.1.7 root 1310: sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1311: kernel_cmdline, initrd_filename, cpu_model);
1312: }
1313:
1314: /* SPARCstation 20 hardware initialisation */
1.1.1.8 root 1315: static void ss20_init(ram_addr_t RAM_size,
1.1.1.7 root 1316: const char *boot_device,
1.1.1.6 root 1317: const char *kernel_filename, const char *kernel_cmdline,
1318: const char *initrd_filename, const char *cpu_model)
1319: {
1.1.1.7 root 1320: sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1321: kernel_cmdline, initrd_filename, cpu_model);
1322: }
1323:
1.1.1.7 root 1324: /* SPARCstation Voyager hardware initialisation */
1.1.1.8 root 1325: static void vger_init(ram_addr_t RAM_size,
1.1.1.7 root 1326: const char *boot_device,
1327: const char *kernel_filename, const char *kernel_cmdline,
1328: const char *initrd_filename, const char *cpu_model)
1329: {
1330: sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1331: kernel_cmdline, initrd_filename, cpu_model);
1332: }
1333:
1334: /* SPARCstation LX hardware initialisation */
1.1.1.8 root 1335: static void ss_lx_init(ram_addr_t RAM_size,
1.1.1.7 root 1336: const char *boot_device,
1337: const char *kernel_filename, const char *kernel_cmdline,
1338: const char *initrd_filename, const char *cpu_model)
1339: {
1340: sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1341: kernel_cmdline, initrd_filename, cpu_model);
1342: }
1343:
1344: /* SPARCstation 4 hardware initialisation */
1.1.1.8 root 1345: static void ss4_init(ram_addr_t RAM_size,
1.1.1.7 root 1346: const char *boot_device,
1.1.1.6 root 1347: const char *kernel_filename, const char *kernel_cmdline,
1348: const char *initrd_filename, const char *cpu_model)
1349: {
1.1.1.7 root 1350: sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1351: kernel_cmdline, initrd_filename, cpu_model);
1352: }
1353:
1354: /* SPARCClassic hardware initialisation */
1.1.1.8 root 1355: static void scls_init(ram_addr_t RAM_size,
1.1.1.7 root 1356: const char *boot_device,
1357: const char *kernel_filename, const char *kernel_cmdline,
1358: const char *initrd_filename, const char *cpu_model)
1359: {
1360: sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1361: kernel_cmdline, initrd_filename, cpu_model);
1362: }
1363:
1364: /* SPARCbook hardware initialisation */
1.1.1.8 root 1365: static void sbook_init(ram_addr_t RAM_size,
1.1.1.7 root 1366: const char *boot_device,
1367: const char *kernel_filename, const char *kernel_cmdline,
1368: const char *initrd_filename, const char *cpu_model)
1369: {
1370: sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1371: kernel_cmdline, initrd_filename, cpu_model);
1372: }
1373:
1.1.1.8 root 1374: static QEMUMachine ss5_machine = {
1.1.1.7 root 1375: .name = "SS-5",
1376: .desc = "Sun4m platform, SPARCstation 5",
1377: .init = ss5_init,
1378: .use_scsi = 1,
1.1.1.8 root 1379: .is_default = 1,
1.1.1.6 root 1380: };
1381:
1.1.1.8 root 1382: static QEMUMachine ss10_machine = {
1.1.1.7 root 1383: .name = "SS-10",
1384: .desc = "Sun4m platform, SPARCstation 10",
1385: .init = ss10_init,
1386: .use_scsi = 1,
1387: .max_cpus = 4,
1.1.1.6 root 1388: };
1389:
1.1.1.8 root 1390: static QEMUMachine ss600mp_machine = {
1.1.1.7 root 1391: .name = "SS-600MP",
1392: .desc = "Sun4m platform, SPARCserver 600MP",
1393: .init = ss600mp_init,
1394: .use_scsi = 1,
1395: .max_cpus = 4,
1.1.1.6 root 1396: };
1397:
1.1.1.8 root 1398: static QEMUMachine ss20_machine = {
1.1.1.7 root 1399: .name = "SS-20",
1400: .desc = "Sun4m platform, SPARCstation 20",
1401: .init = ss20_init,
1402: .use_scsi = 1,
1403: .max_cpus = 4,
1.1.1.6 root 1404: };
1405:
1.1.1.8 root 1406: static QEMUMachine voyager_machine = {
1.1.1.7 root 1407: .name = "Voyager",
1408: .desc = "Sun4m platform, SPARCstation Voyager",
1409: .init = vger_init,
1410: .use_scsi = 1,
1411: };
1412:
1.1.1.8 root 1413: static QEMUMachine ss_lx_machine = {
1.1.1.7 root 1414: .name = "LX",
1415: .desc = "Sun4m platform, SPARCstation LX",
1416: .init = ss_lx_init,
1417: .use_scsi = 1,
1418: };
1419:
1.1.1.8 root 1420: static QEMUMachine ss4_machine = {
1.1.1.7 root 1421: .name = "SS-4",
1422: .desc = "Sun4m platform, SPARCstation 4",
1423: .init = ss4_init,
1424: .use_scsi = 1,
1425: };
1426:
1.1.1.8 root 1427: static QEMUMachine scls_machine = {
1.1.1.7 root 1428: .name = "SPARCClassic",
1429: .desc = "Sun4m platform, SPARCClassic",
1430: .init = scls_init,
1431: .use_scsi = 1,
1432: };
1433:
1.1.1.8 root 1434: static QEMUMachine sbook_machine = {
1.1.1.7 root 1435: .name = "SPARCbook",
1436: .desc = "Sun4m platform, SPARCbook",
1437: .init = sbook_init,
1438: .use_scsi = 1,
1.1.1.6 root 1439: };
1440:
1441: static const struct sun4d_hwdef sun4d_hwdefs[] = {
1442: /* SS-1000 */
1443: {
1444: .iounit_bases = {
1445: 0xfe0200000ULL,
1446: 0xfe1200000ULL,
1447: 0xfe2200000ULL,
1448: 0xfe3200000ULL,
1449: -1,
1450: },
1451: .tcx_base = 0x820000000ULL,
1452: .slavio_base = 0xf00000000ULL,
1453: .ms_kb_base = 0xf00240000ULL,
1454: .serial_base = 0xf00200000ULL,
1455: .nvram_base = 0xf00280000ULL,
1456: .counter_base = 0xf00300000ULL,
1457: .espdma_base = 0x800081000ULL,
1458: .esp_base = 0x800080000ULL,
1459: .ledma_base = 0x800040000ULL,
1460: .le_base = 0x800060000ULL,
1461: .sbi_base = 0xf02800000ULL,
1.1.1.7 root 1462: .nvram_machine_id = 0x80,
1463: .machine_id = ss1000_id,
1.1.1.6 root 1464: .iounit_version = 0x03000000,
1.1.1.7 root 1465: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1466: .default_cpu_model = "TI SuperSparc II",
1467: },
1468: /* SS-2000 */
1469: {
1470: .iounit_bases = {
1471: 0xfe0200000ULL,
1472: 0xfe1200000ULL,
1473: 0xfe2200000ULL,
1474: 0xfe3200000ULL,
1475: 0xfe4200000ULL,
1476: },
1477: .tcx_base = 0x820000000ULL,
1478: .slavio_base = 0xf00000000ULL,
1479: .ms_kb_base = 0xf00240000ULL,
1480: .serial_base = 0xf00200000ULL,
1481: .nvram_base = 0xf00280000ULL,
1482: .counter_base = 0xf00300000ULL,
1483: .espdma_base = 0x800081000ULL,
1484: .esp_base = 0x800080000ULL,
1485: .ledma_base = 0x800040000ULL,
1486: .le_base = 0x800060000ULL,
1487: .sbi_base = 0xf02800000ULL,
1.1.1.7 root 1488: .nvram_machine_id = 0x80,
1489: .machine_id = ss2000_id,
1.1.1.6 root 1490: .iounit_version = 0x03000000,
1.1.1.7 root 1491: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1492: .default_cpu_model = "TI SuperSparc II",
1493: },
1494: };
1495:
1.1.1.10 root 1496: static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1497: {
1498: DeviceState *dev;
1499: SysBusDevice *s;
1500: unsigned int i;
1501:
1502: dev = qdev_create(NULL, "sbi");
1503: qdev_init_nofail(dev);
1504:
1505: s = sysbus_from_qdev(dev);
1506:
1507: for (i = 0; i < MAX_CPUS; i++) {
1508: sysbus_connect_irq(s, i, *parent_irq[i]);
1509: }
1510:
1511: sysbus_mmio_map(s, 0, addr);
1512:
1513: return dev;
1514: }
1515:
1.1.1.7 root 1516: static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1.1.1.6 root 1517: const char *boot_device,
1.1.1.7 root 1518: const char *kernel_filename,
1.1.1.6 root 1519: const char *kernel_cmdline,
1520: const char *initrd_filename, const char *cpu_model)
1521: {
1522: unsigned int i;
1.1.1.10 root 1523: void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1524: qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1.1.1.8 root 1525: espdma_irq, ledma_irq;
1.1.1.12 root 1526: qemu_irq esp_reset, dma_enable;
1.1.1.7 root 1527: unsigned long kernel_size;
1528: void *fw_cfg;
1.1.1.10 root 1529: DeviceState *dev;
1.1.1.6 root 1530:
1531: /* init CPUs */
1532: if (!cpu_model)
1533: cpu_model = hwdef->default_cpu_model;
1534:
1.1.1.8 root 1535: for(i = 0; i < smp_cpus; i++) {
1.1.1.11 root 1536: cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1.1.1.6 root 1537: }
1538:
1539: for (i = smp_cpus; i < MAX_CPUS; i++)
1540: cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1541:
1.1.1.8 root 1542: /* set up devices */
1543: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.6 root 1544:
1.1.1.8 root 1545: prom_init(hwdef->slavio_base, bios_name);
1.1.1.6 root 1546:
1.1.1.10 root 1547: dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1548:
1549: for (i = 0; i < 32; i++) {
1550: sbi_irq[i] = qdev_get_gpio_in(dev, i);
1551: }
1552: for (i = 0; i < MAX_CPUS; i++) {
1553: sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1554: }
1.1.1.6 root 1555:
1556: for (i = 0; i < MAX_IOUNITS; i++)
1557: if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1558: iounits[i] = iommu_init(hwdef->iounit_bases[i],
1559: hwdef->iounit_version,
1.1.1.10 root 1560: sbi_irq[0]);
1.1.1.6 root 1561:
1.1.1.10 root 1562: espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1.1.1.12 root 1563: iounits[0], &espdma_irq, 0);
1.1.1.6 root 1564:
1.1.1.12 root 1565: /* should be lebuffer instead */
1.1.1.10 root 1566: ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1.1.1.12 root 1567: iounits[0], &ledma_irq, 0);
1.1.1.6 root 1568:
1569: if (graphic_depth != 8 && graphic_depth != 24) {
1570: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1571: exit (1);
1572: }
1.1.1.10 root 1573: tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1.1.1.8 root 1574: graphic_depth);
1.1.1.6 root 1575:
1.1.1.10 root 1576: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1.1.1.6 root 1577:
1.1.1.10 root 1578: nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1.1.1.6 root 1579:
1.1.1.10 root 1580: slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1.1.1.6 root 1581:
1.1.1.10 root 1582: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1.1.1.8 root 1583: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1.1.15! root 1584: /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
! 1585: Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1.1.1.10 root 1586: escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1.1.1.7 root 1587: serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1.1.1.6 root 1588:
1589: if (drive_get_max_bus(IF_SCSI) > 0) {
1590: fprintf(stderr, "qemu: too many SCSI bus\n");
1591: exit(1);
1592: }
1593:
1.1.1.8 root 1594: esp_init(hwdef->esp_base, 2,
1595: espdma_memory_read, espdma_memory_write,
1.1.1.12 root 1596: espdma, espdma_irq, &esp_reset, &dma_enable);
1597:
1598: qdev_connect_gpio_out(espdma, 0, esp_reset);
1599: qdev_connect_gpio_out(espdma, 1, dma_enable);
1.1.1.6 root 1600:
1.1.1.7 root 1601: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1602: RAM_size);
1.1.1.6 root 1603:
1604: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1605: boot_device, RAM_size, kernel_size, graphic_width,
1.1.1.7 root 1606: graphic_height, graphic_depth, hwdef->nvram_machine_id,
1607: "Sun4d");
1608:
1609: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1610: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1611: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1612: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1.1.1.8 root 1613: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1614: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1615: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1616: if (kernel_cmdline) {
1617: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1.1.1.10 root 1618: pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1.1.1.11 root 1619: fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1620: (uint8_t*)strdup(kernel_cmdline),
1621: strlen(kernel_cmdline) + 1);
1.1.1.8 root 1622: } else {
1623: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1624: }
1625: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1626: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1627: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1628: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.6 root 1629: }
1630:
1631: /* SPARCserver 1000 hardware initialisation */
1.1.1.8 root 1632: static void ss1000_init(ram_addr_t RAM_size,
1.1.1.7 root 1633: const char *boot_device,
1.1.1.6 root 1634: const char *kernel_filename, const char *kernel_cmdline,
1635: const char *initrd_filename, const char *cpu_model)
1636: {
1.1.1.7 root 1637: sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1638: kernel_cmdline, initrd_filename, cpu_model);
1.1 root 1639: }
1640:
1.1.1.6 root 1641: /* SPARCcenter 2000 hardware initialisation */
1.1.1.8 root 1642: static void ss2000_init(ram_addr_t RAM_size,
1.1.1.7 root 1643: const char *boot_device,
1.1.1.6 root 1644: const char *kernel_filename, const char *kernel_cmdline,
1645: const char *initrd_filename, const char *cpu_model)
1646: {
1.1.1.7 root 1647: sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1648: kernel_cmdline, initrd_filename, cpu_model);
1649: }
1650:
1.1.1.8 root 1651: static QEMUMachine ss1000_machine = {
1.1.1.7 root 1652: .name = "SS-1000",
1653: .desc = "Sun4d platform, SPARCserver 1000",
1654: .init = ss1000_init,
1655: .use_scsi = 1,
1656: .max_cpus = 8,
1.1.1.6 root 1657: };
1658:
1.1.1.8 root 1659: static QEMUMachine ss2000_machine = {
1.1.1.7 root 1660: .name = "SS-2000",
1661: .desc = "Sun4d platform, SPARCcenter 2000",
1662: .init = ss2000_init,
1663: .use_scsi = 1,
1664: .max_cpus = 20,
1665: };
1666:
1667: static const struct sun4c_hwdef sun4c_hwdefs[] = {
1668: /* SS-2 */
1669: {
1670: .iommu_base = 0xf8000000,
1671: .tcx_base = 0xfe000000,
1672: .slavio_base = 0xf6000000,
1673: .intctl_base = 0xf5000000,
1674: .counter_base = 0xf3000000,
1675: .ms_kb_base = 0xf0000000,
1676: .serial_base = 0xf1000000,
1677: .nvram_base = 0xf2000000,
1678: .fd_base = 0xf7200000,
1679: .dma_base = 0xf8400000,
1680: .esp_base = 0xf8800000,
1681: .le_base = 0xf8c00000,
1682: .aux1_base = 0xf7400003,
1683: .nvram_machine_id = 0x55,
1684: .machine_id = ss2_id,
1685: .max_mem = 0x10000000,
1686: .default_cpu_model = "Cypress CY7C601",
1687: },
1688: };
1689:
1.1.1.10 root 1690: static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1691: qemu_irq *parent_irq)
1692: {
1693: DeviceState *dev;
1694: SysBusDevice *s;
1695: unsigned int i;
1696:
1697: dev = qdev_create(NULL, "sun4c_intctl");
1698: qdev_init_nofail(dev);
1699:
1700: s = sysbus_from_qdev(dev);
1701:
1702: for (i = 0; i < MAX_PILS; i++) {
1703: sysbus_connect_irq(s, i, parent_irq[i]);
1704: }
1705: sysbus_mmio_map(s, 0, addr);
1706:
1707: return dev;
1708: }
1709:
1.1.1.7 root 1710: static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1711: const char *boot_device,
1712: const char *kernel_filename,
1713: const char *kernel_cmdline,
1714: const char *initrd_filename, const char *cpu_model)
1715: {
1.1.1.8 root 1716: void *iommu, *espdma, *ledma, *nvram;
1.1.1.10 root 1717: qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1.1.1.12 root 1718: qemu_irq esp_reset, dma_enable;
1.1.1.8 root 1719: qemu_irq fdc_tc;
1.1.1.7 root 1720: unsigned long kernel_size;
1.1.1.10 root 1721: DriveInfo *fd[MAX_FD];
1.1.1.7 root 1722: void *fw_cfg;
1.1.1.10 root 1723: DeviceState *dev;
1724: unsigned int i;
1.1.1.7 root 1725:
1726: /* init CPU */
1727: if (!cpu_model)
1728: cpu_model = hwdef->default_cpu_model;
1729:
1.1.1.11 root 1730: cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1.1.1.7 root 1731:
1.1.1.8 root 1732: /* set up devices */
1733: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.7 root 1734:
1.1.1.8 root 1735: prom_init(hwdef->slavio_base, bios_name);
1.1.1.7 root 1736:
1.1.1.10 root 1737: dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1738:
1739: for (i = 0; i < 8; i++) {
1740: slavio_irq[i] = qdev_get_gpio_in(dev, i);
1741: }
1.1.1.7 root 1742:
1743: iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1.1.1.10 root 1744: slavio_irq[1]);
1.1.1.7 root 1745:
1.1.1.10 root 1746: espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1.1.1.12 root 1747: iommu, &espdma_irq, 0);
1.1.1.7 root 1748:
1749: ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1.1.1.12 root 1750: slavio_irq[3], iommu, &ledma_irq, 1);
1.1.1.7 root 1751:
1752: if (graphic_depth != 8 && graphic_depth != 24) {
1753: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1754: exit (1);
1755: }
1.1.1.10 root 1756: tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1.1.1.8 root 1757: graphic_depth);
1.1.1.7 root 1758:
1.1.1.10 root 1759: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1.1.1.7 root 1760:
1.1.1.10 root 1761: nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1.1.1.7 root 1762:
1.1.1.10 root 1763: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1.1.1.8 root 1764: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1.1.15! root 1765: /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
! 1766: Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1.1.1.10 root 1767: escc_init(hwdef->serial_base, slavio_irq[1],
1768: slavio_irq[1], serial_hds[0], serial_hds[1],
1.1.1.7 root 1769: ESCC_CLOCK, 1);
1770:
1.1.1.10 root 1771: slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1.1.1.7 root 1772:
1773: if (hwdef->fd_base != (target_phys_addr_t)-1) {
1774: /* there is zero or one floppy drive */
1775: memset(fd, 0, sizeof(fd));
1.1.1.10 root 1776: fd[0] = drive_get(IF_FLOPPY, 0, 0);
1777: sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1.1.1.8 root 1778: &fdc_tc);
1.1.1.7 root 1779: }
1780:
1781: if (drive_get_max_bus(IF_SCSI) > 0) {
1782: fprintf(stderr, "qemu: too many SCSI bus\n");
1783: exit(1);
1784: }
1785:
1.1.1.8 root 1786: esp_init(hwdef->esp_base, 2,
1787: espdma_memory_read, espdma_memory_write,
1.1.1.12 root 1788: espdma, espdma_irq, &esp_reset, &dma_enable);
1789:
1790: qdev_connect_gpio_out(espdma, 0, esp_reset);
1791: qdev_connect_gpio_out(espdma, 1, dma_enable);
1.1.1.7 root 1792:
1793: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1794: RAM_size);
1795:
1796: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1797: boot_device, RAM_size, kernel_size, graphic_width,
1798: graphic_height, graphic_depth, hwdef->nvram_machine_id,
1799: "Sun4c");
1800:
1801: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1802: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1803: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1804: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1.1.1.8 root 1805: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1806: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1807: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1808: if (kernel_cmdline) {
1809: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1.1.1.10 root 1810: pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1.1.1.11 root 1811: fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1812: (uint8_t*)strdup(kernel_cmdline),
1813: strlen(kernel_cmdline) + 1);
1.1.1.8 root 1814: } else {
1815: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1816: }
1817: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1818: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1819: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1820: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.7 root 1821: }
1822:
1823: /* SPARCstation 2 hardware initialisation */
1.1.1.8 root 1824: static void ss2_init(ram_addr_t RAM_size,
1.1.1.7 root 1825: const char *boot_device,
1826: const char *kernel_filename, const char *kernel_cmdline,
1827: const char *initrd_filename, const char *cpu_model)
1828: {
1829: sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1830: kernel_cmdline, initrd_filename, cpu_model);
1831: }
1832:
1.1.1.8 root 1833: static QEMUMachine ss2_machine = {
1.1.1.7 root 1834: .name = "SS-2",
1835: .desc = "Sun4c platform, SPARCstation 2",
1836: .init = ss2_init,
1837: .use_scsi = 1,
1.1 root 1838: };
1.1.1.8 root 1839:
1.1.1.15! root 1840: static void sun4m_register_types(void)
! 1841: {
! 1842: type_register_static(&idreg_info);
! 1843: type_register_static(&afx_info);
! 1844: type_register_static(&prom_info);
! 1845: type_register_static(&ram_info);
! 1846: }
! 1847:
1.1.1.8 root 1848: static void ss2_machine_init(void)
1849: {
1850: qemu_register_machine(&ss5_machine);
1851: qemu_register_machine(&ss10_machine);
1852: qemu_register_machine(&ss600mp_machine);
1853: qemu_register_machine(&ss20_machine);
1854: qemu_register_machine(&voyager_machine);
1855: qemu_register_machine(&ss_lx_machine);
1856: qemu_register_machine(&ss4_machine);
1857: qemu_register_machine(&scls_machine);
1858: qemu_register_machine(&sbook_machine);
1859: qemu_register_machine(&ss1000_machine);
1860: qemu_register_machine(&ss2000_machine);
1861: qemu_register_machine(&ss2_machine);
1862: }
1863:
1.1.1.15! root 1864: type_init(sun4m_register_types)
1.1.1.8 root 1865: machine_init(ss2_machine_init);
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.