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1.1 root 1: /*
2: * QEMU Sun4m System Emulator
3: *
4: * Copyright (c) 2003-2005 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24: #include "vl.h"
25:
26: #define KERNEL_LOAD_ADDR 0x00004000
27: #define CMDLINE_ADDR 0x007ff000
28: #define INITRD_LOAD_ADDR 0x00800000
1.1.1.3 root 29: #define PROM_SIZE_MAX (256 * 1024)
1.1 root 30: #define PROM_ADDR 0xffd00000
1.1.1.4 ! root 31: #define PROM_FILENAME "openbios-sparc32"
1.1 root 32: #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */
33: #define PHYS_JJ_IDPROM_OFF 0x1FD8
34: #define PHYS_JJ_EEPROM_SIZE 0x2000
35: // IRQs are not PIL ones, but master interrupt controller register
36: // bits
37: #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */
38: #define PHYS_JJ_TCX_FB 0x50000000 /* TCX frame buffer */
39: #define PHYS_JJ_SLAVIO 0x70000000 /* Slavio base */
40: #define PHYS_JJ_ESPDMA 0x78400000 /* ESP DMA controller */
41: #define PHYS_JJ_ESP 0x78800000 /* ESP SCSI */
42: #define PHYS_JJ_ESP_IRQ 18
43: #define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */
44: #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */
45: #define PHYS_JJ_LE_IRQ 16
46: #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */
47: #define PHYS_JJ_CLOCK_IRQ 7
48: #define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */
49: #define PHYS_JJ_CLOCK1_IRQ 19
50: #define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */
51: #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */
52: #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */
53: #define PHYS_JJ_MS_KBD_IRQ 14
54: #define PHYS_JJ_SER 0x71100000 /* Serial */
55: #define PHYS_JJ_SER_IRQ 15
56: #define PHYS_JJ_FDC 0x71400000 /* Floppy */
57: #define PHYS_JJ_FLOPPY_IRQ 22
58: #define PHYS_JJ_ME_IRQ 30 /* Module error, power fail */
1.1.1.2 root 59: #define MAX_CPUS 16
1.1 root 60:
61: /* TSC handling */
62:
63: uint64_t cpu_get_tsc()
64: {
65: return qemu_get_clock(vm_clock);
66: }
67:
68: int DMA_get_channel_mode (int nchan)
69: {
70: return 0;
71: }
72: int DMA_read_memory (int nchan, void *buf, int pos, int size)
73: {
74: return 0;
75: }
76: int DMA_write_memory (int nchan, void *buf, int pos, int size)
77: {
78: return 0;
79: }
80: void DMA_hold_DREQ (int nchan) {}
81: void DMA_release_DREQ (int nchan) {}
82: void DMA_schedule(int nchan) {}
83: void DMA_run (void) {}
84: void DMA_init (int high_page_enable) {}
85: void DMA_register_channel (int nchan,
86: DMA_transfer_handler transfer_handler,
87: void *opaque)
88: {
89: }
90:
1.1.1.2 root 91: static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
1.1 root 92: {
1.1.1.2 root 93: m48t59_write(nvram, addr++, (value >> 8) & 0xff);
94: m48t59_write(nvram, addr++, value & 0xff);
1.1 root 95: }
96:
1.1.1.2 root 97: static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
1.1 root 98: {
1.1.1.2 root 99: m48t59_write(nvram, addr++, value >> 24);
100: m48t59_write(nvram, addr++, (value >> 16) & 0xff);
101: m48t59_write(nvram, addr++, (value >> 8) & 0xff);
102: m48t59_write(nvram, addr++, value & 0xff);
1.1 root 103: }
104:
1.1.1.2 root 105: static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
1.1 root 106: const unsigned char *str, uint32_t max)
107: {
108: unsigned int i;
109:
110: for (i = 0; i < max && str[i] != '\0'; i++) {
1.1.1.2 root 111: m48t59_write(nvram, addr + i, str[i]);
1.1 root 112: }
1.1.1.2 root 113: m48t59_write(nvram, addr + max - 1, '\0');
1.1 root 114: }
115:
1.1.1.2 root 116: static m48t59_t *nvram;
1.1 root 117:
118: extern int nographic;
119:
1.1.1.2 root 120: static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
1.1 root 121: int boot_device, uint32_t RAM_size,
122: uint32_t kernel_size,
123: int width, int height, int depth)
124: {
125: unsigned char tmp = 0;
126: int i, j;
127:
128: // Try to match PPC NVRAM
129: nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
130: nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
131: // NVRAM_size, arch not applicable
1.1.1.2 root 132: m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
133: m48t59_write(nvram, 0x2E, 0);
134: m48t59_write(nvram, 0x2F, nographic & 0xff);
1.1 root 135: nvram_set_lword(nvram, 0x30, RAM_size);
1.1.1.2 root 136: m48t59_write(nvram, 0x34, boot_device & 0xff);
1.1 root 137: nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
138: nvram_set_lword(nvram, 0x3C, kernel_size);
139: if (cmdline) {
140: strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
141: nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
142: nvram_set_lword(nvram, 0x44, strlen(cmdline));
143: }
144: // initrd_image, initrd_size passed differently
145: nvram_set_word(nvram, 0x54, width);
146: nvram_set_word(nvram, 0x56, height);
147: nvram_set_word(nvram, 0x58, depth);
148:
149: // Sun4m specific use
150: i = 0x1fd8;
1.1.1.2 root 151: m48t59_write(nvram, i++, 0x01);
152: m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */
1.1 root 153: j = 0;
1.1.1.2 root 154: m48t59_write(nvram, i++, macaddr[j++]);
155: m48t59_write(nvram, i++, macaddr[j++]);
156: m48t59_write(nvram, i++, macaddr[j++]);
157: m48t59_write(nvram, i++, macaddr[j++]);
158: m48t59_write(nvram, i++, macaddr[j++]);
159: m48t59_write(nvram, i, macaddr[j]);
1.1 root 160:
161: /* Calculate checksum */
162: for (i = 0x1fd8; i < 0x1fe7; i++) {
1.1.1.2 root 163: tmp ^= m48t59_read(nvram, i);
1.1 root 164: }
1.1.1.2 root 165: m48t59_write(nvram, 0x1fe7, tmp);
1.1 root 166: }
167:
168: static void *slavio_intctl;
169:
170: void pic_info()
171: {
172: slavio_pic_info(slavio_intctl);
173: }
174:
175: void irq_info()
176: {
177: slavio_irq_info(slavio_intctl);
178: }
179:
180: void pic_set_irq(int irq, int level)
181: {
182: slavio_pic_set_irq(slavio_intctl, irq, level);
183: }
184:
1.1.1.4 ! root 185: void pic_set_irq_new(void *opaque, int irq, int level)
! 186: {
! 187: pic_set_irq(irq, level);
! 188: }
! 189:
1.1.1.2 root 190: void pic_set_irq_cpu(int irq, int level, unsigned int cpu)
191: {
192: slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu);
193: }
194:
1.1 root 195: static void *iommu;
196:
197: uint32_t iommu_translate(uint32_t addr)
198: {
199: return iommu_translate_local(iommu, addr);
200: }
201:
202: static void *slavio_misc;
203:
204: void qemu_system_powerdown(void)
205: {
206: slavio_set_power_fail(slavio_misc, 1);
207: }
208:
1.1.1.2 root 209: static void main_cpu_reset(void *opaque)
210: {
211: CPUState *env = opaque;
212: cpu_reset(env);
213: }
214:
1.1 root 215: /* Sun4m hardware initialisation */
216: static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
217: DisplayState *ds, const char **fd_filename, int snapshot,
218: const char *kernel_filename, const char *kernel_cmdline,
219: const char *initrd_filename)
220: {
1.1.1.2 root 221: CPUState *env, *envs[MAX_CPUS];
1.1 root 222: char buf[1024];
223: int ret, linux_boot;
224: unsigned int i;
225: long vram_size = 0x100000, prom_offset, initrd_size, kernel_size;
226:
227: linux_boot = (kernel_filename != NULL);
228:
1.1.1.2 root 229: /* init CPUs */
230: for(i = 0; i < smp_cpus; i++) {
231: env = cpu_init();
232: envs[i] = env;
233: if (i != 0)
234: env->halted = 1;
235: register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
236: qemu_register_reset(main_cpu_reset, env);
237: }
1.1 root 238: /* allocate RAM */
239: cpu_register_physical_memory(0, ram_size, 0);
240:
241: iommu = iommu_init(PHYS_JJ_IOMMU);
242: slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
1.1.1.2 root 243: for(i = 0; i < smp_cpus; i++) {
244: slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
245: }
246:
1.1.1.3 root 247: tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
248: if (nd_table[0].vlan) {
249: if (nd_table[0].model == NULL
250: || strcmp(nd_table[0].model, "lance") == 0) {
251: lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
252: } else {
253: fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
254: exit (1);
255: }
256: }
1.1.1.2 root 257: nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
258: for (i = 0; i < MAX_CPUS; i++) {
259: slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i);
260: }
261: slavio_timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ, 2, (unsigned int)-1);
1.1 root 262: slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
263: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
264: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
265: slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]);
266: fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
267: esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA);
268: slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ);
269:
270: prom_offset = ram_size + vram_size;
1.1.1.3 root 271: cpu_register_physical_memory(PROM_ADDR,
272: (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK,
273: prom_offset | IO_MEM_ROM);
1.1 root 274:
1.1.1.4 ! root 275: snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
1.1.1.3 root 276: ret = load_elf(buf, 0, NULL);
1.1 root 277: if (ret < 0) {
278: fprintf(stderr, "qemu: could not load prom '%s'\n",
279: buf);
280: exit(1);
281: }
282:
283: kernel_size = 0;
284: if (linux_boot) {
1.1.1.3 root 285: kernel_size = load_elf(kernel_filename, -0xf0000000, NULL);
1.1 root 286: if (kernel_size < 0)
287: kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
288: if (kernel_size < 0)
289: kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
290: if (kernel_size < 0) {
291: fprintf(stderr, "qemu: could not load kernel '%s'\n",
292: kernel_filename);
293: exit(1);
294: }
295:
296: /* load initrd */
297: initrd_size = 0;
298: if (initrd_filename) {
299: initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
300: if (initrd_size < 0) {
301: fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
302: initrd_filename);
303: exit(1);
304: }
305: }
306: if (initrd_size > 0) {
307: for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
308: if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
309: == 0x48647253) { // HdrS
310: stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
311: stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
312: break;
313: }
314: }
315: }
316: }
317: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
318: }
319:
320: QEMUMachine sun4m_machine = {
321: "sun4m",
322: "Sun4m platform",
323: sun4m_init,
324: };
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