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1.1 root 1: /*
1.1.1.6 root 2: * QEMU Sun4m & Sun4d & Sun4c System Emulator
3: *
1.1 root 4: * Copyright (c) 2003-2005 Fabrice Bellard
1.1.1.6 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.8 ! root 24: #include "sysbus.h"
1.1.1.6 root 25: #include "qemu-timer.h"
26: #include "sun4m.h"
27: #include "nvram.h"
28: #include "sparc32_dma.h"
29: #include "fdc.h"
30: #include "sysemu.h"
31: #include "net.h"
32: #include "boards.h"
33: #include "firmware_abi.h"
1.1.1.7 root 34: #include "scsi.h"
35: #include "pc.h"
36: #include "isa.h"
37: #include "fw_cfg.h"
38: #include "escc.h"
1.1.1.6 root 39:
40: //#define DEBUG_IRQ
41:
42: /*
43: * Sun4m architecture was used in the following machines:
44: *
45: * SPARCserver 6xxMP/xx
1.1.1.7 root 46: * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47: * SPARCclassic X (4/10)
1.1.1.6 root 48: * SPARCstation LX/ZX (4/30)
49: * SPARCstation Voyager
50: * SPARCstation 10/xx, SPARCserver 10/xx
51: * SPARCstation 5, SPARCserver 5
52: * SPARCstation 20/xx, SPARCserver 20
53: * SPARCstation 4
54: *
55: * Sun4d architecture was used in the following machines:
56: *
57: * SPARCcenter 2000
58: * SPARCserver 1000
59: *
60: * Sun4c architecture was used in the following machines:
61: * SPARCstation 1/1+, SPARCserver 1/1+
62: * SPARCstation SLC
63: * SPARCstation IPC
64: * SPARCstation ELC
65: * SPARCstation IPX
66: *
67: * See for example: http://www.sunhelp.org/faq/sunref1.html
68: */
69:
70: #ifdef DEBUG_IRQ
1.1.1.8 ! root 71: #define DPRINTF(fmt, ...) \
! 72: do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
1.1.1.6 root 73: #else
1.1.1.8 ! root 74: #define DPRINTF(fmt, ...)
1.1.1.6 root 75: #endif
1.1 root 76:
77: #define KERNEL_LOAD_ADDR 0x00004000
78: #define CMDLINE_ADDR 0x007ff000
79: #define INITRD_LOAD_ADDR 0x00800000
1.1.1.7 root 80: #define PROM_SIZE_MAX (1024 * 1024)
1.1.1.6 root 81: #define PROM_VADDR 0xffd00000
82: #define PROM_FILENAME "openbios-sparc32"
1.1.1.7 root 83: #define CFG_ADDR 0xd00000510ULL
84: #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85:
1.1.1.2 root 86: #define MAX_CPUS 16
1.1.1.6 root 87: #define MAX_PILS 16
88:
1.1.1.7 root 89: #define ESCC_CLOCK 4915200
90:
91: struct sun4m_hwdef {
1.1.1.6 root 92: target_phys_addr_t iommu_base, slavio_base;
93: target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94: target_phys_addr_t serial_base, fd_base;
95: target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
1.1.1.7 root 96: target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
1.1.1.6 root 97: target_phys_addr_t ecc_base;
98: uint32_t ecc_version;
99: long vram_size, nvram_size;
100: // IRQ numbers are not PIL ones, but master interrupt controller
101: // register bit numbers
1.1.1.7 root 102: int esp_irq, le_irq, clock_irq, clock1_irq;
103: int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104: uint8_t nvram_machine_id;
105: uint16_t machine_id;
1.1.1.6 root 106: uint32_t iommu_version;
107: uint32_t intbit_to_level[32];
108: uint64_t max_mem;
109: const char * const default_cpu_model;
110: };
111:
112: #define MAX_IOUNITS 5
113:
114: struct sun4d_hwdef {
115: target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116: target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117: target_phys_addr_t serial_base;
118: target_phys_addr_t espdma_base, esp_base;
119: target_phys_addr_t ledma_base, le_base;
120: target_phys_addr_t tcx_base;
121: target_phys_addr_t sbi_base;
122: unsigned long vram_size, nvram_size;
123: // IRQ numbers are not PIL ones, but SBI register bit numbers
124: int esp_irq, le_irq, clock_irq, clock1_irq;
125: int ser_irq, ms_kb_irq, me_irq;
1.1.1.7 root 126: uint8_t nvram_machine_id;
127: uint16_t machine_id;
1.1.1.6 root 128: uint32_t iounit_version;
129: uint64_t max_mem;
130: const char * const default_cpu_model;
131: };
1.1 root 132:
1.1.1.7 root 133: struct sun4c_hwdef {
134: target_phys_addr_t iommu_base, slavio_base;
135: target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136: target_phys_addr_t serial_base, fd_base;
137: target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138: target_phys_addr_t tcx_base, aux1_base;
139: long vram_size, nvram_size;
140: // IRQ numbers are not PIL ones, but master interrupt controller
141: // register bit numbers
142: int esp_irq, le_irq, clock_irq, clock1_irq;
143: int ser_irq, ms_kb_irq, fd_irq, me_irq;
144: uint8_t nvram_machine_id;
145: uint16_t machine_id;
146: uint32_t iommu_version;
147: uint32_t intbit_to_level[32];
148: uint64_t max_mem;
149: const char * const default_cpu_model;
150: };
1.1 root 151:
152: int DMA_get_channel_mode (int nchan)
153: {
154: return 0;
155: }
156: int DMA_read_memory (int nchan, void *buf, int pos, int size)
157: {
158: return 0;
159: }
160: int DMA_write_memory (int nchan, void *buf, int pos, int size)
161: {
162: return 0;
163: }
164: void DMA_hold_DREQ (int nchan) {}
165: void DMA_release_DREQ (int nchan) {}
166: void DMA_schedule(int nchan) {}
167: void DMA_init (int high_page_enable) {}
168: void DMA_register_channel (int nchan,
169: DMA_transfer_handler transfer_handler,
170: void *opaque)
171: {
172: }
173:
1.1.1.8 ! root 174: static int fw_cfg_boot_set(void *opaque, const char *boot_device)
1.1.1.7 root 175: {
1.1.1.8 ! root 176: fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
1.1.1.7 root 177: return 0;
178: }
1.1 root 179:
1.1.1.2 root 180: static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
1.1.1.7 root 181: const char *boot_devices, ram_addr_t RAM_size,
1.1.1.6 root 182: uint32_t kernel_size,
183: int width, int height, int depth,
1.1.1.7 root 184: int nvram_machine_id, const char *arch)
1.1 root 185: {
1.1.1.6 root 186: unsigned int i;
187: uint32_t start, end;
188: uint8_t image[0x1ff0];
189: struct OpenBIOS_nvpart_v1 *part_header;
190:
191: memset(image, '\0', sizeof(image));
1.1 root 192:
1.1.1.8 ! root 193: start = 0;
1.1.1.6 root 194:
195: // OpenBIOS nvram variables
196: // Variable partition
197: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
198: part_header->signature = OPENBIOS_PART_SYSTEM;
1.1.1.7 root 199: pstrcpy(part_header->name, sizeof(part_header->name), "system");
1.1.1.6 root 200:
201: end = start + sizeof(struct OpenBIOS_nvpart_v1);
202: for (i = 0; i < nb_prom_envs; i++)
203: end = OpenBIOS_set_var(image, end, prom_envs[i]);
204:
205: // End marker
206: image[end++] = '\0';
207:
208: end = start + ((end - start + 15) & ~15);
209: OpenBIOS_finish_partition(part_header, end - start);
210:
211: // free partition
212: start = end;
213: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
214: part_header->signature = OPENBIOS_PART_FREE;
1.1.1.7 root 215: pstrcpy(part_header->name, sizeof(part_header->name), "free");
1.1.1.6 root 216:
217: end = 0x1fd0;
218: OpenBIOS_finish_partition(part_header, end - start);
219:
1.1.1.7 root 220: Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
221: nvram_machine_id);
1.1.1.6 root 222:
223: for (i = 0; i < sizeof(image); i++)
224: m48t59_write(nvram, i, image[i]);
1.1 root 225: }
226:
227: static void *slavio_intctl;
228:
1.1.1.8 ! root 229: void pic_info(Monitor *mon)
1.1 root 230: {
1.1.1.6 root 231: if (slavio_intctl)
1.1.1.8 ! root 232: slavio_pic_info(mon, slavio_intctl);
1.1 root 233: }
234:
1.1.1.8 ! root 235: void irq_info(Monitor *mon)
1.1 root 236: {
1.1.1.6 root 237: if (slavio_intctl)
1.1.1.8 ! root 238: slavio_irq_info(mon, slavio_intctl);
1.1 root 239: }
240:
1.1.1.6 root 241: void cpu_check_irqs(CPUState *env)
1.1 root 242: {
1.1.1.6 root 243: if (env->pil_in && (env->interrupt_index == 0 ||
244: (env->interrupt_index & ~15) == TT_EXTINT)) {
245: unsigned int i;
246:
247: for (i = 15; i > 0; i--) {
248: if (env->pil_in & (1 << i)) {
249: int old_interrupt = env->interrupt_index;
250:
251: env->interrupt_index = TT_EXTINT | i;
1.1.1.7 root 252: if (old_interrupt != env->interrupt_index) {
253: DPRINTF("Set CPU IRQ %d\n", i);
1.1.1.6 root 254: cpu_interrupt(env, CPU_INTERRUPT_HARD);
1.1.1.7 root 255: }
1.1.1.6 root 256: break;
257: }
258: }
259: } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
1.1.1.7 root 260: DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
1.1.1.6 root 261: env->interrupt_index = 0;
262: cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
263: }
1.1 root 264: }
265:
1.1.1.6 root 266: static void cpu_set_irq(void *opaque, int irq, int level)
1.1.1.4 root 267: {
1.1.1.6 root 268: CPUState *env = opaque;
269:
270: if (level) {
271: DPRINTF("Raise CPU IRQ %d\n", irq);
272: env->halted = 0;
273: env->pil_in |= 1 << irq;
274: cpu_check_irqs(env);
275: } else {
276: DPRINTF("Lower CPU IRQ %d\n", irq);
277: env->pil_in &= ~(1 << irq);
278: cpu_check_irqs(env);
279: }
1.1.1.4 root 280: }
281:
1.1.1.6 root 282: static void dummy_cpu_set_irq(void *opaque, int irq, int level)
1.1.1.2 root 283: {
284: }
285:
1.1 root 286: static void *slavio_misc;
287:
288: void qemu_system_powerdown(void)
289: {
290: slavio_set_power_fail(slavio_misc, 1);
291: }
292:
1.1.1.2 root 293: static void main_cpu_reset(void *opaque)
294: {
295: CPUState *env = opaque;
1.1.1.6 root 296:
1.1.1.2 root 297: cpu_reset(env);
1.1.1.6 root 298: env->halted = 0;
1.1.1.2 root 299: }
300:
1.1.1.6 root 301: static void secondary_cpu_reset(void *opaque)
1.1 root 302: {
1.1.1.6 root 303: CPUState *env = opaque;
304:
305: cpu_reset(env);
306: env->halted = 1;
307: }
308:
1.1.1.7 root 309: static void cpu_halt_signal(void *opaque, int irq, int level)
310: {
311: if (level && cpu_single_env)
312: cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
313: }
314:
1.1.1.6 root 315: static unsigned long sun4m_load_kernel(const char *kernel_filename,
1.1.1.7 root 316: const char *initrd_filename,
317: ram_addr_t RAM_size)
1.1.1.6 root 318: {
319: int linux_boot;
1.1 root 320: unsigned int i;
1.1.1.6 root 321: long initrd_size, kernel_size;
1.1 root 322:
323: linux_boot = (kernel_filename != NULL);
324:
1.1.1.6 root 325: kernel_size = 0;
326: if (linux_boot) {
327: kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
328: NULL);
329: if (kernel_size < 0)
1.1.1.7 root 330: kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
331: RAM_size - KERNEL_LOAD_ADDR);
1.1.1.6 root 332: if (kernel_size < 0)
1.1.1.7 root 333: kernel_size = load_image_targphys(kernel_filename,
334: KERNEL_LOAD_ADDR,
335: RAM_size - KERNEL_LOAD_ADDR);
1.1.1.6 root 336: if (kernel_size < 0) {
337: fprintf(stderr, "qemu: could not load kernel '%s'\n",
338: kernel_filename);
339: exit(1);
340: }
341:
342: /* load initrd */
343: initrd_size = 0;
344: if (initrd_filename) {
1.1.1.7 root 345: initrd_size = load_image_targphys(initrd_filename,
346: INITRD_LOAD_ADDR,
347: RAM_size - INITRD_LOAD_ADDR);
1.1.1.6 root 348: if (initrd_size < 0) {
349: fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
350: initrd_filename);
351: exit(1);
352: }
353: }
354: if (initrd_size > 0) {
355: for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
1.1.1.7 root 356: if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
357: stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
358: stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
1.1.1.6 root 359: break;
360: }
361: }
362: }
363: }
364: return kernel_size;
365: }
366:
1.1.1.8 ! root 367: static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
! 368: void *dma_opaque, qemu_irq irq, qemu_irq *reset)
! 369: {
! 370: DeviceState *dev;
! 371: SysBusDevice *s;
! 372:
! 373: qemu_check_nic_model(&nd_table[0], "lance");
! 374:
! 375: dev = qdev_create(NULL, "lance");
! 376: dev->nd = nd;
! 377: qdev_init(dev);
! 378: s = sysbus_from_qdev(dev);
! 379: sysbus_mmio_map(s, 0, leaddr);
! 380: sysbus_connect_irq(s, 0, irq);
! 381: *reset = qdev_get_gpio_in(dev, 0);
! 382: }
! 383:
! 384: /* NCR89C100/MACIO Internal ID register */
! 385: static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
! 386:
! 387: static void idreg_init(target_phys_addr_t addr)
! 388: {
! 389: DeviceState *dev;
! 390: SysBusDevice *s;
! 391:
! 392: dev = qdev_create(NULL, "macio_idreg");
! 393: qdev_init(dev);
! 394: s = sysbus_from_qdev(dev);
! 395:
! 396: sysbus_mmio_map(s, 0, addr);
! 397: cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
! 398: }
! 399:
! 400: static void idreg_init1(SysBusDevice *dev)
! 401: {
! 402: ram_addr_t idreg_offset;
! 403:
! 404: idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
! 405: sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
! 406: }
! 407:
! 408: static SysBusDeviceInfo idreg_info = {
! 409: .init = idreg_init1,
! 410: .qdev.name = "macio_idreg",
! 411: .qdev.size = sizeof(SysBusDevice),
! 412: };
! 413:
! 414: static void idreg_register_devices(void)
! 415: {
! 416: sysbus_register_withprop(&idreg_info);
! 417: }
! 418:
! 419: device_init(idreg_register_devices);
! 420:
! 421: /* Boot PROM (OpenBIOS) */
! 422: static void prom_init(target_phys_addr_t addr, const char *bios_name)
! 423: {
! 424: DeviceState *dev;
! 425: SysBusDevice *s;
! 426: char *filename;
! 427: int ret;
! 428:
! 429: dev = qdev_create(NULL, "openprom");
! 430: qdev_init(dev);
! 431: s = sysbus_from_qdev(dev);
! 432:
! 433: sysbus_mmio_map(s, 0, addr);
! 434:
! 435: /* load boot prom */
! 436: if (bios_name == NULL) {
! 437: bios_name = PROM_FILENAME;
! 438: }
! 439: filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
! 440: if (filename) {
! 441: ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL);
! 442: if (ret < 0 || ret > PROM_SIZE_MAX) {
! 443: ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
! 444: }
! 445: qemu_free(filename);
! 446: } else {
! 447: ret = -1;
! 448: }
! 449: if (ret < 0 || ret > PROM_SIZE_MAX) {
! 450: fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
! 451: exit(1);
! 452: }
! 453: }
! 454:
! 455: static void prom_init1(SysBusDevice *dev)
! 456: {
! 457: ram_addr_t prom_offset;
! 458:
! 459: prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
! 460: sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
! 461: }
! 462:
! 463: static SysBusDeviceInfo prom_info = {
! 464: .init = prom_init1,
! 465: .qdev.name = "openprom",
! 466: .qdev.size = sizeof(SysBusDevice),
! 467: .qdev.props = (Property[]) {
! 468: {/* end of property list */}
! 469: }
! 470: };
! 471:
! 472: static void prom_register_devices(void)
! 473: {
! 474: sysbus_register_withprop(&prom_info);
! 475: }
! 476:
! 477: device_init(prom_register_devices);
! 478:
! 479: typedef struct RamDevice
! 480: {
! 481: SysBusDevice busdev;
! 482: uint32_t size;
! 483: } RamDevice;
! 484:
! 485: /* System RAM */
! 486: static void ram_init1(SysBusDevice *dev)
! 487: {
! 488: ram_addr_t RAM_size, ram_offset;
! 489: RamDevice *d = FROM_SYSBUS(RamDevice, dev);
! 490:
! 491: RAM_size = d->size;
! 492:
! 493: ram_offset = qemu_ram_alloc(RAM_size);
! 494: sysbus_init_mmio(dev, RAM_size, ram_offset);
! 495: }
! 496:
! 497: static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
! 498: uint64_t max_mem)
! 499: {
! 500: DeviceState *dev;
! 501: SysBusDevice *s;
! 502: RamDevice *d;
! 503:
! 504: /* allocate RAM */
! 505: if ((uint64_t)RAM_size > max_mem) {
! 506: fprintf(stderr,
! 507: "qemu: Too much memory for this machine: %d, maximum %d\n",
! 508: (unsigned int)(RAM_size / (1024 * 1024)),
! 509: (unsigned int)(max_mem / (1024 * 1024)));
! 510: exit(1);
! 511: }
! 512: dev = qdev_create(NULL, "memory");
! 513: s = sysbus_from_qdev(dev);
! 514:
! 515: d = FROM_SYSBUS(RamDevice, s);
! 516: d->size = RAM_size;
! 517: qdev_init(dev);
! 518:
! 519: sysbus_mmio_map(s, 0, addr);
! 520: }
! 521:
! 522: static SysBusDeviceInfo ram_info = {
! 523: .init = ram_init1,
! 524: .qdev.name = "memory",
! 525: .qdev.size = sizeof(RamDevice),
! 526: .qdev.props = (Property[]) {
! 527: {
! 528: .name = "size",
! 529: .info = &qdev_prop_uint32,
! 530: .offset = offsetof(RamDevice, size),
! 531: },
! 532: {/* end of property list */}
! 533: }
! 534: };
! 535:
! 536: static void ram_register_devices(void)
! 537: {
! 538: sysbus_register_withprop(&ram_info);
! 539: }
! 540:
! 541: device_init(ram_register_devices);
! 542:
! 543: static CPUState *cpu_devinit(const char *cpu_model, unsigned int id,
! 544: uint64_t prom_addr, qemu_irq **cpu_irqs)
! 545: {
! 546: CPUState *env;
! 547:
! 548: env = cpu_init(cpu_model);
! 549: if (!env) {
! 550: fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
! 551: exit(1);
! 552: }
! 553:
! 554: cpu_sparc_set_id(env, id);
! 555: if (id == 0) {
! 556: qemu_register_reset(main_cpu_reset, env);
! 557: } else {
! 558: qemu_register_reset(secondary_cpu_reset, env);
! 559: env->halted = 1;
! 560: }
! 561: *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
! 562: env->prom_addr = prom_addr;
! 563:
! 564: return env;
! 565: }
! 566:
1.1.1.7 root 567: static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
1.1.1.6 root 568: const char *boot_device,
1.1.1.7 root 569: const char *kernel_filename,
1.1.1.6 root 570: const char *kernel_cmdline,
571: const char *initrd_filename, const char *cpu_model)
572: {
1.1.1.8 ! root 573: CPUState *envs[MAX_CPUS];
1.1.1.6 root 574: unsigned int i;
1.1.1.8 ! root 575: void *iommu, *espdma, *ledma, *nvram;
! 576: qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
! 577: espdma_irq, ledma_irq;
1.1.1.6 root 578: qemu_irq *esp_reset, *le_reset;
1.1.1.8 ! root 579: qemu_irq fdc_tc;
1.1.1.7 root 580: qemu_irq *cpu_halt;
581: unsigned long kernel_size;
1.1.1.6 root 582: BlockDriverState *fd[MAX_FD];
1.1.1.7 root 583: int drive_index;
584: void *fw_cfg;
1.1.1.8 ! root 585: DeviceState *dev;
1.1.1.6 root 586:
1.1.1.2 root 587: /* init CPUs */
1.1.1.6 root 588: if (!cpu_model)
589: cpu_model = hwdef->default_cpu_model;
590:
1.1.1.2 root 591: for(i = 0; i < smp_cpus; i++) {
1.1.1.8 ! root 592: envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1.1.1.2 root 593: }
1.1.1.6 root 594:
595: for (i = smp_cpus; i < MAX_CPUS; i++)
596: cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
597:
598:
1.1.1.8 ! root 599: /* set up devices */
! 600: ram_init(0, RAM_size, hwdef->max_mem);
1.1 root 601:
1.1.1.8 ! root 602: prom_init(hwdef->slavio_base, bios_name);
1.1.1.6 root 603:
1.1.1.8 ! root 604: dev = slavio_intctl_init(hwdef->intctl_base,
! 605: hwdef->intctl_base + 0x10000ULL,
! 606: &hwdef->intbit_to_level[0],
! 607: cpu_irqs,
! 608: hwdef->clock_irq);
1.1.1.2 root 609:
1.1.1.8 ! root 610: for (i = 0; i < 32; i++) {
! 611: slavio_irq[i] = qdev_get_gpio_in(dev, i);
! 612: }
! 613: for (i = 0; i < MAX_CPUS; i++) {
! 614: slavio_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
! 615: }
1.1.1.6 root 616:
1.1.1.7 root 617: if (hwdef->idreg_base) {
1.1.1.8 ! root 618: idreg_init(hwdef->idreg_base);
1.1.1.3 root 619: }
1.1.1.6 root 620:
621: iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
622: slavio_irq[hwdef->me_irq]);
623:
624: espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
625: iommu, &espdma_irq, &esp_reset);
626:
627: ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
628: slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
629: &le_reset);
630:
631: if (graphic_depth != 8 && graphic_depth != 24) {
632: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
633: exit (1);
634: }
1.1.1.8 ! root 635: tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
! 636: graphic_depth);
1.1.1.6 root 637:
1.1.1.8 ! root 638: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1.1.1.6 root 639:
640: nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
641: hwdef->nvram_size, 8);
642:
643: slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
644: slavio_cpu_irq, smp_cpus);
645:
646: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1.1.1.8 ! root 647: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1 root 648: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
649: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1.1.1.7 root 650: escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
651: serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1.1.1.6 root 652:
1.1.1.7 root 653: cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
1.1.1.8 ! root 654: slavio_misc = slavio_misc_init(hwdef->slavio_base,
1.1.1.7 root 655: hwdef->aux1_base, hwdef->aux2_base,
1.1.1.8 ! root 656: slavio_irq[hwdef->me_irq], fdc_tc);
! 657: if (hwdef->apc_base) {
! 658: apc_init(hwdef->apc_base, cpu_halt[0]);
! 659: }
1.1.1.7 root 660:
661: if (hwdef->fd_base) {
1.1.1.6 root 662: /* there is zero or one floppy drive */
1.1.1.7 root 663: memset(fd, 0, sizeof(fd));
664: drive_index = drive_get_index(IF_FLOPPY, 0, 0);
665: if (drive_index != -1)
666: fd[0] = drives_table[drive_index].bdrv;
1.1.1.6 root 667:
1.1.1.7 root 668: sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1.1.1.8 ! root 669: &fdc_tc);
1.1.1.6 root 670: }
671:
672: if (drive_get_max_bus(IF_SCSI) > 0) {
673: fprintf(stderr, "qemu: too many SCSI bus\n");
674: exit(1);
675: }
676:
1.1.1.8 ! root 677: esp_init(hwdef->esp_base, 2,
! 678: espdma_memory_read, espdma_memory_write,
! 679: espdma, espdma_irq, esp_reset);
! 680:
! 681: if (hwdef->cs_base) {
! 682: sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
! 683: slavio_irq[hwdef->cs_irq]);
1.1.1.6 root 684: }
685:
1.1.1.7 root 686: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
687: RAM_size);
1.1.1.6 root 688:
689: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
690: boot_device, RAM_size, kernel_size, graphic_width,
1.1.1.7 root 691: graphic_height, graphic_depth, hwdef->nvram_machine_id,
692: "Sun4m");
1.1.1.6 root 693:
1.1.1.7 root 694: if (hwdef->ecc_base)
695: ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
696: hwdef->ecc_version);
697:
698: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
699: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
700: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
701: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
702: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1.1.1.8 ! root 703: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
! 704: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
! 705: if (kernel_cmdline) {
! 706: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
! 707: pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
! 708: } else {
! 709: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
! 710: }
! 711: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
! 712: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
! 713: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
! 714: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.7 root 715: }
716:
717: enum {
718: ss2_id = 0,
719: ss5_id = 32,
720: vger_id,
721: lx_id,
722: ss4_id,
723: scls_id,
724: sbook_id,
725: ss10_id = 64,
726: ss20_id,
727: ss600mp_id,
728: ss1000_id = 96,
729: ss2000_id,
730: };
1.1.1.6 root 731:
1.1.1.7 root 732: static const struct sun4m_hwdef sun4m_hwdefs[] = {
1.1.1.6 root 733: /* SS-5 */
734: {
735: .iommu_base = 0x10000000,
736: .tcx_base = 0x50000000,
737: .cs_base = 0x6c000000,
738: .slavio_base = 0x70000000,
739: .ms_kb_base = 0x71000000,
740: .serial_base = 0x71100000,
741: .nvram_base = 0x71200000,
742: .fd_base = 0x71400000,
743: .counter_base = 0x71d00000,
744: .intctl_base = 0x71e00000,
745: .idreg_base = 0x78000000,
746: .dma_base = 0x78400000,
747: .esp_base = 0x78800000,
748: .le_base = 0x78c00000,
1.1.1.7 root 749: .apc_base = 0x6a000000,
750: .aux1_base = 0x71900000,
751: .aux2_base = 0x71910000,
1.1.1.6 root 752: .vram_size = 0x00100000,
753: .nvram_size = 0x2000,
754: .esp_irq = 18,
755: .le_irq = 16,
756: .clock_irq = 7,
757: .clock1_irq = 19,
758: .ms_kb_irq = 14,
759: .ser_irq = 15,
760: .fd_irq = 22,
761: .me_irq = 30,
762: .cs_irq = 5,
1.1.1.7 root 763: .nvram_machine_id = 0x80,
764: .machine_id = ss5_id,
1.1.1.6 root 765: .iommu_version = 0x05000000,
766: .intbit_to_level = {
767: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
768: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
769: },
770: .max_mem = 0x10000000,
771: .default_cpu_model = "Fujitsu MB86904",
772: },
773: /* SS-10 */
774: {
775: .iommu_base = 0xfe0000000ULL,
776: .tcx_base = 0xe20000000ULL,
777: .slavio_base = 0xff0000000ULL,
778: .ms_kb_base = 0xff1000000ULL,
779: .serial_base = 0xff1100000ULL,
780: .nvram_base = 0xff1200000ULL,
781: .fd_base = 0xff1700000ULL,
782: .counter_base = 0xff1300000ULL,
783: .intctl_base = 0xff1400000ULL,
784: .idreg_base = 0xef0000000ULL,
785: .dma_base = 0xef0400000ULL,
786: .esp_base = 0xef0800000ULL,
787: .le_base = 0xef0c00000ULL,
1.1.1.7 root 788: .apc_base = 0xefa000000ULL, // XXX should not exist
789: .aux1_base = 0xff1800000ULL,
790: .aux2_base = 0xff1a01000ULL,
1.1.1.6 root 791: .ecc_base = 0xf00000000ULL,
792: .ecc_version = 0x10000000, // version 0, implementation 1
793: .vram_size = 0x00100000,
794: .nvram_size = 0x2000,
795: .esp_irq = 18,
796: .le_irq = 16,
797: .clock_irq = 7,
798: .clock1_irq = 19,
799: .ms_kb_irq = 14,
800: .ser_irq = 15,
801: .fd_irq = 22,
802: .me_irq = 30,
1.1.1.7 root 803: .ecc_irq = 28,
804: .nvram_machine_id = 0x72,
805: .machine_id = ss10_id,
1.1.1.6 root 806: .iommu_version = 0x03000000,
807: .intbit_to_level = {
808: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
809: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
810: },
1.1.1.7 root 811: .max_mem = 0xf00000000ULL,
1.1.1.6 root 812: .default_cpu_model = "TI SuperSparc II",
813: },
814: /* SS-600MP */
815: {
816: .iommu_base = 0xfe0000000ULL,
817: .tcx_base = 0xe20000000ULL,
818: .slavio_base = 0xff0000000ULL,
819: .ms_kb_base = 0xff1000000ULL,
820: .serial_base = 0xff1100000ULL,
821: .nvram_base = 0xff1200000ULL,
822: .counter_base = 0xff1300000ULL,
823: .intctl_base = 0xff1400000ULL,
824: .dma_base = 0xef0081000ULL,
825: .esp_base = 0xef0080000ULL,
826: .le_base = 0xef0060000ULL,
1.1.1.7 root 827: .apc_base = 0xefa000000ULL, // XXX should not exist
828: .aux1_base = 0xff1800000ULL,
829: .aux2_base = 0xff1a01000ULL, // XXX should not exist
1.1.1.6 root 830: .ecc_base = 0xf00000000ULL,
831: .ecc_version = 0x00000000, // version 0, implementation 0
832: .vram_size = 0x00100000,
833: .nvram_size = 0x2000,
834: .esp_irq = 18,
835: .le_irq = 16,
836: .clock_irq = 7,
837: .clock1_irq = 19,
838: .ms_kb_irq = 14,
839: .ser_irq = 15,
840: .fd_irq = 22,
841: .me_irq = 30,
1.1.1.7 root 842: .ecc_irq = 28,
843: .nvram_machine_id = 0x71,
844: .machine_id = ss600mp_id,
1.1.1.6 root 845: .iommu_version = 0x01000000,
846: .intbit_to_level = {
847: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
848: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
849: },
1.1.1.7 root 850: .max_mem = 0xf00000000ULL,
1.1.1.6 root 851: .default_cpu_model = "TI SuperSparc II",
852: },
853: /* SS-20 */
854: {
855: .iommu_base = 0xfe0000000ULL,
856: .tcx_base = 0xe20000000ULL,
857: .slavio_base = 0xff0000000ULL,
858: .ms_kb_base = 0xff1000000ULL,
859: .serial_base = 0xff1100000ULL,
860: .nvram_base = 0xff1200000ULL,
861: .fd_base = 0xff1700000ULL,
862: .counter_base = 0xff1300000ULL,
863: .intctl_base = 0xff1400000ULL,
864: .idreg_base = 0xef0000000ULL,
865: .dma_base = 0xef0400000ULL,
866: .esp_base = 0xef0800000ULL,
867: .le_base = 0xef0c00000ULL,
1.1.1.7 root 868: .apc_base = 0xefa000000ULL, // XXX should not exist
869: .aux1_base = 0xff1800000ULL,
870: .aux2_base = 0xff1a01000ULL,
1.1.1.6 root 871: .ecc_base = 0xf00000000ULL,
872: .ecc_version = 0x20000000, // version 0, implementation 2
873: .vram_size = 0x00100000,
874: .nvram_size = 0x2000,
875: .esp_irq = 18,
876: .le_irq = 16,
877: .clock_irq = 7,
878: .clock1_irq = 19,
879: .ms_kb_irq = 14,
880: .ser_irq = 15,
881: .fd_irq = 22,
882: .me_irq = 30,
1.1.1.7 root 883: .ecc_irq = 28,
884: .nvram_machine_id = 0x72,
885: .machine_id = ss20_id,
1.1.1.6 root 886: .iommu_version = 0x13000000,
887: .intbit_to_level = {
888: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
889: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
890: },
1.1.1.7 root 891: .max_mem = 0xf00000000ULL,
1.1.1.6 root 892: .default_cpu_model = "TI SuperSparc II",
893: },
1.1.1.7 root 894: /* Voyager */
1.1.1.6 root 895: {
1.1.1.7 root 896: .iommu_base = 0x10000000,
897: .tcx_base = 0x50000000,
898: .slavio_base = 0x70000000,
899: .ms_kb_base = 0x71000000,
900: .serial_base = 0x71100000,
901: .nvram_base = 0x71200000,
902: .fd_base = 0x71400000,
903: .counter_base = 0x71d00000,
904: .intctl_base = 0x71e00000,
905: .idreg_base = 0x78000000,
906: .dma_base = 0x78400000,
907: .esp_base = 0x78800000,
908: .le_base = 0x78c00000,
909: .apc_base = 0x71300000, // pmc
910: .aux1_base = 0x71900000,
911: .aux2_base = 0x71910000,
1.1.1.6 root 912: .vram_size = 0x00100000,
1.1.1.7 root 913: .nvram_size = 0x2000,
914: .esp_irq = 18,
915: .le_irq = 16,
916: .clock_irq = 7,
917: .clock1_irq = 19,
918: .ms_kb_irq = 14,
919: .ser_irq = 15,
920: .fd_irq = 22,
921: .me_irq = 30,
922: .nvram_machine_id = 0x80,
923: .machine_id = vger_id,
924: .iommu_version = 0x05000000,
925: .intbit_to_level = {
926: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
927: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
928: },
1.1.1.6 root 929: .max_mem = 0x10000000,
1.1.1.7 root 930: .default_cpu_model = "Fujitsu MB86904",
931: },
932: /* LX */
933: {
934: .iommu_base = 0x10000000,
935: .tcx_base = 0x50000000,
936: .slavio_base = 0x70000000,
937: .ms_kb_base = 0x71000000,
938: .serial_base = 0x71100000,
939: .nvram_base = 0x71200000,
940: .fd_base = 0x71400000,
941: .counter_base = 0x71d00000,
942: .intctl_base = 0x71e00000,
943: .idreg_base = 0x78000000,
944: .dma_base = 0x78400000,
945: .esp_base = 0x78800000,
946: .le_base = 0x78c00000,
947: .aux1_base = 0x71900000,
948: .aux2_base = 0x71910000,
949: .vram_size = 0x00100000,
950: .nvram_size = 0x2000,
951: .esp_irq = 18,
952: .le_irq = 16,
953: .clock_irq = 7,
954: .clock1_irq = 19,
955: .ms_kb_irq = 14,
956: .ser_irq = 15,
957: .fd_irq = 22,
958: .me_irq = 30,
959: .nvram_machine_id = 0x80,
960: .machine_id = lx_id,
961: .iommu_version = 0x04000000,
962: .intbit_to_level = {
963: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
964: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
965: },
966: .max_mem = 0x10000000,
967: .default_cpu_model = "TI MicroSparc I",
968: },
969: /* SS-4 */
970: {
971: .iommu_base = 0x10000000,
972: .tcx_base = 0x50000000,
973: .cs_base = 0x6c000000,
974: .slavio_base = 0x70000000,
975: .ms_kb_base = 0x71000000,
976: .serial_base = 0x71100000,
977: .nvram_base = 0x71200000,
978: .fd_base = 0x71400000,
979: .counter_base = 0x71d00000,
980: .intctl_base = 0x71e00000,
981: .idreg_base = 0x78000000,
982: .dma_base = 0x78400000,
983: .esp_base = 0x78800000,
984: .le_base = 0x78c00000,
985: .apc_base = 0x6a000000,
986: .aux1_base = 0x71900000,
987: .aux2_base = 0x71910000,
988: .vram_size = 0x00100000,
989: .nvram_size = 0x2000,
990: .esp_irq = 18,
991: .le_irq = 16,
992: .clock_irq = 7,
993: .clock1_irq = 19,
994: .ms_kb_irq = 14,
995: .ser_irq = 15,
996: .fd_irq = 22,
997: .me_irq = 30,
998: .cs_irq = 5,
999: .nvram_machine_id = 0x80,
1000: .machine_id = ss4_id,
1001: .iommu_version = 0x05000000,
1002: .intbit_to_level = {
1003: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1004: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1005: },
1006: .max_mem = 0x10000000,
1007: .default_cpu_model = "Fujitsu MB86904",
1008: },
1009: /* SPARCClassic */
1010: {
1011: .iommu_base = 0x10000000,
1012: .tcx_base = 0x50000000,
1013: .slavio_base = 0x70000000,
1014: .ms_kb_base = 0x71000000,
1015: .serial_base = 0x71100000,
1016: .nvram_base = 0x71200000,
1017: .fd_base = 0x71400000,
1018: .counter_base = 0x71d00000,
1019: .intctl_base = 0x71e00000,
1020: .idreg_base = 0x78000000,
1021: .dma_base = 0x78400000,
1022: .esp_base = 0x78800000,
1023: .le_base = 0x78c00000,
1024: .apc_base = 0x6a000000,
1025: .aux1_base = 0x71900000,
1026: .aux2_base = 0x71910000,
1027: .vram_size = 0x00100000,
1028: .nvram_size = 0x2000,
1029: .esp_irq = 18,
1030: .le_irq = 16,
1031: .clock_irq = 7,
1032: .clock1_irq = 19,
1033: .ms_kb_irq = 14,
1034: .ser_irq = 15,
1035: .fd_irq = 22,
1036: .me_irq = 30,
1037: .nvram_machine_id = 0x80,
1038: .machine_id = scls_id,
1039: .iommu_version = 0x05000000,
1040: .intbit_to_level = {
1041: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1042: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1043: },
1044: .max_mem = 0x10000000,
1045: .default_cpu_model = "TI MicroSparc I",
1046: },
1047: /* SPARCbook */
1048: {
1049: .iommu_base = 0x10000000,
1050: .tcx_base = 0x50000000, // XXX
1051: .slavio_base = 0x70000000,
1052: .ms_kb_base = 0x71000000,
1053: .serial_base = 0x71100000,
1054: .nvram_base = 0x71200000,
1055: .fd_base = 0x71400000,
1056: .counter_base = 0x71d00000,
1057: .intctl_base = 0x71e00000,
1058: .idreg_base = 0x78000000,
1059: .dma_base = 0x78400000,
1060: .esp_base = 0x78800000,
1061: .le_base = 0x78c00000,
1062: .apc_base = 0x6a000000,
1063: .aux1_base = 0x71900000,
1064: .aux2_base = 0x71910000,
1065: .vram_size = 0x00100000,
1066: .nvram_size = 0x2000,
1067: .esp_irq = 18,
1068: .le_irq = 16,
1069: .clock_irq = 7,
1070: .clock1_irq = 19,
1071: .ms_kb_irq = 14,
1072: .ser_irq = 15,
1073: .fd_irq = 22,
1074: .me_irq = 30,
1075: .nvram_machine_id = 0x80,
1076: .machine_id = sbook_id,
1077: .iommu_version = 0x05000000,
1078: .intbit_to_level = {
1079: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1080: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1081: },
1082: .max_mem = 0x10000000,
1083: .default_cpu_model = "TI MicroSparc I",
1.1.1.6 root 1084: },
1085: };
1086:
1087: /* SPARCstation 5 hardware initialisation */
1.1.1.8 ! root 1088: static void ss5_init(ram_addr_t RAM_size,
1.1.1.7 root 1089: const char *boot_device,
1.1.1.6 root 1090: const char *kernel_filename, const char *kernel_cmdline,
1091: const char *initrd_filename, const char *cpu_model)
1092: {
1.1.1.7 root 1093: sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1094: kernel_cmdline, initrd_filename, cpu_model);
1095: }
1096:
1097: /* SPARCstation 10 hardware initialisation */
1.1.1.8 ! root 1098: static void ss10_init(ram_addr_t RAM_size,
1.1.1.7 root 1099: const char *boot_device,
1.1.1.6 root 1100: const char *kernel_filename, const char *kernel_cmdline,
1101: const char *initrd_filename, const char *cpu_model)
1102: {
1.1.1.7 root 1103: sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1104: kernel_cmdline, initrd_filename, cpu_model);
1105: }
1106:
1107: /* SPARCserver 600MP hardware initialisation */
1.1.1.8 ! root 1108: static void ss600mp_init(ram_addr_t RAM_size,
1.1.1.7 root 1109: const char *boot_device,
1110: const char *kernel_filename,
1111: const char *kernel_cmdline,
1.1.1.6 root 1112: const char *initrd_filename, const char *cpu_model)
1113: {
1.1.1.7 root 1114: sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1115: kernel_cmdline, initrd_filename, cpu_model);
1116: }
1117:
1118: /* SPARCstation 20 hardware initialisation */
1.1.1.8 ! root 1119: static void ss20_init(ram_addr_t RAM_size,
1.1.1.7 root 1120: const char *boot_device,
1.1.1.6 root 1121: const char *kernel_filename, const char *kernel_cmdline,
1122: const char *initrd_filename, const char *cpu_model)
1123: {
1.1.1.7 root 1124: sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1125: kernel_cmdline, initrd_filename, cpu_model);
1126: }
1127:
1.1.1.7 root 1128: /* SPARCstation Voyager hardware initialisation */
1.1.1.8 ! root 1129: static void vger_init(ram_addr_t RAM_size,
1.1.1.7 root 1130: const char *boot_device,
1131: const char *kernel_filename, const char *kernel_cmdline,
1132: const char *initrd_filename, const char *cpu_model)
1133: {
1134: sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1135: kernel_cmdline, initrd_filename, cpu_model);
1136: }
1137:
1138: /* SPARCstation LX hardware initialisation */
1.1.1.8 ! root 1139: static void ss_lx_init(ram_addr_t RAM_size,
1.1.1.7 root 1140: const char *boot_device,
1141: const char *kernel_filename, const char *kernel_cmdline,
1142: const char *initrd_filename, const char *cpu_model)
1143: {
1144: sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1145: kernel_cmdline, initrd_filename, cpu_model);
1146: }
1147:
1148: /* SPARCstation 4 hardware initialisation */
1.1.1.8 ! root 1149: static void ss4_init(ram_addr_t RAM_size,
1.1.1.7 root 1150: const char *boot_device,
1.1.1.6 root 1151: const char *kernel_filename, const char *kernel_cmdline,
1152: const char *initrd_filename, const char *cpu_model)
1153: {
1.1.1.7 root 1154: sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1155: kernel_cmdline, initrd_filename, cpu_model);
1156: }
1157:
1158: /* SPARCClassic hardware initialisation */
1.1.1.8 ! root 1159: static void scls_init(ram_addr_t RAM_size,
1.1.1.7 root 1160: const char *boot_device,
1161: const char *kernel_filename, const char *kernel_cmdline,
1162: const char *initrd_filename, const char *cpu_model)
1163: {
1164: sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1165: kernel_cmdline, initrd_filename, cpu_model);
1166: }
1167:
1168: /* SPARCbook hardware initialisation */
1.1.1.8 ! root 1169: static void sbook_init(ram_addr_t RAM_size,
1.1.1.7 root 1170: const char *boot_device,
1171: const char *kernel_filename, const char *kernel_cmdline,
1172: const char *initrd_filename, const char *cpu_model)
1173: {
1174: sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1175: kernel_cmdline, initrd_filename, cpu_model);
1176: }
1177:
1.1.1.8 ! root 1178: static QEMUMachine ss5_machine = {
1.1.1.7 root 1179: .name = "SS-5",
1180: .desc = "Sun4m platform, SPARCstation 5",
1181: .init = ss5_init,
1182: .use_scsi = 1,
1.1.1.8 ! root 1183: .is_default = 1,
1.1.1.6 root 1184: };
1185:
1.1.1.8 ! root 1186: static QEMUMachine ss10_machine = {
1.1.1.7 root 1187: .name = "SS-10",
1188: .desc = "Sun4m platform, SPARCstation 10",
1189: .init = ss10_init,
1190: .use_scsi = 1,
1191: .max_cpus = 4,
1.1.1.6 root 1192: };
1193:
1.1.1.8 ! root 1194: static QEMUMachine ss600mp_machine = {
1.1.1.7 root 1195: .name = "SS-600MP",
1196: .desc = "Sun4m platform, SPARCserver 600MP",
1197: .init = ss600mp_init,
1198: .use_scsi = 1,
1199: .max_cpus = 4,
1.1.1.6 root 1200: };
1201:
1.1.1.8 ! root 1202: static QEMUMachine ss20_machine = {
1.1.1.7 root 1203: .name = "SS-20",
1204: .desc = "Sun4m platform, SPARCstation 20",
1205: .init = ss20_init,
1206: .use_scsi = 1,
1207: .max_cpus = 4,
1.1.1.6 root 1208: };
1209:
1.1.1.8 ! root 1210: static QEMUMachine voyager_machine = {
1.1.1.7 root 1211: .name = "Voyager",
1212: .desc = "Sun4m platform, SPARCstation Voyager",
1213: .init = vger_init,
1214: .use_scsi = 1,
1215: };
1216:
1.1.1.8 ! root 1217: static QEMUMachine ss_lx_machine = {
1.1.1.7 root 1218: .name = "LX",
1219: .desc = "Sun4m platform, SPARCstation LX",
1220: .init = ss_lx_init,
1221: .use_scsi = 1,
1222: };
1223:
1.1.1.8 ! root 1224: static QEMUMachine ss4_machine = {
1.1.1.7 root 1225: .name = "SS-4",
1226: .desc = "Sun4m platform, SPARCstation 4",
1227: .init = ss4_init,
1228: .use_scsi = 1,
1229: };
1230:
1.1.1.8 ! root 1231: static QEMUMachine scls_machine = {
1.1.1.7 root 1232: .name = "SPARCClassic",
1233: .desc = "Sun4m platform, SPARCClassic",
1234: .init = scls_init,
1235: .use_scsi = 1,
1236: };
1237:
1.1.1.8 ! root 1238: static QEMUMachine sbook_machine = {
1.1.1.7 root 1239: .name = "SPARCbook",
1240: .desc = "Sun4m platform, SPARCbook",
1241: .init = sbook_init,
1242: .use_scsi = 1,
1.1.1.6 root 1243: };
1244:
1245: static const struct sun4d_hwdef sun4d_hwdefs[] = {
1246: /* SS-1000 */
1247: {
1248: .iounit_bases = {
1249: 0xfe0200000ULL,
1250: 0xfe1200000ULL,
1251: 0xfe2200000ULL,
1252: 0xfe3200000ULL,
1253: -1,
1254: },
1255: .tcx_base = 0x820000000ULL,
1256: .slavio_base = 0xf00000000ULL,
1257: .ms_kb_base = 0xf00240000ULL,
1258: .serial_base = 0xf00200000ULL,
1259: .nvram_base = 0xf00280000ULL,
1260: .counter_base = 0xf00300000ULL,
1261: .espdma_base = 0x800081000ULL,
1262: .esp_base = 0x800080000ULL,
1263: .ledma_base = 0x800040000ULL,
1264: .le_base = 0x800060000ULL,
1265: .sbi_base = 0xf02800000ULL,
1266: .vram_size = 0x00100000,
1267: .nvram_size = 0x2000,
1268: .esp_irq = 3,
1269: .le_irq = 4,
1270: .clock_irq = 14,
1271: .clock1_irq = 10,
1272: .ms_kb_irq = 12,
1273: .ser_irq = 12,
1.1.1.7 root 1274: .nvram_machine_id = 0x80,
1275: .machine_id = ss1000_id,
1.1.1.6 root 1276: .iounit_version = 0x03000000,
1.1.1.7 root 1277: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1278: .default_cpu_model = "TI SuperSparc II",
1279: },
1280: /* SS-2000 */
1281: {
1282: .iounit_bases = {
1283: 0xfe0200000ULL,
1284: 0xfe1200000ULL,
1285: 0xfe2200000ULL,
1286: 0xfe3200000ULL,
1287: 0xfe4200000ULL,
1288: },
1289: .tcx_base = 0x820000000ULL,
1290: .slavio_base = 0xf00000000ULL,
1291: .ms_kb_base = 0xf00240000ULL,
1292: .serial_base = 0xf00200000ULL,
1293: .nvram_base = 0xf00280000ULL,
1294: .counter_base = 0xf00300000ULL,
1295: .espdma_base = 0x800081000ULL,
1296: .esp_base = 0x800080000ULL,
1297: .ledma_base = 0x800040000ULL,
1298: .le_base = 0x800060000ULL,
1299: .sbi_base = 0xf02800000ULL,
1300: .vram_size = 0x00100000,
1301: .nvram_size = 0x2000,
1302: .esp_irq = 3,
1303: .le_irq = 4,
1304: .clock_irq = 14,
1305: .clock1_irq = 10,
1306: .ms_kb_irq = 12,
1307: .ser_irq = 12,
1.1.1.7 root 1308: .nvram_machine_id = 0x80,
1309: .machine_id = ss2000_id,
1.1.1.6 root 1310: .iounit_version = 0x03000000,
1.1.1.7 root 1311: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1312: .default_cpu_model = "TI SuperSparc II",
1313: },
1314: };
1315:
1.1.1.7 root 1316: static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1.1.1.6 root 1317: const char *boot_device,
1.1.1.7 root 1318: const char *kernel_filename,
1.1.1.6 root 1319: const char *kernel_cmdline,
1320: const char *initrd_filename, const char *cpu_model)
1321: {
1.1.1.8 ! root 1322: CPUState *envs[MAX_CPUS];
1.1.1.6 root 1323: unsigned int i;
1.1.1.8 ! root 1324: void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
1.1.1.6 root 1325: qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1.1.1.8 ! root 1326: espdma_irq, ledma_irq;
1.1.1.6 root 1327: qemu_irq *esp_reset, *le_reset;
1.1.1.7 root 1328: unsigned long kernel_size;
1329: void *fw_cfg;
1.1.1.6 root 1330:
1331: /* init CPUs */
1332: if (!cpu_model)
1333: cpu_model = hwdef->default_cpu_model;
1334:
1.1.1.8 ! root 1335: for(i = 0; i < smp_cpus; i++) {
! 1336: envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1.1.1.6 root 1337: }
1338:
1339: for (i = smp_cpus; i < MAX_CPUS; i++)
1340: cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1341:
1.1.1.8 ! root 1342: /* set up devices */
! 1343: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.6 root 1344:
1.1.1.8 ! root 1345: prom_init(hwdef->slavio_base, bios_name);
1.1.1.6 root 1346:
1347: sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1348:
1349: for (i = 0; i < MAX_IOUNITS; i++)
1350: if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1351: iounits[i] = iommu_init(hwdef->iounit_bases[i],
1352: hwdef->iounit_version,
1353: sbi_irq[hwdef->me_irq]);
1354:
1355: espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1356: iounits[0], &espdma_irq, &esp_reset);
1357:
1358: ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1359: iounits[0], &ledma_irq, &le_reset);
1360:
1361: if (graphic_depth != 8 && graphic_depth != 24) {
1362: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1363: exit (1);
1364: }
1.1.1.8 ! root 1365: tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
! 1366: graphic_depth);
1.1.1.6 root 1367:
1.1.1.8 ! root 1368: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1.1.1.6 root 1369:
1370: nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1371: hwdef->nvram_size, 8);
1372:
1373: slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1374: sbi_cpu_irq, smp_cpus);
1375:
1376: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1.1.1.8 ! root 1377: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1.1.6 root 1378: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1379: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1.1.1.7 root 1380: escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1381: serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1.1.1.6 root 1382:
1383: if (drive_get_max_bus(IF_SCSI) > 0) {
1384: fprintf(stderr, "qemu: too many SCSI bus\n");
1385: exit(1);
1386: }
1387:
1.1.1.8 ! root 1388: esp_init(hwdef->esp_base, 2,
! 1389: espdma_memory_read, espdma_memory_write,
! 1390: espdma, espdma_irq, esp_reset);
1.1.1.6 root 1391:
1.1.1.7 root 1392: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1393: RAM_size);
1.1.1.6 root 1394:
1395: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1396: boot_device, RAM_size, kernel_size, graphic_width,
1.1.1.7 root 1397: graphic_height, graphic_depth, hwdef->nvram_machine_id,
1398: "Sun4d");
1399:
1400: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1401: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1402: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1403: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1.1.1.8 ! root 1404: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
! 1405: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
! 1406: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
! 1407: if (kernel_cmdline) {
! 1408: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
! 1409: pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
! 1410: } else {
! 1411: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
! 1412: }
! 1413: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
! 1414: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
! 1415: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
! 1416: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.6 root 1417: }
1418:
1419: /* SPARCserver 1000 hardware initialisation */
1.1.1.8 ! root 1420: static void ss1000_init(ram_addr_t RAM_size,
1.1.1.7 root 1421: const char *boot_device,
1.1.1.6 root 1422: const char *kernel_filename, const char *kernel_cmdline,
1423: const char *initrd_filename, const char *cpu_model)
1424: {
1.1.1.7 root 1425: sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1426: kernel_cmdline, initrd_filename, cpu_model);
1.1 root 1427: }
1428:
1.1.1.6 root 1429: /* SPARCcenter 2000 hardware initialisation */
1.1.1.8 ! root 1430: static void ss2000_init(ram_addr_t RAM_size,
1.1.1.7 root 1431: const char *boot_device,
1.1.1.6 root 1432: const char *kernel_filename, const char *kernel_cmdline,
1433: const char *initrd_filename, const char *cpu_model)
1434: {
1.1.1.7 root 1435: sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1436: kernel_cmdline, initrd_filename, cpu_model);
1437: }
1438:
1.1.1.8 ! root 1439: static QEMUMachine ss1000_machine = {
1.1.1.7 root 1440: .name = "SS-1000",
1441: .desc = "Sun4d platform, SPARCserver 1000",
1442: .init = ss1000_init,
1443: .use_scsi = 1,
1444: .max_cpus = 8,
1.1.1.6 root 1445: };
1446:
1.1.1.8 ! root 1447: static QEMUMachine ss2000_machine = {
1.1.1.7 root 1448: .name = "SS-2000",
1449: .desc = "Sun4d platform, SPARCcenter 2000",
1450: .init = ss2000_init,
1451: .use_scsi = 1,
1452: .max_cpus = 20,
1453: };
1454:
1455: static const struct sun4c_hwdef sun4c_hwdefs[] = {
1456: /* SS-2 */
1457: {
1458: .iommu_base = 0xf8000000,
1459: .tcx_base = 0xfe000000,
1460: .slavio_base = 0xf6000000,
1461: .intctl_base = 0xf5000000,
1462: .counter_base = 0xf3000000,
1463: .ms_kb_base = 0xf0000000,
1464: .serial_base = 0xf1000000,
1465: .nvram_base = 0xf2000000,
1466: .fd_base = 0xf7200000,
1467: .dma_base = 0xf8400000,
1468: .esp_base = 0xf8800000,
1469: .le_base = 0xf8c00000,
1470: .aux1_base = 0xf7400003,
1471: .vram_size = 0x00100000,
1472: .nvram_size = 0x800,
1473: .esp_irq = 2,
1474: .le_irq = 3,
1475: .clock_irq = 5,
1476: .clock1_irq = 7,
1477: .ms_kb_irq = 1,
1478: .ser_irq = 1,
1479: .fd_irq = 1,
1480: .me_irq = 1,
1481: .nvram_machine_id = 0x55,
1482: .machine_id = ss2_id,
1483: .max_mem = 0x10000000,
1484: .default_cpu_model = "Cypress CY7C601",
1485: },
1486: };
1487:
1488: static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1489: const char *boot_device,
1490: const char *kernel_filename,
1491: const char *kernel_cmdline,
1492: const char *initrd_filename, const char *cpu_model)
1493: {
1494: CPUState *env;
1.1.1.8 ! root 1495: void *iommu, *espdma, *ledma, *nvram;
! 1496: qemu_irq *cpu_irqs, *slavio_irq, espdma_irq, ledma_irq;
1.1.1.7 root 1497: qemu_irq *esp_reset, *le_reset;
1.1.1.8 ! root 1498: qemu_irq fdc_tc;
1.1.1.7 root 1499: unsigned long kernel_size;
1500: BlockDriverState *fd[MAX_FD];
1501: int drive_index;
1502: void *fw_cfg;
1503:
1504: /* init CPU */
1505: if (!cpu_model)
1506: cpu_model = hwdef->default_cpu_model;
1507:
1.1.1.8 ! root 1508: env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1.1.1.7 root 1509:
1.1.1.8 ! root 1510: /* set up devices */
! 1511: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.7 root 1512:
1.1.1.8 ! root 1513: prom_init(hwdef->slavio_base, bios_name);
1.1.1.7 root 1514:
1515: slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1516: &slavio_irq, cpu_irqs);
1517:
1518: iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1519: slavio_irq[hwdef->me_irq]);
1520:
1521: espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1522: iommu, &espdma_irq, &esp_reset);
1523:
1524: ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1525: slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1526: &le_reset);
1527:
1528: if (graphic_depth != 8 && graphic_depth != 24) {
1529: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1530: exit (1);
1531: }
1.1.1.8 ! root 1532: tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
! 1533: graphic_depth);
1.1.1.7 root 1534:
1.1.1.8 ! root 1535: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1.1.1.7 root 1536:
1537: nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1538: hwdef->nvram_size, 2);
1539:
1540: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1.1.1.8 ! root 1541: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1.1.7 root 1542: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1543: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1544: escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1545: slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1546: ESCC_CLOCK, 1);
1547:
1.1.1.8 ! root 1548: slavio_misc = slavio_misc_init(0, hwdef->aux1_base, 0,
! 1549: slavio_irq[hwdef->me_irq], fdc_tc);
1.1.1.7 root 1550:
1551: if (hwdef->fd_base != (target_phys_addr_t)-1) {
1552: /* there is zero or one floppy drive */
1553: memset(fd, 0, sizeof(fd));
1554: drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1555: if (drive_index != -1)
1556: fd[0] = drives_table[drive_index].bdrv;
1557:
1558: sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1.1.1.8 ! root 1559: &fdc_tc);
1.1.1.7 root 1560: }
1561:
1562: if (drive_get_max_bus(IF_SCSI) > 0) {
1563: fprintf(stderr, "qemu: too many SCSI bus\n");
1564: exit(1);
1565: }
1566:
1.1.1.8 ! root 1567: esp_init(hwdef->esp_base, 2,
! 1568: espdma_memory_read, espdma_memory_write,
! 1569: espdma, espdma_irq, esp_reset);
1.1.1.7 root 1570:
1571: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1572: RAM_size);
1573:
1574: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1575: boot_device, RAM_size, kernel_size, graphic_width,
1576: graphic_height, graphic_depth, hwdef->nvram_machine_id,
1577: "Sun4c");
1578:
1579: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1580: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1581: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1582: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1.1.1.8 ! root 1583: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
! 1584: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
! 1585: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
! 1586: if (kernel_cmdline) {
! 1587: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
! 1588: pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
! 1589: } else {
! 1590: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
! 1591: }
! 1592: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
! 1593: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
! 1594: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
! 1595: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.7 root 1596: }
1597:
1598: /* SPARCstation 2 hardware initialisation */
1.1.1.8 ! root 1599: static void ss2_init(ram_addr_t RAM_size,
1.1.1.7 root 1600: const char *boot_device,
1601: const char *kernel_filename, const char *kernel_cmdline,
1602: const char *initrd_filename, const char *cpu_model)
1603: {
1604: sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1605: kernel_cmdline, initrd_filename, cpu_model);
1606: }
1607:
1.1.1.8 ! root 1608: static QEMUMachine ss2_machine = {
1.1.1.7 root 1609: .name = "SS-2",
1610: .desc = "Sun4c platform, SPARCstation 2",
1611: .init = ss2_init,
1612: .use_scsi = 1,
1.1 root 1613: };
1.1.1.8 ! root 1614:
! 1615: static void ss2_machine_init(void)
! 1616: {
! 1617: qemu_register_machine(&ss5_machine);
! 1618: qemu_register_machine(&ss10_machine);
! 1619: qemu_register_machine(&ss600mp_machine);
! 1620: qemu_register_machine(&ss20_machine);
! 1621: qemu_register_machine(&voyager_machine);
! 1622: qemu_register_machine(&ss_lx_machine);
! 1623: qemu_register_machine(&ss4_machine);
! 1624: qemu_register_machine(&scls_machine);
! 1625: qemu_register_machine(&sbook_machine);
! 1626: qemu_register_machine(&ss1000_machine);
! 1627: qemu_register_machine(&ss2000_machine);
! 1628: qemu_register_machine(&ss2_machine);
! 1629: }
! 1630:
! 1631: machine_init(ss2_machine_init);
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