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1.1 root 1: /*
1.1.1.6 root 2: * QEMU Sun4m & Sun4d & Sun4c System Emulator
3: *
1.1 root 4: * Copyright (c) 2003-2005 Fabrice Bellard
1.1.1.6 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.8 root 24: #include "sysbus.h"
1.1.1.6 root 25: #include "qemu-timer.h"
26: #include "sun4m.h"
27: #include "nvram.h"
28: #include "sparc32_dma.h"
29: #include "fdc.h"
30: #include "sysemu.h"
31: #include "net.h"
32: #include "boards.h"
33: #include "firmware_abi.h"
1.1.1.7 root 34: #include "scsi.h"
35: #include "pc.h"
36: #include "isa.h"
37: #include "fw_cfg.h"
38: #include "escc.h"
1.1.1.6 root 39:
40: //#define DEBUG_IRQ
41:
42: /*
43: * Sun4m architecture was used in the following machines:
44: *
45: * SPARCserver 6xxMP/xx
1.1.1.7 root 46: * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47: * SPARCclassic X (4/10)
1.1.1.6 root 48: * SPARCstation LX/ZX (4/30)
49: * SPARCstation Voyager
50: * SPARCstation 10/xx, SPARCserver 10/xx
51: * SPARCstation 5, SPARCserver 5
52: * SPARCstation 20/xx, SPARCserver 20
53: * SPARCstation 4
54: *
55: * Sun4d architecture was used in the following machines:
56: *
57: * SPARCcenter 2000
58: * SPARCserver 1000
59: *
60: * Sun4c architecture was used in the following machines:
61: * SPARCstation 1/1+, SPARCserver 1/1+
62: * SPARCstation SLC
63: * SPARCstation IPC
64: * SPARCstation ELC
65: * SPARCstation IPX
66: *
67: * See for example: http://www.sunhelp.org/faq/sunref1.html
68: */
69:
70: #ifdef DEBUG_IRQ
1.1.1.8 root 71: #define DPRINTF(fmt, ...) \
72: do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
1.1.1.6 root 73: #else
1.1.1.8 root 74: #define DPRINTF(fmt, ...)
1.1.1.6 root 75: #endif
1.1 root 76:
77: #define KERNEL_LOAD_ADDR 0x00004000
78: #define CMDLINE_ADDR 0x007ff000
79: #define INITRD_LOAD_ADDR 0x00800000
1.1.1.7 root 80: #define PROM_SIZE_MAX (1024 * 1024)
1.1.1.6 root 81: #define PROM_VADDR 0xffd00000
82: #define PROM_FILENAME "openbios-sparc32"
1.1.1.7 root 83: #define CFG_ADDR 0xd00000510ULL
84: #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85:
1.1.1.2 root 86: #define MAX_CPUS 16
1.1.1.6 root 87: #define MAX_PILS 16
88:
1.1.1.7 root 89: #define ESCC_CLOCK 4915200
90:
91: struct sun4m_hwdef {
1.1.1.6 root 92: target_phys_addr_t iommu_base, slavio_base;
93: target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94: target_phys_addr_t serial_base, fd_base;
95: target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
1.1.1.7 root 96: target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
1.1.1.6 root 97: target_phys_addr_t ecc_base;
98: uint32_t ecc_version;
99: long vram_size, nvram_size;
100: // IRQ numbers are not PIL ones, but master interrupt controller
101: // register bit numbers
1.1.1.7 root 102: int esp_irq, le_irq, clock_irq, clock1_irq;
103: int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104: uint8_t nvram_machine_id;
105: uint16_t machine_id;
1.1.1.6 root 106: uint32_t iommu_version;
107: uint32_t intbit_to_level[32];
108: uint64_t max_mem;
109: const char * const default_cpu_model;
110: };
111:
112: #define MAX_IOUNITS 5
113:
114: struct sun4d_hwdef {
115: target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116: target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117: target_phys_addr_t serial_base;
118: target_phys_addr_t espdma_base, esp_base;
119: target_phys_addr_t ledma_base, le_base;
120: target_phys_addr_t tcx_base;
121: target_phys_addr_t sbi_base;
122: unsigned long vram_size, nvram_size;
123: // IRQ numbers are not PIL ones, but SBI register bit numbers
124: int esp_irq, le_irq, clock_irq, clock1_irq;
125: int ser_irq, ms_kb_irq, me_irq;
1.1.1.7 root 126: uint8_t nvram_machine_id;
127: uint16_t machine_id;
1.1.1.6 root 128: uint32_t iounit_version;
129: uint64_t max_mem;
130: const char * const default_cpu_model;
131: };
1.1 root 132:
1.1.1.7 root 133: struct sun4c_hwdef {
134: target_phys_addr_t iommu_base, slavio_base;
135: target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136: target_phys_addr_t serial_base, fd_base;
137: target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138: target_phys_addr_t tcx_base, aux1_base;
139: long vram_size, nvram_size;
140: // IRQ numbers are not PIL ones, but master interrupt controller
141: // register bit numbers
142: int esp_irq, le_irq, clock_irq, clock1_irq;
143: int ser_irq, ms_kb_irq, fd_irq, me_irq;
144: uint8_t nvram_machine_id;
145: uint16_t machine_id;
146: uint32_t iommu_version;
147: uint32_t intbit_to_level[32];
148: uint64_t max_mem;
149: const char * const default_cpu_model;
150: };
1.1 root 151:
152: int DMA_get_channel_mode (int nchan)
153: {
154: return 0;
155: }
156: int DMA_read_memory (int nchan, void *buf, int pos, int size)
157: {
158: return 0;
159: }
160: int DMA_write_memory (int nchan, void *buf, int pos, int size)
161: {
162: return 0;
163: }
164: void DMA_hold_DREQ (int nchan) {}
165: void DMA_release_DREQ (int nchan) {}
166: void DMA_schedule(int nchan) {}
167: void DMA_init (int high_page_enable) {}
168: void DMA_register_channel (int nchan,
169: DMA_transfer_handler transfer_handler,
170: void *opaque)
171: {
172: }
173:
1.1.1.8 root 174: static int fw_cfg_boot_set(void *opaque, const char *boot_device)
1.1.1.7 root 175: {
1.1.1.8 root 176: fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
1.1.1.7 root 177: return 0;
178: }
1.1 root 179:
1.1.1.2 root 180: static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
1.1.1.7 root 181: const char *boot_devices, ram_addr_t RAM_size,
1.1.1.6 root 182: uint32_t kernel_size,
183: int width, int height, int depth,
1.1.1.7 root 184: int nvram_machine_id, const char *arch)
1.1 root 185: {
1.1.1.6 root 186: unsigned int i;
187: uint32_t start, end;
188: uint8_t image[0x1ff0];
189: struct OpenBIOS_nvpart_v1 *part_header;
190:
191: memset(image, '\0', sizeof(image));
1.1 root 192:
1.1.1.8 root 193: start = 0;
1.1.1.6 root 194:
195: // OpenBIOS nvram variables
196: // Variable partition
197: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
198: part_header->signature = OPENBIOS_PART_SYSTEM;
1.1.1.7 root 199: pstrcpy(part_header->name, sizeof(part_header->name), "system");
1.1.1.6 root 200:
201: end = start + sizeof(struct OpenBIOS_nvpart_v1);
202: for (i = 0; i < nb_prom_envs; i++)
203: end = OpenBIOS_set_var(image, end, prom_envs[i]);
204:
205: // End marker
206: image[end++] = '\0';
207:
208: end = start + ((end - start + 15) & ~15);
209: OpenBIOS_finish_partition(part_header, end - start);
210:
211: // free partition
212: start = end;
213: part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
214: part_header->signature = OPENBIOS_PART_FREE;
1.1.1.7 root 215: pstrcpy(part_header->name, sizeof(part_header->name), "free");
1.1.1.6 root 216:
217: end = 0x1fd0;
218: OpenBIOS_finish_partition(part_header, end - start);
219:
1.1.1.7 root 220: Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
221: nvram_machine_id);
1.1.1.6 root 222:
223: for (i = 0; i < sizeof(image); i++)
224: m48t59_write(nvram, i, image[i]);
1.1 root 225: }
226:
227: static void *slavio_intctl;
228:
1.1.1.8 root 229: void pic_info(Monitor *mon)
1.1 root 230: {
1.1.1.6 root 231: if (slavio_intctl)
1.1.1.8 root 232: slavio_pic_info(mon, slavio_intctl);
1.1 root 233: }
234:
1.1.1.8 root 235: void irq_info(Monitor *mon)
1.1 root 236: {
1.1.1.6 root 237: if (slavio_intctl)
1.1.1.8 root 238: slavio_irq_info(mon, slavio_intctl);
1.1 root 239: }
240:
1.1.1.6 root 241: void cpu_check_irqs(CPUState *env)
1.1 root 242: {
1.1.1.6 root 243: if (env->pil_in && (env->interrupt_index == 0 ||
244: (env->interrupt_index & ~15) == TT_EXTINT)) {
245: unsigned int i;
246:
247: for (i = 15; i > 0; i--) {
248: if (env->pil_in & (1 << i)) {
249: int old_interrupt = env->interrupt_index;
250:
251: env->interrupt_index = TT_EXTINT | i;
1.1.1.7 root 252: if (old_interrupt != env->interrupt_index) {
253: DPRINTF("Set CPU IRQ %d\n", i);
1.1.1.6 root 254: cpu_interrupt(env, CPU_INTERRUPT_HARD);
1.1.1.7 root 255: }
1.1.1.6 root 256: break;
257: }
258: }
259: } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
1.1.1.7 root 260: DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
1.1.1.6 root 261: env->interrupt_index = 0;
262: cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
263: }
1.1 root 264: }
265:
1.1.1.6 root 266: static void cpu_set_irq(void *opaque, int irq, int level)
1.1.1.4 root 267: {
1.1.1.6 root 268: CPUState *env = opaque;
269:
270: if (level) {
271: DPRINTF("Raise CPU IRQ %d\n", irq);
272: env->halted = 0;
273: env->pil_in |= 1 << irq;
274: cpu_check_irqs(env);
275: } else {
276: DPRINTF("Lower CPU IRQ %d\n", irq);
277: env->pil_in &= ~(1 << irq);
278: cpu_check_irqs(env);
279: }
1.1.1.4 root 280: }
281:
1.1.1.6 root 282: static void dummy_cpu_set_irq(void *opaque, int irq, int level)
1.1.1.2 root 283: {
284: }
285:
1.1 root 286: static void *slavio_misc;
287:
288: void qemu_system_powerdown(void)
289: {
290: slavio_set_power_fail(slavio_misc, 1);
291: }
292:
1.1.1.2 root 293: static void main_cpu_reset(void *opaque)
294: {
295: CPUState *env = opaque;
1.1.1.6 root 296:
1.1.1.2 root 297: cpu_reset(env);
1.1.1.6 root 298: env->halted = 0;
1.1.1.2 root 299: }
300:
1.1.1.6 root 301: static void secondary_cpu_reset(void *opaque)
1.1 root 302: {
1.1.1.6 root 303: CPUState *env = opaque;
304:
305: cpu_reset(env);
306: env->halted = 1;
307: }
308:
1.1.1.7 root 309: static void cpu_halt_signal(void *opaque, int irq, int level)
310: {
311: if (level && cpu_single_env)
312: cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
313: }
314:
1.1.1.6 root 315: static unsigned long sun4m_load_kernel(const char *kernel_filename,
1.1.1.7 root 316: const char *initrd_filename,
317: ram_addr_t RAM_size)
1.1.1.6 root 318: {
319: int linux_boot;
1.1 root 320: unsigned int i;
1.1.1.6 root 321: long initrd_size, kernel_size;
1.1 root 322:
323: linux_boot = (kernel_filename != NULL);
324:
1.1.1.6 root 325: kernel_size = 0;
326: if (linux_boot) {
327: kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
328: NULL);
329: if (kernel_size < 0)
1.1.1.7 root 330: kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
331: RAM_size - KERNEL_LOAD_ADDR);
1.1.1.6 root 332: if (kernel_size < 0)
1.1.1.7 root 333: kernel_size = load_image_targphys(kernel_filename,
334: KERNEL_LOAD_ADDR,
335: RAM_size - KERNEL_LOAD_ADDR);
1.1.1.6 root 336: if (kernel_size < 0) {
337: fprintf(stderr, "qemu: could not load kernel '%s'\n",
338: kernel_filename);
339: exit(1);
340: }
341:
342: /* load initrd */
343: initrd_size = 0;
344: if (initrd_filename) {
1.1.1.7 root 345: initrd_size = load_image_targphys(initrd_filename,
346: INITRD_LOAD_ADDR,
347: RAM_size - INITRD_LOAD_ADDR);
1.1.1.6 root 348: if (initrd_size < 0) {
349: fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
350: initrd_filename);
351: exit(1);
352: }
353: }
354: if (initrd_size > 0) {
355: for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
1.1.1.7 root 356: if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
357: stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
358: stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
1.1.1.6 root 359: break;
360: }
361: }
362: }
363: }
364: return kernel_size;
365: }
366:
1.1.1.8 root 367: static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
368: void *dma_opaque, qemu_irq irq, qemu_irq *reset)
369: {
370: DeviceState *dev;
371: SysBusDevice *s;
372:
373: qemu_check_nic_model(&nd_table[0], "lance");
374:
375: dev = qdev_create(NULL, "lance");
376: dev->nd = nd;
1.1.1.9 ! root 377: qdev_prop_set_ptr(dev, "dma", dma_opaque);
1.1.1.8 root 378: qdev_init(dev);
379: s = sysbus_from_qdev(dev);
380: sysbus_mmio_map(s, 0, leaddr);
381: sysbus_connect_irq(s, 0, irq);
382: *reset = qdev_get_gpio_in(dev, 0);
383: }
384:
385: /* NCR89C100/MACIO Internal ID register */
386: static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
387:
388: static void idreg_init(target_phys_addr_t addr)
389: {
390: DeviceState *dev;
391: SysBusDevice *s;
392:
393: dev = qdev_create(NULL, "macio_idreg");
394: qdev_init(dev);
395: s = sysbus_from_qdev(dev);
396:
397: sysbus_mmio_map(s, 0, addr);
398: cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
399: }
400:
401: static void idreg_init1(SysBusDevice *dev)
402: {
403: ram_addr_t idreg_offset;
404:
405: idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
406: sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
407: }
408:
409: static SysBusDeviceInfo idreg_info = {
410: .init = idreg_init1,
411: .qdev.name = "macio_idreg",
412: .qdev.size = sizeof(SysBusDevice),
413: };
414:
415: static void idreg_register_devices(void)
416: {
417: sysbus_register_withprop(&idreg_info);
418: }
419:
420: device_init(idreg_register_devices);
421:
422: /* Boot PROM (OpenBIOS) */
423: static void prom_init(target_phys_addr_t addr, const char *bios_name)
424: {
425: DeviceState *dev;
426: SysBusDevice *s;
427: char *filename;
428: int ret;
429:
430: dev = qdev_create(NULL, "openprom");
431: qdev_init(dev);
432: s = sysbus_from_qdev(dev);
433:
434: sysbus_mmio_map(s, 0, addr);
435:
436: /* load boot prom */
437: if (bios_name == NULL) {
438: bios_name = PROM_FILENAME;
439: }
440: filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
441: if (filename) {
442: ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL);
443: if (ret < 0 || ret > PROM_SIZE_MAX) {
444: ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
445: }
446: qemu_free(filename);
447: } else {
448: ret = -1;
449: }
450: if (ret < 0 || ret > PROM_SIZE_MAX) {
451: fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
452: exit(1);
453: }
454: }
455:
456: static void prom_init1(SysBusDevice *dev)
457: {
458: ram_addr_t prom_offset;
459:
460: prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
461: sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
462: }
463:
464: static SysBusDeviceInfo prom_info = {
465: .init = prom_init1,
466: .qdev.name = "openprom",
467: .qdev.size = sizeof(SysBusDevice),
468: .qdev.props = (Property[]) {
469: {/* end of property list */}
470: }
471: };
472:
473: static void prom_register_devices(void)
474: {
475: sysbus_register_withprop(&prom_info);
476: }
477:
478: device_init(prom_register_devices);
479:
480: typedef struct RamDevice
481: {
482: SysBusDevice busdev;
483: uint32_t size;
484: } RamDevice;
485:
486: /* System RAM */
487: static void ram_init1(SysBusDevice *dev)
488: {
489: ram_addr_t RAM_size, ram_offset;
490: RamDevice *d = FROM_SYSBUS(RamDevice, dev);
491:
492: RAM_size = d->size;
493:
494: ram_offset = qemu_ram_alloc(RAM_size);
495: sysbus_init_mmio(dev, RAM_size, ram_offset);
496: }
497:
498: static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
499: uint64_t max_mem)
500: {
501: DeviceState *dev;
502: SysBusDevice *s;
503: RamDevice *d;
504:
505: /* allocate RAM */
506: if ((uint64_t)RAM_size > max_mem) {
507: fprintf(stderr,
508: "qemu: Too much memory for this machine: %d, maximum %d\n",
509: (unsigned int)(RAM_size / (1024 * 1024)),
510: (unsigned int)(max_mem / (1024 * 1024)));
511: exit(1);
512: }
513: dev = qdev_create(NULL, "memory");
514: s = sysbus_from_qdev(dev);
515:
516: d = FROM_SYSBUS(RamDevice, s);
517: d->size = RAM_size;
518: qdev_init(dev);
519:
520: sysbus_mmio_map(s, 0, addr);
521: }
522:
523: static SysBusDeviceInfo ram_info = {
524: .init = ram_init1,
525: .qdev.name = "memory",
526: .qdev.size = sizeof(RamDevice),
527: .qdev.props = (Property[]) {
528: {
529: .name = "size",
530: .info = &qdev_prop_uint32,
531: .offset = offsetof(RamDevice, size),
532: },
533: {/* end of property list */}
534: }
535: };
536:
537: static void ram_register_devices(void)
538: {
539: sysbus_register_withprop(&ram_info);
540: }
541:
542: device_init(ram_register_devices);
543:
544: static CPUState *cpu_devinit(const char *cpu_model, unsigned int id,
545: uint64_t prom_addr, qemu_irq **cpu_irqs)
546: {
547: CPUState *env;
548:
549: env = cpu_init(cpu_model);
550: if (!env) {
551: fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
552: exit(1);
553: }
554:
555: cpu_sparc_set_id(env, id);
556: if (id == 0) {
557: qemu_register_reset(main_cpu_reset, env);
558: } else {
559: qemu_register_reset(secondary_cpu_reset, env);
560: env->halted = 1;
561: }
562: *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
563: env->prom_addr = prom_addr;
564:
565: return env;
566: }
567:
1.1.1.7 root 568: static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
1.1.1.6 root 569: const char *boot_device,
1.1.1.7 root 570: const char *kernel_filename,
1.1.1.6 root 571: const char *kernel_cmdline,
572: const char *initrd_filename, const char *cpu_model)
573: {
1.1.1.8 root 574: CPUState *envs[MAX_CPUS];
1.1.1.6 root 575: unsigned int i;
1.1.1.8 root 576: void *iommu, *espdma, *ledma, *nvram;
577: qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
578: espdma_irq, ledma_irq;
1.1.1.6 root 579: qemu_irq *esp_reset, *le_reset;
1.1.1.8 root 580: qemu_irq fdc_tc;
1.1.1.7 root 581: qemu_irq *cpu_halt;
582: unsigned long kernel_size;
1.1.1.6 root 583: BlockDriverState *fd[MAX_FD];
1.1.1.7 root 584: int drive_index;
585: void *fw_cfg;
1.1.1.8 root 586: DeviceState *dev;
1.1.1.6 root 587:
1.1.1.2 root 588: /* init CPUs */
1.1.1.6 root 589: if (!cpu_model)
590: cpu_model = hwdef->default_cpu_model;
591:
1.1.1.2 root 592: for(i = 0; i < smp_cpus; i++) {
1.1.1.8 root 593: envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1.1.1.2 root 594: }
1.1.1.6 root 595:
596: for (i = smp_cpus; i < MAX_CPUS; i++)
597: cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
598:
599:
1.1.1.8 root 600: /* set up devices */
601: ram_init(0, RAM_size, hwdef->max_mem);
1.1 root 602:
1.1.1.8 root 603: prom_init(hwdef->slavio_base, bios_name);
1.1.1.6 root 604:
1.1.1.8 root 605: dev = slavio_intctl_init(hwdef->intctl_base,
606: hwdef->intctl_base + 0x10000ULL,
607: &hwdef->intbit_to_level[0],
608: cpu_irqs,
609: hwdef->clock_irq);
1.1.1.2 root 610:
1.1.1.8 root 611: for (i = 0; i < 32; i++) {
612: slavio_irq[i] = qdev_get_gpio_in(dev, i);
613: }
614: for (i = 0; i < MAX_CPUS; i++) {
615: slavio_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
616: }
1.1.1.6 root 617:
1.1.1.7 root 618: if (hwdef->idreg_base) {
1.1.1.8 root 619: idreg_init(hwdef->idreg_base);
1.1.1.3 root 620: }
1.1.1.6 root 621:
622: iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
623: slavio_irq[hwdef->me_irq]);
624:
625: espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
626: iommu, &espdma_irq, &esp_reset);
627:
628: ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
629: slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
630: &le_reset);
631:
632: if (graphic_depth != 8 && graphic_depth != 24) {
633: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
634: exit (1);
635: }
1.1.1.8 root 636: tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
637: graphic_depth);
1.1.1.6 root 638:
1.1.1.8 root 639: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1.1.1.6 root 640:
641: nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
642: hwdef->nvram_size, 8);
643:
644: slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
645: slavio_cpu_irq, smp_cpus);
646:
647: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1.1.1.8 root 648: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1 root 649: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
650: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1.1.1.7 root 651: escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
652: serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1.1.1.6 root 653:
1.1.1.7 root 654: cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
1.1.1.8 root 655: slavio_misc = slavio_misc_init(hwdef->slavio_base,
1.1.1.7 root 656: hwdef->aux1_base, hwdef->aux2_base,
1.1.1.8 root 657: slavio_irq[hwdef->me_irq], fdc_tc);
658: if (hwdef->apc_base) {
659: apc_init(hwdef->apc_base, cpu_halt[0]);
660: }
1.1.1.7 root 661:
662: if (hwdef->fd_base) {
1.1.1.6 root 663: /* there is zero or one floppy drive */
1.1.1.7 root 664: memset(fd, 0, sizeof(fd));
665: drive_index = drive_get_index(IF_FLOPPY, 0, 0);
666: if (drive_index != -1)
667: fd[0] = drives_table[drive_index].bdrv;
1.1.1.6 root 668:
1.1.1.7 root 669: sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1.1.1.8 root 670: &fdc_tc);
1.1.1.6 root 671: }
672:
673: if (drive_get_max_bus(IF_SCSI) > 0) {
674: fprintf(stderr, "qemu: too many SCSI bus\n");
675: exit(1);
676: }
677:
1.1.1.8 root 678: esp_init(hwdef->esp_base, 2,
679: espdma_memory_read, espdma_memory_write,
680: espdma, espdma_irq, esp_reset);
681:
682: if (hwdef->cs_base) {
683: sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
684: slavio_irq[hwdef->cs_irq]);
1.1.1.6 root 685: }
686:
1.1.1.7 root 687: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
688: RAM_size);
1.1.1.6 root 689:
690: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
691: boot_device, RAM_size, kernel_size, graphic_width,
1.1.1.7 root 692: graphic_height, graphic_depth, hwdef->nvram_machine_id,
693: "Sun4m");
1.1.1.6 root 694:
1.1.1.7 root 695: if (hwdef->ecc_base)
696: ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
697: hwdef->ecc_version);
698:
699: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
700: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
701: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
702: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
703: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1.1.1.8 root 704: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
705: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
706: if (kernel_cmdline) {
707: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
708: pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
709: } else {
710: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
711: }
712: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
713: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
714: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
715: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.7 root 716: }
717:
718: enum {
719: ss2_id = 0,
720: ss5_id = 32,
721: vger_id,
722: lx_id,
723: ss4_id,
724: scls_id,
725: sbook_id,
726: ss10_id = 64,
727: ss20_id,
728: ss600mp_id,
729: ss1000_id = 96,
730: ss2000_id,
731: };
1.1.1.6 root 732:
1.1.1.7 root 733: static const struct sun4m_hwdef sun4m_hwdefs[] = {
1.1.1.6 root 734: /* SS-5 */
735: {
736: .iommu_base = 0x10000000,
737: .tcx_base = 0x50000000,
738: .cs_base = 0x6c000000,
739: .slavio_base = 0x70000000,
740: .ms_kb_base = 0x71000000,
741: .serial_base = 0x71100000,
742: .nvram_base = 0x71200000,
743: .fd_base = 0x71400000,
744: .counter_base = 0x71d00000,
745: .intctl_base = 0x71e00000,
746: .idreg_base = 0x78000000,
747: .dma_base = 0x78400000,
748: .esp_base = 0x78800000,
749: .le_base = 0x78c00000,
1.1.1.7 root 750: .apc_base = 0x6a000000,
751: .aux1_base = 0x71900000,
752: .aux2_base = 0x71910000,
1.1.1.6 root 753: .vram_size = 0x00100000,
754: .nvram_size = 0x2000,
755: .esp_irq = 18,
756: .le_irq = 16,
757: .clock_irq = 7,
758: .clock1_irq = 19,
759: .ms_kb_irq = 14,
760: .ser_irq = 15,
761: .fd_irq = 22,
762: .me_irq = 30,
763: .cs_irq = 5,
1.1.1.7 root 764: .nvram_machine_id = 0x80,
765: .machine_id = ss5_id,
1.1.1.6 root 766: .iommu_version = 0x05000000,
767: .intbit_to_level = {
768: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
769: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
770: },
771: .max_mem = 0x10000000,
772: .default_cpu_model = "Fujitsu MB86904",
773: },
774: /* SS-10 */
775: {
776: .iommu_base = 0xfe0000000ULL,
777: .tcx_base = 0xe20000000ULL,
778: .slavio_base = 0xff0000000ULL,
779: .ms_kb_base = 0xff1000000ULL,
780: .serial_base = 0xff1100000ULL,
781: .nvram_base = 0xff1200000ULL,
782: .fd_base = 0xff1700000ULL,
783: .counter_base = 0xff1300000ULL,
784: .intctl_base = 0xff1400000ULL,
785: .idreg_base = 0xef0000000ULL,
786: .dma_base = 0xef0400000ULL,
787: .esp_base = 0xef0800000ULL,
788: .le_base = 0xef0c00000ULL,
1.1.1.7 root 789: .apc_base = 0xefa000000ULL, // XXX should not exist
790: .aux1_base = 0xff1800000ULL,
791: .aux2_base = 0xff1a01000ULL,
1.1.1.6 root 792: .ecc_base = 0xf00000000ULL,
793: .ecc_version = 0x10000000, // version 0, implementation 1
794: .vram_size = 0x00100000,
795: .nvram_size = 0x2000,
796: .esp_irq = 18,
797: .le_irq = 16,
798: .clock_irq = 7,
799: .clock1_irq = 19,
800: .ms_kb_irq = 14,
801: .ser_irq = 15,
802: .fd_irq = 22,
803: .me_irq = 30,
1.1.1.7 root 804: .ecc_irq = 28,
805: .nvram_machine_id = 0x72,
806: .machine_id = ss10_id,
1.1.1.6 root 807: .iommu_version = 0x03000000,
808: .intbit_to_level = {
809: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
810: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
811: },
1.1.1.7 root 812: .max_mem = 0xf00000000ULL,
1.1.1.6 root 813: .default_cpu_model = "TI SuperSparc II",
814: },
815: /* SS-600MP */
816: {
817: .iommu_base = 0xfe0000000ULL,
818: .tcx_base = 0xe20000000ULL,
819: .slavio_base = 0xff0000000ULL,
820: .ms_kb_base = 0xff1000000ULL,
821: .serial_base = 0xff1100000ULL,
822: .nvram_base = 0xff1200000ULL,
823: .counter_base = 0xff1300000ULL,
824: .intctl_base = 0xff1400000ULL,
825: .dma_base = 0xef0081000ULL,
826: .esp_base = 0xef0080000ULL,
827: .le_base = 0xef0060000ULL,
1.1.1.7 root 828: .apc_base = 0xefa000000ULL, // XXX should not exist
829: .aux1_base = 0xff1800000ULL,
830: .aux2_base = 0xff1a01000ULL, // XXX should not exist
1.1.1.6 root 831: .ecc_base = 0xf00000000ULL,
832: .ecc_version = 0x00000000, // version 0, implementation 0
833: .vram_size = 0x00100000,
834: .nvram_size = 0x2000,
835: .esp_irq = 18,
836: .le_irq = 16,
837: .clock_irq = 7,
838: .clock1_irq = 19,
839: .ms_kb_irq = 14,
840: .ser_irq = 15,
841: .fd_irq = 22,
842: .me_irq = 30,
1.1.1.7 root 843: .ecc_irq = 28,
844: .nvram_machine_id = 0x71,
845: .machine_id = ss600mp_id,
1.1.1.6 root 846: .iommu_version = 0x01000000,
847: .intbit_to_level = {
848: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
849: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
850: },
1.1.1.7 root 851: .max_mem = 0xf00000000ULL,
1.1.1.6 root 852: .default_cpu_model = "TI SuperSparc II",
853: },
854: /* SS-20 */
855: {
856: .iommu_base = 0xfe0000000ULL,
857: .tcx_base = 0xe20000000ULL,
858: .slavio_base = 0xff0000000ULL,
859: .ms_kb_base = 0xff1000000ULL,
860: .serial_base = 0xff1100000ULL,
861: .nvram_base = 0xff1200000ULL,
862: .fd_base = 0xff1700000ULL,
863: .counter_base = 0xff1300000ULL,
864: .intctl_base = 0xff1400000ULL,
865: .idreg_base = 0xef0000000ULL,
866: .dma_base = 0xef0400000ULL,
867: .esp_base = 0xef0800000ULL,
868: .le_base = 0xef0c00000ULL,
1.1.1.7 root 869: .apc_base = 0xefa000000ULL, // XXX should not exist
870: .aux1_base = 0xff1800000ULL,
871: .aux2_base = 0xff1a01000ULL,
1.1.1.6 root 872: .ecc_base = 0xf00000000ULL,
873: .ecc_version = 0x20000000, // version 0, implementation 2
874: .vram_size = 0x00100000,
875: .nvram_size = 0x2000,
876: .esp_irq = 18,
877: .le_irq = 16,
878: .clock_irq = 7,
879: .clock1_irq = 19,
880: .ms_kb_irq = 14,
881: .ser_irq = 15,
882: .fd_irq = 22,
883: .me_irq = 30,
1.1.1.7 root 884: .ecc_irq = 28,
885: .nvram_machine_id = 0x72,
886: .machine_id = ss20_id,
1.1.1.6 root 887: .iommu_version = 0x13000000,
888: .intbit_to_level = {
889: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
890: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
891: },
1.1.1.7 root 892: .max_mem = 0xf00000000ULL,
1.1.1.6 root 893: .default_cpu_model = "TI SuperSparc II",
894: },
1.1.1.7 root 895: /* Voyager */
1.1.1.6 root 896: {
1.1.1.7 root 897: .iommu_base = 0x10000000,
898: .tcx_base = 0x50000000,
899: .slavio_base = 0x70000000,
900: .ms_kb_base = 0x71000000,
901: .serial_base = 0x71100000,
902: .nvram_base = 0x71200000,
903: .fd_base = 0x71400000,
904: .counter_base = 0x71d00000,
905: .intctl_base = 0x71e00000,
906: .idreg_base = 0x78000000,
907: .dma_base = 0x78400000,
908: .esp_base = 0x78800000,
909: .le_base = 0x78c00000,
910: .apc_base = 0x71300000, // pmc
911: .aux1_base = 0x71900000,
912: .aux2_base = 0x71910000,
1.1.1.6 root 913: .vram_size = 0x00100000,
1.1.1.7 root 914: .nvram_size = 0x2000,
915: .esp_irq = 18,
916: .le_irq = 16,
917: .clock_irq = 7,
918: .clock1_irq = 19,
919: .ms_kb_irq = 14,
920: .ser_irq = 15,
921: .fd_irq = 22,
922: .me_irq = 30,
923: .nvram_machine_id = 0x80,
924: .machine_id = vger_id,
925: .iommu_version = 0x05000000,
926: .intbit_to_level = {
927: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
928: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
929: },
1.1.1.6 root 930: .max_mem = 0x10000000,
1.1.1.7 root 931: .default_cpu_model = "Fujitsu MB86904",
932: },
933: /* LX */
934: {
935: .iommu_base = 0x10000000,
936: .tcx_base = 0x50000000,
937: .slavio_base = 0x70000000,
938: .ms_kb_base = 0x71000000,
939: .serial_base = 0x71100000,
940: .nvram_base = 0x71200000,
941: .fd_base = 0x71400000,
942: .counter_base = 0x71d00000,
943: .intctl_base = 0x71e00000,
944: .idreg_base = 0x78000000,
945: .dma_base = 0x78400000,
946: .esp_base = 0x78800000,
947: .le_base = 0x78c00000,
948: .aux1_base = 0x71900000,
949: .aux2_base = 0x71910000,
950: .vram_size = 0x00100000,
951: .nvram_size = 0x2000,
952: .esp_irq = 18,
953: .le_irq = 16,
954: .clock_irq = 7,
955: .clock1_irq = 19,
956: .ms_kb_irq = 14,
957: .ser_irq = 15,
958: .fd_irq = 22,
959: .me_irq = 30,
960: .nvram_machine_id = 0x80,
961: .machine_id = lx_id,
962: .iommu_version = 0x04000000,
963: .intbit_to_level = {
964: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
965: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
966: },
967: .max_mem = 0x10000000,
968: .default_cpu_model = "TI MicroSparc I",
969: },
970: /* SS-4 */
971: {
972: .iommu_base = 0x10000000,
973: .tcx_base = 0x50000000,
974: .cs_base = 0x6c000000,
975: .slavio_base = 0x70000000,
976: .ms_kb_base = 0x71000000,
977: .serial_base = 0x71100000,
978: .nvram_base = 0x71200000,
979: .fd_base = 0x71400000,
980: .counter_base = 0x71d00000,
981: .intctl_base = 0x71e00000,
982: .idreg_base = 0x78000000,
983: .dma_base = 0x78400000,
984: .esp_base = 0x78800000,
985: .le_base = 0x78c00000,
986: .apc_base = 0x6a000000,
987: .aux1_base = 0x71900000,
988: .aux2_base = 0x71910000,
989: .vram_size = 0x00100000,
990: .nvram_size = 0x2000,
991: .esp_irq = 18,
992: .le_irq = 16,
993: .clock_irq = 7,
994: .clock1_irq = 19,
995: .ms_kb_irq = 14,
996: .ser_irq = 15,
997: .fd_irq = 22,
998: .me_irq = 30,
999: .cs_irq = 5,
1000: .nvram_machine_id = 0x80,
1001: .machine_id = ss4_id,
1002: .iommu_version = 0x05000000,
1003: .intbit_to_level = {
1004: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1005: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1006: },
1007: .max_mem = 0x10000000,
1008: .default_cpu_model = "Fujitsu MB86904",
1009: },
1010: /* SPARCClassic */
1011: {
1012: .iommu_base = 0x10000000,
1013: .tcx_base = 0x50000000,
1014: .slavio_base = 0x70000000,
1015: .ms_kb_base = 0x71000000,
1016: .serial_base = 0x71100000,
1017: .nvram_base = 0x71200000,
1018: .fd_base = 0x71400000,
1019: .counter_base = 0x71d00000,
1020: .intctl_base = 0x71e00000,
1021: .idreg_base = 0x78000000,
1022: .dma_base = 0x78400000,
1023: .esp_base = 0x78800000,
1024: .le_base = 0x78c00000,
1025: .apc_base = 0x6a000000,
1026: .aux1_base = 0x71900000,
1027: .aux2_base = 0x71910000,
1028: .vram_size = 0x00100000,
1029: .nvram_size = 0x2000,
1030: .esp_irq = 18,
1031: .le_irq = 16,
1032: .clock_irq = 7,
1033: .clock1_irq = 19,
1034: .ms_kb_irq = 14,
1035: .ser_irq = 15,
1036: .fd_irq = 22,
1037: .me_irq = 30,
1038: .nvram_machine_id = 0x80,
1039: .machine_id = scls_id,
1040: .iommu_version = 0x05000000,
1041: .intbit_to_level = {
1042: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1043: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1044: },
1045: .max_mem = 0x10000000,
1046: .default_cpu_model = "TI MicroSparc I",
1047: },
1048: /* SPARCbook */
1049: {
1050: .iommu_base = 0x10000000,
1051: .tcx_base = 0x50000000, // XXX
1052: .slavio_base = 0x70000000,
1053: .ms_kb_base = 0x71000000,
1054: .serial_base = 0x71100000,
1055: .nvram_base = 0x71200000,
1056: .fd_base = 0x71400000,
1057: .counter_base = 0x71d00000,
1058: .intctl_base = 0x71e00000,
1059: .idreg_base = 0x78000000,
1060: .dma_base = 0x78400000,
1061: .esp_base = 0x78800000,
1062: .le_base = 0x78c00000,
1063: .apc_base = 0x6a000000,
1064: .aux1_base = 0x71900000,
1065: .aux2_base = 0x71910000,
1066: .vram_size = 0x00100000,
1067: .nvram_size = 0x2000,
1068: .esp_irq = 18,
1069: .le_irq = 16,
1070: .clock_irq = 7,
1071: .clock1_irq = 19,
1072: .ms_kb_irq = 14,
1073: .ser_irq = 15,
1074: .fd_irq = 22,
1075: .me_irq = 30,
1076: .nvram_machine_id = 0x80,
1077: .machine_id = sbook_id,
1078: .iommu_version = 0x05000000,
1079: .intbit_to_level = {
1080: 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1081: 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1082: },
1083: .max_mem = 0x10000000,
1084: .default_cpu_model = "TI MicroSparc I",
1.1.1.6 root 1085: },
1086: };
1087:
1088: /* SPARCstation 5 hardware initialisation */
1.1.1.8 root 1089: static void ss5_init(ram_addr_t RAM_size,
1.1.1.7 root 1090: const char *boot_device,
1.1.1.6 root 1091: const char *kernel_filename, const char *kernel_cmdline,
1092: const char *initrd_filename, const char *cpu_model)
1093: {
1.1.1.7 root 1094: sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1095: kernel_cmdline, initrd_filename, cpu_model);
1096: }
1097:
1098: /* SPARCstation 10 hardware initialisation */
1.1.1.8 root 1099: static void ss10_init(ram_addr_t RAM_size,
1.1.1.7 root 1100: const char *boot_device,
1.1.1.6 root 1101: const char *kernel_filename, const char *kernel_cmdline,
1102: const char *initrd_filename, const char *cpu_model)
1103: {
1.1.1.7 root 1104: sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1105: kernel_cmdline, initrd_filename, cpu_model);
1106: }
1107:
1108: /* SPARCserver 600MP hardware initialisation */
1.1.1.8 root 1109: static void ss600mp_init(ram_addr_t RAM_size,
1.1.1.7 root 1110: const char *boot_device,
1111: const char *kernel_filename,
1112: const char *kernel_cmdline,
1.1.1.6 root 1113: const char *initrd_filename, const char *cpu_model)
1114: {
1.1.1.7 root 1115: sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1116: kernel_cmdline, initrd_filename, cpu_model);
1117: }
1118:
1119: /* SPARCstation 20 hardware initialisation */
1.1.1.8 root 1120: static void ss20_init(ram_addr_t RAM_size,
1.1.1.7 root 1121: const char *boot_device,
1.1.1.6 root 1122: const char *kernel_filename, const char *kernel_cmdline,
1123: const char *initrd_filename, const char *cpu_model)
1124: {
1.1.1.7 root 1125: sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1126: kernel_cmdline, initrd_filename, cpu_model);
1127: }
1128:
1.1.1.7 root 1129: /* SPARCstation Voyager hardware initialisation */
1.1.1.8 root 1130: static void vger_init(ram_addr_t RAM_size,
1.1.1.7 root 1131: const char *boot_device,
1132: const char *kernel_filename, const char *kernel_cmdline,
1133: const char *initrd_filename, const char *cpu_model)
1134: {
1135: sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1136: kernel_cmdline, initrd_filename, cpu_model);
1137: }
1138:
1139: /* SPARCstation LX hardware initialisation */
1.1.1.8 root 1140: static void ss_lx_init(ram_addr_t RAM_size,
1.1.1.7 root 1141: const char *boot_device,
1142: const char *kernel_filename, const char *kernel_cmdline,
1143: const char *initrd_filename, const char *cpu_model)
1144: {
1145: sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1146: kernel_cmdline, initrd_filename, cpu_model);
1147: }
1148:
1149: /* SPARCstation 4 hardware initialisation */
1.1.1.8 root 1150: static void ss4_init(ram_addr_t RAM_size,
1.1.1.7 root 1151: const char *boot_device,
1.1.1.6 root 1152: const char *kernel_filename, const char *kernel_cmdline,
1153: const char *initrd_filename, const char *cpu_model)
1154: {
1.1.1.7 root 1155: sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1156: kernel_cmdline, initrd_filename, cpu_model);
1157: }
1158:
1159: /* SPARCClassic hardware initialisation */
1.1.1.8 root 1160: static void scls_init(ram_addr_t RAM_size,
1.1.1.7 root 1161: const char *boot_device,
1162: const char *kernel_filename, const char *kernel_cmdline,
1163: const char *initrd_filename, const char *cpu_model)
1164: {
1165: sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1166: kernel_cmdline, initrd_filename, cpu_model);
1167: }
1168:
1169: /* SPARCbook hardware initialisation */
1.1.1.8 root 1170: static void sbook_init(ram_addr_t RAM_size,
1.1.1.7 root 1171: const char *boot_device,
1172: const char *kernel_filename, const char *kernel_cmdline,
1173: const char *initrd_filename, const char *cpu_model)
1174: {
1175: sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1176: kernel_cmdline, initrd_filename, cpu_model);
1177: }
1178:
1.1.1.8 root 1179: static QEMUMachine ss5_machine = {
1.1.1.7 root 1180: .name = "SS-5",
1181: .desc = "Sun4m platform, SPARCstation 5",
1182: .init = ss5_init,
1183: .use_scsi = 1,
1.1.1.8 root 1184: .is_default = 1,
1.1.1.6 root 1185: };
1186:
1.1.1.8 root 1187: static QEMUMachine ss10_machine = {
1.1.1.7 root 1188: .name = "SS-10",
1189: .desc = "Sun4m platform, SPARCstation 10",
1190: .init = ss10_init,
1191: .use_scsi = 1,
1192: .max_cpus = 4,
1.1.1.6 root 1193: };
1194:
1.1.1.8 root 1195: static QEMUMachine ss600mp_machine = {
1.1.1.7 root 1196: .name = "SS-600MP",
1197: .desc = "Sun4m platform, SPARCserver 600MP",
1198: .init = ss600mp_init,
1199: .use_scsi = 1,
1200: .max_cpus = 4,
1.1.1.6 root 1201: };
1202:
1.1.1.8 root 1203: static QEMUMachine ss20_machine = {
1.1.1.7 root 1204: .name = "SS-20",
1205: .desc = "Sun4m platform, SPARCstation 20",
1206: .init = ss20_init,
1207: .use_scsi = 1,
1208: .max_cpus = 4,
1.1.1.6 root 1209: };
1210:
1.1.1.8 root 1211: static QEMUMachine voyager_machine = {
1.1.1.7 root 1212: .name = "Voyager",
1213: .desc = "Sun4m platform, SPARCstation Voyager",
1214: .init = vger_init,
1215: .use_scsi = 1,
1216: };
1217:
1.1.1.8 root 1218: static QEMUMachine ss_lx_machine = {
1.1.1.7 root 1219: .name = "LX",
1220: .desc = "Sun4m platform, SPARCstation LX",
1221: .init = ss_lx_init,
1222: .use_scsi = 1,
1223: };
1224:
1.1.1.8 root 1225: static QEMUMachine ss4_machine = {
1.1.1.7 root 1226: .name = "SS-4",
1227: .desc = "Sun4m platform, SPARCstation 4",
1228: .init = ss4_init,
1229: .use_scsi = 1,
1230: };
1231:
1.1.1.8 root 1232: static QEMUMachine scls_machine = {
1.1.1.7 root 1233: .name = "SPARCClassic",
1234: .desc = "Sun4m platform, SPARCClassic",
1235: .init = scls_init,
1236: .use_scsi = 1,
1237: };
1238:
1.1.1.8 root 1239: static QEMUMachine sbook_machine = {
1.1.1.7 root 1240: .name = "SPARCbook",
1241: .desc = "Sun4m platform, SPARCbook",
1242: .init = sbook_init,
1243: .use_scsi = 1,
1.1.1.6 root 1244: };
1245:
1246: static const struct sun4d_hwdef sun4d_hwdefs[] = {
1247: /* SS-1000 */
1248: {
1249: .iounit_bases = {
1250: 0xfe0200000ULL,
1251: 0xfe1200000ULL,
1252: 0xfe2200000ULL,
1253: 0xfe3200000ULL,
1254: -1,
1255: },
1256: .tcx_base = 0x820000000ULL,
1257: .slavio_base = 0xf00000000ULL,
1258: .ms_kb_base = 0xf00240000ULL,
1259: .serial_base = 0xf00200000ULL,
1260: .nvram_base = 0xf00280000ULL,
1261: .counter_base = 0xf00300000ULL,
1262: .espdma_base = 0x800081000ULL,
1263: .esp_base = 0x800080000ULL,
1264: .ledma_base = 0x800040000ULL,
1265: .le_base = 0x800060000ULL,
1266: .sbi_base = 0xf02800000ULL,
1267: .vram_size = 0x00100000,
1268: .nvram_size = 0x2000,
1269: .esp_irq = 3,
1270: .le_irq = 4,
1271: .clock_irq = 14,
1272: .clock1_irq = 10,
1273: .ms_kb_irq = 12,
1274: .ser_irq = 12,
1.1.1.7 root 1275: .nvram_machine_id = 0x80,
1276: .machine_id = ss1000_id,
1.1.1.6 root 1277: .iounit_version = 0x03000000,
1.1.1.7 root 1278: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1279: .default_cpu_model = "TI SuperSparc II",
1280: },
1281: /* SS-2000 */
1282: {
1283: .iounit_bases = {
1284: 0xfe0200000ULL,
1285: 0xfe1200000ULL,
1286: 0xfe2200000ULL,
1287: 0xfe3200000ULL,
1288: 0xfe4200000ULL,
1289: },
1290: .tcx_base = 0x820000000ULL,
1291: .slavio_base = 0xf00000000ULL,
1292: .ms_kb_base = 0xf00240000ULL,
1293: .serial_base = 0xf00200000ULL,
1294: .nvram_base = 0xf00280000ULL,
1295: .counter_base = 0xf00300000ULL,
1296: .espdma_base = 0x800081000ULL,
1297: .esp_base = 0x800080000ULL,
1298: .ledma_base = 0x800040000ULL,
1299: .le_base = 0x800060000ULL,
1300: .sbi_base = 0xf02800000ULL,
1301: .vram_size = 0x00100000,
1302: .nvram_size = 0x2000,
1303: .esp_irq = 3,
1304: .le_irq = 4,
1305: .clock_irq = 14,
1306: .clock1_irq = 10,
1307: .ms_kb_irq = 12,
1308: .ser_irq = 12,
1.1.1.7 root 1309: .nvram_machine_id = 0x80,
1310: .machine_id = ss2000_id,
1.1.1.6 root 1311: .iounit_version = 0x03000000,
1.1.1.7 root 1312: .max_mem = 0xf00000000ULL,
1.1.1.6 root 1313: .default_cpu_model = "TI SuperSparc II",
1314: },
1315: };
1316:
1.1.1.7 root 1317: static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1.1.1.6 root 1318: const char *boot_device,
1.1.1.7 root 1319: const char *kernel_filename,
1.1.1.6 root 1320: const char *kernel_cmdline,
1321: const char *initrd_filename, const char *cpu_model)
1322: {
1.1.1.8 root 1323: CPUState *envs[MAX_CPUS];
1.1.1.6 root 1324: unsigned int i;
1.1.1.8 root 1325: void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
1.1.1.6 root 1326: qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1.1.1.8 root 1327: espdma_irq, ledma_irq;
1.1.1.6 root 1328: qemu_irq *esp_reset, *le_reset;
1.1.1.7 root 1329: unsigned long kernel_size;
1330: void *fw_cfg;
1.1.1.6 root 1331:
1332: /* init CPUs */
1333: if (!cpu_model)
1334: cpu_model = hwdef->default_cpu_model;
1335:
1.1.1.8 root 1336: for(i = 0; i < smp_cpus; i++) {
1337: envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1.1.1.6 root 1338: }
1339:
1340: for (i = smp_cpus; i < MAX_CPUS; i++)
1341: cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1342:
1.1.1.8 root 1343: /* set up devices */
1344: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.6 root 1345:
1.1.1.8 root 1346: prom_init(hwdef->slavio_base, bios_name);
1.1.1.6 root 1347:
1348: sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1349:
1350: for (i = 0; i < MAX_IOUNITS; i++)
1351: if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1352: iounits[i] = iommu_init(hwdef->iounit_bases[i],
1353: hwdef->iounit_version,
1354: sbi_irq[hwdef->me_irq]);
1355:
1356: espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1357: iounits[0], &espdma_irq, &esp_reset);
1358:
1359: ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1360: iounits[0], &ledma_irq, &le_reset);
1361:
1362: if (graphic_depth != 8 && graphic_depth != 24) {
1363: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1364: exit (1);
1365: }
1.1.1.8 root 1366: tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1367: graphic_depth);
1.1.1.6 root 1368:
1.1.1.8 root 1369: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1.1.1.6 root 1370:
1371: nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1372: hwdef->nvram_size, 8);
1373:
1374: slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1375: sbi_cpu_irq, smp_cpus);
1376:
1377: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1.1.1.8 root 1378: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1.1.6 root 1379: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1380: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1.1.1.7 root 1381: escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1382: serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1.1.1.6 root 1383:
1384: if (drive_get_max_bus(IF_SCSI) > 0) {
1385: fprintf(stderr, "qemu: too many SCSI bus\n");
1386: exit(1);
1387: }
1388:
1.1.1.8 root 1389: esp_init(hwdef->esp_base, 2,
1390: espdma_memory_read, espdma_memory_write,
1391: espdma, espdma_irq, esp_reset);
1.1.1.6 root 1392:
1.1.1.7 root 1393: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1394: RAM_size);
1.1.1.6 root 1395:
1396: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1397: boot_device, RAM_size, kernel_size, graphic_width,
1.1.1.7 root 1398: graphic_height, graphic_depth, hwdef->nvram_machine_id,
1399: "Sun4d");
1400:
1401: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1402: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1403: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1404: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1.1.1.8 root 1405: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1406: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1407: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1408: if (kernel_cmdline) {
1409: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1410: pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1411: } else {
1412: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1413: }
1414: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1415: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1416: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1417: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.6 root 1418: }
1419:
1420: /* SPARCserver 1000 hardware initialisation */
1.1.1.8 root 1421: static void ss1000_init(ram_addr_t RAM_size,
1.1.1.7 root 1422: const char *boot_device,
1.1.1.6 root 1423: const char *kernel_filename, const char *kernel_cmdline,
1424: const char *initrd_filename, const char *cpu_model)
1425: {
1.1.1.7 root 1426: sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1427: kernel_cmdline, initrd_filename, cpu_model);
1.1 root 1428: }
1429:
1.1.1.6 root 1430: /* SPARCcenter 2000 hardware initialisation */
1.1.1.8 root 1431: static void ss2000_init(ram_addr_t RAM_size,
1.1.1.7 root 1432: const char *boot_device,
1.1.1.6 root 1433: const char *kernel_filename, const char *kernel_cmdline,
1434: const char *initrd_filename, const char *cpu_model)
1435: {
1.1.1.7 root 1436: sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1.1.1.6 root 1437: kernel_cmdline, initrd_filename, cpu_model);
1438: }
1439:
1.1.1.8 root 1440: static QEMUMachine ss1000_machine = {
1.1.1.7 root 1441: .name = "SS-1000",
1442: .desc = "Sun4d platform, SPARCserver 1000",
1443: .init = ss1000_init,
1444: .use_scsi = 1,
1445: .max_cpus = 8,
1.1.1.6 root 1446: };
1447:
1.1.1.8 root 1448: static QEMUMachine ss2000_machine = {
1.1.1.7 root 1449: .name = "SS-2000",
1450: .desc = "Sun4d platform, SPARCcenter 2000",
1451: .init = ss2000_init,
1452: .use_scsi = 1,
1453: .max_cpus = 20,
1454: };
1455:
1456: static const struct sun4c_hwdef sun4c_hwdefs[] = {
1457: /* SS-2 */
1458: {
1459: .iommu_base = 0xf8000000,
1460: .tcx_base = 0xfe000000,
1461: .slavio_base = 0xf6000000,
1462: .intctl_base = 0xf5000000,
1463: .counter_base = 0xf3000000,
1464: .ms_kb_base = 0xf0000000,
1465: .serial_base = 0xf1000000,
1466: .nvram_base = 0xf2000000,
1467: .fd_base = 0xf7200000,
1468: .dma_base = 0xf8400000,
1469: .esp_base = 0xf8800000,
1470: .le_base = 0xf8c00000,
1471: .aux1_base = 0xf7400003,
1472: .vram_size = 0x00100000,
1473: .nvram_size = 0x800,
1474: .esp_irq = 2,
1475: .le_irq = 3,
1476: .clock_irq = 5,
1477: .clock1_irq = 7,
1478: .ms_kb_irq = 1,
1479: .ser_irq = 1,
1480: .fd_irq = 1,
1481: .me_irq = 1,
1482: .nvram_machine_id = 0x55,
1483: .machine_id = ss2_id,
1484: .max_mem = 0x10000000,
1485: .default_cpu_model = "Cypress CY7C601",
1486: },
1487: };
1488:
1489: static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1490: const char *boot_device,
1491: const char *kernel_filename,
1492: const char *kernel_cmdline,
1493: const char *initrd_filename, const char *cpu_model)
1494: {
1495: CPUState *env;
1.1.1.8 root 1496: void *iommu, *espdma, *ledma, *nvram;
1497: qemu_irq *cpu_irqs, *slavio_irq, espdma_irq, ledma_irq;
1.1.1.7 root 1498: qemu_irq *esp_reset, *le_reset;
1.1.1.8 root 1499: qemu_irq fdc_tc;
1.1.1.7 root 1500: unsigned long kernel_size;
1501: BlockDriverState *fd[MAX_FD];
1502: int drive_index;
1503: void *fw_cfg;
1504:
1505: /* init CPU */
1506: if (!cpu_model)
1507: cpu_model = hwdef->default_cpu_model;
1508:
1.1.1.8 root 1509: env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1.1.1.7 root 1510:
1.1.1.8 root 1511: /* set up devices */
1512: ram_init(0, RAM_size, hwdef->max_mem);
1.1.1.7 root 1513:
1.1.1.8 root 1514: prom_init(hwdef->slavio_base, bios_name);
1.1.1.7 root 1515:
1516: slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1517: &slavio_irq, cpu_irqs);
1518:
1519: iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1520: slavio_irq[hwdef->me_irq]);
1521:
1522: espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1523: iommu, &espdma_irq, &esp_reset);
1524:
1525: ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1526: slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1527: &le_reset);
1528:
1529: if (graphic_depth != 8 && graphic_depth != 24) {
1530: fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1531: exit (1);
1532: }
1.1.1.8 root 1533: tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1534: graphic_depth);
1.1.1.7 root 1535:
1.1.1.8 root 1536: lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1.1.1.7 root 1537:
1538: nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1539: hwdef->nvram_size, 2);
1540:
1541: slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1.1.1.8 root 1542: display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1.1.1.7 root 1543: // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1544: // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1545: escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1546: slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1547: ESCC_CLOCK, 1);
1548:
1.1.1.8 root 1549: slavio_misc = slavio_misc_init(0, hwdef->aux1_base, 0,
1550: slavio_irq[hwdef->me_irq], fdc_tc);
1.1.1.7 root 1551:
1552: if (hwdef->fd_base != (target_phys_addr_t)-1) {
1553: /* there is zero or one floppy drive */
1554: memset(fd, 0, sizeof(fd));
1555: drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1556: if (drive_index != -1)
1557: fd[0] = drives_table[drive_index].bdrv;
1558:
1559: sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1.1.1.8 root 1560: &fdc_tc);
1.1.1.7 root 1561: }
1562:
1563: if (drive_get_max_bus(IF_SCSI) > 0) {
1564: fprintf(stderr, "qemu: too many SCSI bus\n");
1565: exit(1);
1566: }
1567:
1.1.1.8 root 1568: esp_init(hwdef->esp_base, 2,
1569: espdma_memory_read, espdma_memory_write,
1570: espdma, espdma_irq, esp_reset);
1.1.1.7 root 1571:
1572: kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1573: RAM_size);
1574:
1575: nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1576: boot_device, RAM_size, kernel_size, graphic_width,
1577: graphic_height, graphic_depth, hwdef->nvram_machine_id,
1578: "Sun4c");
1579:
1580: fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1581: fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1582: fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1583: fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1.1.1.8 root 1584: fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1585: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1586: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1587: if (kernel_cmdline) {
1588: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1589: pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1590: } else {
1591: fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1592: }
1593: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1594: fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1595: fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1596: qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1.1.1.7 root 1597: }
1598:
1599: /* SPARCstation 2 hardware initialisation */
1.1.1.8 root 1600: static void ss2_init(ram_addr_t RAM_size,
1.1.1.7 root 1601: const char *boot_device,
1602: const char *kernel_filename, const char *kernel_cmdline,
1603: const char *initrd_filename, const char *cpu_model)
1604: {
1605: sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1606: kernel_cmdline, initrd_filename, cpu_model);
1607: }
1608:
1.1.1.8 root 1609: static QEMUMachine ss2_machine = {
1.1.1.7 root 1610: .name = "SS-2",
1611: .desc = "Sun4c platform, SPARCstation 2",
1612: .init = ss2_init,
1613: .use_scsi = 1,
1.1 root 1614: };
1.1.1.8 root 1615:
1616: static void ss2_machine_init(void)
1617: {
1618: qemu_register_machine(&ss5_machine);
1619: qemu_register_machine(&ss10_machine);
1620: qemu_register_machine(&ss600mp_machine);
1621: qemu_register_machine(&ss20_machine);
1622: qemu_register_machine(&voyager_machine);
1623: qemu_register_machine(&ss_lx_machine);
1624: qemu_register_machine(&ss4_machine);
1625: qemu_register_machine(&scls_machine);
1626: qemu_register_machine(&sbook_machine);
1627: qemu_register_machine(&ss1000_machine);
1628: qemu_register_machine(&ss2000_machine);
1629: qemu_register_machine(&ss2_machine);
1630: }
1631:
1632: machine_init(ss2_machine_init);
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